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From: cvs at opencores.org<cvs@o...>
Date: Mon Apr 28 10:15:26 CEST 2008
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/08/04 28:10:15

Modified: aemb/rtl/verilog aeMB2_bsft.v aeMB2_ctrl.v aeMB2_intu.v
aeMB2_mult.v
Log:
Optimisations.


Revision Changes Path
1.3 aemb/rtl/verilog/aeMB2_bsft.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_bsft.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB2_bsft.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_bsft.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- aeMB2_bsft.v 26 Apr 2008 01:09:05 -0000 1.2
+++ aeMB2_bsft.v 28 Apr 2008 08:15:25 -0000 1.3
@@ -1,4 +1,4 @@
-/* $Id: aeMB2_bsft.v,v 1.2 2008/04/26 01:09:05 sybreon Exp $
+/* $Id: aeMB2_bsft.v,v 1.3 2008/04/28 08:15:25 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@a...>
@@ -27,6 +27,8 @@

*/

+// 420 LUTS
+
module aeMB2_bsft (/*AUTOARG*/
// Outputs
bsf_mx,
@@ -57,8 +59,6 @@
wire [31:0] wOPB = opb_of;
wire [31:0] wOPA = opa_of;

- assign bsf_mx = (AEMB_BSF[0]) ? rBSR : 32'hX;
-
// STAGE-1 SHIFTERS

// logical
@@ -135,10 +135,15 @@
imm_ex <= #1 imm_of[10:9]; // delay 1 cycle
end

+ assign bsf_mx = (AEMB_BSF[0]) ? rBSR : 32'hX;
+
endmodule // aeMB2_bsft

/*
$Log: aeMB2_bsft.v,v $
+ Revision 1.3 2008/04/28 08:15:25 sybreon
+ Optimisations.
+
Revision 1.2 2008/04/26 01:09:05 sybreon
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.




1.5 aemb/rtl/verilog/aeMB2_ctrl.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_ctrl.v.diff?r1=1.4&r2=1.5

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB2_ctrl.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_ctrl.v,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- aeMB2_ctrl.v 26 Apr 2008 17:57:43 -0000 1.4
+++ aeMB2_ctrl.v 28 Apr 2008 08:15:25 -0000 1.5
@@ -1,4 +1,4 @@
-/* $Id: aeMB2_ctrl.v,v 1.4 2008/04/26 17:57:43 sybreon Exp $
+/* $Id: aeMB2_ctrl.v,v 1.5 2008/04/28 08:15:25 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@a...>
@@ -100,28 +100,28 @@

// decode main opgroups

- wire fSFT = (wOPC == 6'o44);
- wire fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
+ //wire fSFT = (wOPC == 6'o44);
+ //wire fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
- wire fDIV = (wOPC == 6'o22);
+ //wire fDIV = (wOPC == 6'o22);
wire fRTD = (wOPC == 6'o55);
wire fBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
wire fBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
- wire fBRA = fBRU & wRA[3];
+ //wire fBRA = fBRU & wRA[3]; wire fIMM = (wOPC == 6'o54); wire fMOV = (wOPC == 6'o45); wire fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6); wire fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7); - wire fLDST = (wOPC[5:4] == 2'o3); - wire fPUT = (wOPC == 6'o33) & wRB[4]; + //wire fLDST = (wOPC[5:4] == 2'o3); + //wire fPUT = (wOPC == 6'o33) & wRB[4]; wire fGET = (wOPC == 6'o33) & !wRB[4]; // control signals - wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20 - wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10 - wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall + //wire [31:0] wXCEOP = 32'hBA2D0020; // Vector 0x20 + //wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10 + //wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall localparam [2:0] MUX_SFR = 3'o7, MUX_BSF = 3'o6, @@ -145,18 +145,16 @@ end else if (dena) begin mux_of <= #1 - (hzd_bpc | hzd_fwd) ? MUX_NOP : + (hzd_bpc | hzd_fwd | fSTR | fRTD | fBCC) ? MUX_NOP : + (fLOD | fGET) ? MUX_MEM : (fMOV) ? MUX_SFR : (fMUL) ? MUX_MUL : (fBSF) ? MUX_BSF : - (fLOD | fGET) ? MUX_MEM : (fBRU) ? MUX_RPC : - (fSTR | fRTD | fBCC) ? MUX_NOP : - (|wRD) ? MUX_ALU : - MUX_NOP; + MUX_ALU; opc_of <= #1 - (hzd_bpc | hzd_fwd) ? 6'o42 : + (hzd_bpc | hzd_fwd) ? 6'o42 : // XOR (SKIP) wOPC; rd_of <= #1 wRD; @@ -201,16 +199,16 @@ wire opb_fwd, opa_fwd, opd_fwd; assign mux_opb = {wOPC[3], opb_fwd}; - assign opb_fwd = ~|(wRB ^ rd_ex) & // RB forwarding needed + assign opb_fwd = ((wRB ^ rd_ex) == 5'd0) & // RB forwarding needed fwd_ex & wrb_ex; assign mux_opa = {(fBRU|fBCC), opa_fwd}; - assign opa_fwd = ~|(wRA ^ rd_ex) & // RA forwarding needed + assign opa_fwd = ((wRA ^ rd_ex) == 5'd0) & // RA forwarding needed fwd_ex & wrb_ex; assign mux_opd = {fBCC, opd_fwd}; - assign opd_fwd = (( ~|(wRA ^ rd_ex) & fBCC) | - ( ~|(wRD ^ rd_ex) & fSTR)) & + assign opd_fwd = (( ((wRA ^ rd_ex) == 5'd0) & fBCC) | // RA forwarding + ( ((wRD ^ rd_ex) == 5'd0) & fSTR)) & // RD forwarding fwd_ex & wrb_ex; always @(posedge gclk) @@ -267,10 +265,10 @@ end // if (dena) // Hazard Detection - wire wFMUL = (mux_ex == MUX_MUL); - wire wFBSF = (mux_ex == MUX_BSF); - wire wFMEM = (mux_ex == MUX_MEM); - wire wFMOV = (mux_ex == MUX_SFR); + //wire wFMUL = (mux_ex == MUX_MUL); + //wire wFBSF = (mux_ex == MUX_BSF); + //wire wFMEM = (mux_ex == MUX_MEM); + //wire wFMOV = (mux_ex == MUX_SFR); assign hzd_fwd = (opd_fwd | opa_fwd | opb_fwd) & mux_ex[2]; //(wFMUL | wFBSF | wFMEM | wFMOV); @@ -280,6 +278,9 @@ /* $Log: aeMB2_ctrl.v,v $ + Revision 1.5 2008/04/28 08:15:25 sybreon + Optimisations. + Revision 1.4 2008/04/26 17:57:43 sybreon Minor performance improvements. 1.6 aemb/rtl/verilog/aeMB2_intu.v http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_intu.v.diff?r1=1.5&r2=1.6 (In the diff below, changes in quantity of whitespace are not shown.) Index: aeMB2_intu.v =================================================================== RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_intu.v,v retrieving revision 1.5 retrieving revision 1.6 diff -u -b -r1.5 -r1.6 --- aeMB2_intu.v 26 Apr 2008 17:57:43 -0000 1.5 +++ aeMB2_intu.v 28 Apr 2008 08:15:25 -0000 1.6 @@ -1,4 +1,4 @@ -/* $Id: aeMB2_intu.v,v 1.5 2008/04/26 17:57:43 sybreon Exp $ +/* $Id: aeMB2_intu.v,v 1.6 2008/04/28 08:15:25 sybreon Exp $ ** ** AEMB2 EDK 6.2 COMPATIBLE CORE ** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@a...> @@ -44,6 +44,7 @@ output [31:0] alu_ex, alu_mx; + //input [2:0] mux_of; input [5:0] opc_of; input [31:0] opa_of; input [31:0] opb_of; @@ -69,21 +70,26 @@ reg [31:0] sfr_mx; // End of automatics + localparam [2:0] MUX_SFR = 3'o7, + MUX_BSF = 3'o6, + MUX_MUL = 3'o5, + MUX_MEM = 3'o4, + + MUX_RPC = 3'o2, + MUX_ALU = 3'o1, + MUX_NOP = 3'o0; + reg rMSR_C, rMSR_CC, - rMSR_C0, rMSR_C1, rMSR_MTX, - rMSR_DCE, - rMSR_ICE, + rMSR_DTE, + rMSR_ITE, rMSR_BIP, rMSR_IE, rMSR_BE; - // ADDER - /* Infer a ADD cell because ADD/SUB cannot be inferred cross - technologies. */ - - // FIXME: Redesign this critical path + // Infer a ADD with carry cell because ADDSUB cannot be inferred + // across technologies. reg [31:0] add_ex; reg add_c; @@ -91,26 +97,25 @@ wire [31:0] wADD; wire wADC; - wire fCCC = !opc_of[5] & !opc_of[4] & opc_of[1]; - wire fSUB = !opc_of[5] & !opc_of[4] & opc_of[0]; - wire fCMP = !opc_of[3] & imm_of[1] & imm_of[0]; // unsigned + wire fCCC = !opc_of[5] & opc_of[1]; // & !opc_of[4] + wire fSUB = !opc_of[5] & opc_of[0]; // & !opc_of[4] + wire fCMP = !opc_of[3] & imm_of[1]; // & imm_of[0]; // unsigned wire wCMP = (fCMP) ? (opa_of > opb_of) : wADD[31]; wire [31:0] wOPA = (fSUB) ? ~opa_of : opa_of; wire wOPC = (fCCC) ? rMSR_CC : fSUB; - assign {wADC, wADD} = (opb_of + wOPA) + wOPC; + assign {wADC, wADD} = (opb_of + wOPA) + wOPC; // add carry - always @(/*AUTOSENSE*/imm_of or opc_of or wADC or wADD or wCMP) begin - {add_c, add_ex} <= #1 - (!opc_of[3] & imm_of[0]) ? - {wADC, wCMP , wADD[30:0]} : // add with carry - {wADC, wADD[31:0]} ; // add with carry + always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin + {add_c, add_ex} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry + //(!opc_of[3] & imm_of[0]) ? + //{wADC, wCMP , wADD[30:0]} : // add with carry + //{wADC, wADD[31:0]} ; // add with carry end // SHIFT/LOGIC/MOVE reg [31:0] slm_ex; - reg slm_c; always @(/*AUTOSENSE*/imm_of or opa_of or opb_of or opc_of or rMSR_CC) @@ -136,9 +141,6 @@ default: slm_ex <= #1 32'hX; endcase // case (opc_of[2:0]) - always @(/*AUTOSENSE*/imm_of or opa_of or rMSR_CC) - slm_c <= #1 (&imm_of[6:5]) ? rMSR_CC : opa_of[0]; - // ALU RESULT always @(posedge gclk) if (grst) begin @@ -172,8 +174,8 @@ 30 - HTE (hardware thread enabled) 29 - PHA (current phase) - 7 - DCE (data cache enable) - 5 - ICE (instruction cache enable) + 7 - DTE (data cache enable) + 5 - ITE (instruction cache enable) 4 - MTX (hardware mutex bit) 3 - BIP (break in progress) 2 - C (carry flag) @@ -182,9 +184,9 @@ */ assign msr_ex = { - rMSR_DCE, + rMSR_DTE, 1'b0, - rMSR_ICE, + rMSR_ITE, rMSR_MTX, rMSR_BIP, rMSR_C, @@ -207,8 +209,9 @@ wire fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD); wire fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC); - //wire fMOV = (opc_of == 6'o45); - wire fMOV = opc_of[5] & !opc_of[4] & !opc_of[3] & opc_of[2] & !opc_of[1] & opc_of[0]; + wire fMOV = (opc_of == 6'o45); + //wire fMOV = opc_of[5] & !opc_of[4] & !opc_of[3] & opc_of[2] & !opc_of[1] & opc_of[0]; + //wire fMOV = ({!opc_of[5], opc_of[4:3], !opc_of[2], opc_of[1], !opc_of[0]} == 6'd0); wire fMTS = fMOV & &imm_of[15:14]; wire fMOP = fMOV & ~|imm_of[15:14]; @@ -220,9 +223,9 @@ // Beginning of autoreset for uninitialized flops rMSR_BE <= 1'h0; rMSR_BIP <= 1'h0; - rMSR_DCE <= 1'h0; - rMSR_ICE <= 1'h0; + rMSR_DTE <= 1'h0; rMSR_IE <= 1'h0; + rMSR_ITE <= 1'h0; rMSR_MTX <= 1'h0; sfr_ex <= 32'h0; sfr_mx <= 32'h0; @@ -234,9 +237,9 @@ AEMB_HTX[0], gpha, 21'd0, - rMSR_DCE, + rMSR_DTE, 1'b0, - rMSR_ICE, + rMSR_ITE, rMSR_MTX, rMSR_BIP, rMSR_CC, @@ -244,15 +247,15 @@ rMSR_BE }; /* - rMSR_DCE <= #1 + rMSR_DTE <= #1 (fMTS) ? opa_of[7] : (fMOP) ? wRES[7] : - rMSR_DCE; + rMSR_DTE; - rMSR_ICE <= #1 + rMSR_ITE <= #1 (fMTS) ? opa_of[5] : (fMOP) ? wRES[5] : - rMSR_ICE; + rMSR_ITE; rMSR_MTX <= #1 (fMTS) ? opa_of[4] : @@ -266,25 +269,25 @@ */ case ({fMTS, fMOP}) - 2'o2: {rMSR_DCE, - rMSR_ICE, + 2'o2: {rMSR_DTE, + rMSR_ITE, rMSR_MTX, rMSR_BE} <= #1 {opa_of[7], opa_of[5], opa_of[4], opa_of[0]}; - 2'o1: {rMSR_DCE, - rMSR_ICE, + 2'o1: {rMSR_DTE, + rMSR_ITE, rMSR_MTX, rMSR_BE} <= #1 {wRES[7], wRES[5], wRES[4], wRES[0]}; - default: {rMSR_DCE, - rMSR_ICE, + default: {rMSR_DTE, + rMSR_ITE, rMSR_MTX, - rMSR_BE} <= #1 {rMSR_DCE, - rMSR_ICE, + rMSR_BE} <= #1 {rMSR_DTE, + rMSR_ITE, rMSR_MTX, rMSR_BE}; endcase // case ({fMTS, fMOP}) @@ -350,6 +353,9 @@ /* $Log: aeMB2_intu.v,v $ + Revision 1.6 2008/04/28 08:15:25 sybreon + Optimisations. + Revision 1.5 2008/04/26 17:57:43 sybreon Minor performance improvements. 1.5 aemb/rtl/verilog/aeMB2_mult.v http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_mult.v.diff?r1=1.4&r2=1.5 (In the diff below, changes in quantity of whitespace are not shown.) Index: aeMB2_mult.v =================================================================== RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_mult.v,v retrieving revision 1.4 retrieving revision 1.5 diff -u -b -r1.4 -r1.5 --- aeMB2_mult.v 26 Apr 2008 17:57:43 -0000 1.4 +++ aeMB2_mult.v 28 Apr 2008 08:15:25 -0000 1.5 @@ -1,4 +1,4 @@ -/* $Id: aeMB2_mult.v,v 1.4 2008/04/26 17:57:43 sybreon Exp $ +/* $Id: aeMB2_mult.v,v 1.5 2008/04/28 08:15:25 sybreon Exp $ ** ** AEMB2 EDK 6.2 COMPATIBLE CORE ** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@a...> @@ -28,6 +28,8 @@ */ +// 30 LUTS @ 20 MHZ + module aeMB2_mult (/*AUTOARG*/ // Outputs mul_mx, @@ -71,12 +73,15 @@ rOPB <= #1 opb_of; end - assign mul_mx = rMUL1; + assign mul_mx = (AEMB_MUL[0]) ? rMUL1 : 32'hX; endmodule // aeMB2_mult /* $Log: aeMB2_mult.v,v $ + Revision 1.5 2008/04/28 08:15:25 sybreon + Optimisations. + Revision 1.4 2008/04/26 17:57:43 sybreon Minor performance improvements.