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Message
From: cvs at opencores.org<cvs@o...>
Date: Sun Apr 27 18:41:46 CEST 2008
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/08/04 27:18:41 Modified: aemb/rtl/verilog aeMB2_xslif.v
Log:
Disconnect from pipeline.
Revision Changes Path
1.7 aemb/rtl/verilog/aeMB2_xslif.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_xslif.v.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB2_xslif.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_xslif.v,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- aeMB2_xslif.v 27 Apr 2008 16:04:12 -0000 1.6
+++ aeMB2_xslif.v 27 Apr 2008 16:41:46 -0000 1.7
@@ -1,4 +1,4 @@
-/* $Id: aeMB2_xslif.v,v 1.6 2008/04/27 16:04:12 sybreon Exp $
+/* $Id: aeMB2_xslif.v,v 1.7 2008/04/27 16:41:46 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@a...>
@@ -97,7 +97,9 @@
xwb_dat_o <= #1 opa_of; // Latch output
- xwb_mx <= #1 (xwb_ack_i) ? xwb_dat_i : xwb_lat; // Latch input
+ xwb_mx <= #1 (xwb_ack_i) ?
+ xwb_dat_i : // stalled from XWB
+ xwb_lat; // Latch earlier
end // if (dena)
@@ -112,7 +114,7 @@
// Beginning of autoreset for uninitialized flops
xwb_lat <= 32'h0;
// End of automatics
- end else if (xwb_stb_o) begin
+ end else if (xwb_ack_i) begin
xwb_lat <= #1 xwb_dat_i;
end
@@ -123,7 +125,7 @@
xBLK <= 1'h0;
xwb_stb_o <= 1'h0;
// End of automatics
- end else if (dena) begin
+ end else if (xwb_fb) begin
xBLK <= #1 imm_of[14]; // nGET/nPUT
xwb_stb_o <= #1 (dena) ? !opc_of[5] & opc_of[4] & opc_of[3] & opc_of[1] : // GET/PUT
(xwb_stb_o & !xwb_ack_i);
@@ -136,6 +138,9 @@
/*
$Log: aeMB2_xslif.v,v $
+ Revision 1.7 2008/04/27 16:41:46 sybreon
+ Disconnect from pipeline.
+
Revision 1.6 2008/04/27 16:04:12 sybreon
Fixed minor typos.
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