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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Mon Mar 17 00:05:33 CET 2008
    Subject: [cvs-checkins] MODIFIED: r2000 ...
    Top
    Date: 00/08/03 17:00:05

    Modified: r2000/r2000pl/rtl/verilog/r2000 define.h r2000_cp0.v
    r2000_cpu_pipe.v
    Log:
    - when freeze or stall; don't let memory operations

    - Modification on the CP0

    - The CP0 is deplaced in the WB stage

    - The INT, SI event signals are treated asynchronously in the WB stage

    - The rCAUSE register is asynchronous now

    - The wException signal is asyncronous instantanously

    - Add a repeat/continous treatement (not completed yet)



    - *** The "INT EXCEPTION NO STALL" work correctly




    Revision Changes Path
    1.5 r2000/r2000pl/rtl/verilog/r2000/define.h

    http://www.opencores.org/cvsweb.shtml/r2000/r2000pl/rtl/verilog/r2000/define.h.diff?r1=1.4&r2=1.5

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: define.h
    ===================================================================
    RCS file: /cvsroot/ameziti/r2000/r2000pl/rtl/verilog/r2000/define.h,v
    retrieving revision 1.4
    retrieving revision 1.5
    diff -u -b -r1.4 -r1.5
    --- define.h 11 Feb 2008 06:45:16 -0000 1.4
    +++ define.h 16 Mar 2008 23:05:33 -0000 1.5
    @@ -286,7 +286,7 @@
    `define RST_VECTOR `dw'hBFC0_0000

    `define INT_VECTOR_BEV `dw'hBFC0_0400
    - `define INT_VECTOR `dw'h0000_0ebc//`dw'h8000_0200
    + `define INT_VECTOR `dw'h0000_2000//`dw'h8000_0200

    `define GRL_VECTOR_BEV `dw'hBFC0_0380
    `define GRL_VECTOR `dw'h0000_0ec0//`dw'h8000_0180



    1.5 r2000/r2000pl/rtl/verilog/r2000/r2000_cp0.v

    http://www.opencores.org/cvsweb.shtml/r2000/r2000pl/rtl/verilog/r2000/r2000_cp0.v.diff?r1=1.4&r2=1.5

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: r2000_cp0.v
    ===================================================================
    RCS file: /cvsroot/ameziti/r2000/r2000pl/rtl/verilog/r2000/r2000_cp0.v,v
    retrieving revision 1.4
    retrieving revision 1.5
    diff -u -b -r1.4 -r1.5
    --- r2000_cp0.v 10 Feb 2008 23:15:26 -0000 1.4
    +++ r2000_cp0.v 16 Mar 2008 23:05:33 -0000 1.5
    @@ -82,7 +82,9 @@
    // Exception control signals
    Exception_o , // Exception occured

    - EPC_i , // PC to EPC
    + EPC_rpt_i , // PC to EPC repeat
    + EPC_ctn_i , // PC to EPC continue
    +
    PC_vec_o , // Exception Vector


    @@ -108,7 +110,8 @@
    input[1:0] SI_i ; //
    output Exception_o ;

    - input[`dw-1:0] EPC_i ;
    + input[`dw-1:0] EPC_rpt_i ;
    + input[`dw-1:0] EPC_ctn_i ;
    output[`dw-1:0] PC_vec_o ;

    input rfe_i ;
    @@ -144,13 +147,14 @@

    reg wStall ;

    - wire ExceptionP ; // Exception PreComputed
    - reg Exception ; // Exception occured signal
    + wire wExceptionDetect; // Exception Detection
    + reg rExceptionSave ; // Store the Exception signal while pipeline stall
    +
    + wire wException ; // Exception occured signal
    +
    + wire wRepeat ; // Repeat or continue type of exception

    - wire ptrSTATUS
    -// , ptr_CAUSE -// , ptr_EPC - ; + wire ptrSTATUS ; reg[`dw-1:0] rPC_vec = `ZERO; @@ -158,29 +162,32 @@ /* -------------------------------------------------------------- */ /* instances, statements */ /* --------------------- */ + + assign wRepeat = `LOW; + // Set "Exception sign" active until all Stalls are completed. - always@(rst_i, stall_i, Exception) - if ((rst_i) || (!stall_i)) - wStall = 0; - else if ((stall_i) && Exception ) - wStall = 1; + always@(rst_i, stall_i, wException) + if (rst_i || !stall_i) + wStall = `LOW; + else if (stall_i && wException ) + wStall = `HIGH; assign {KUo, IEo, KUp, IEp, KUc, IEc} = rSTATUS[5:0]; // Exception if Interrupt pending AND Not Masked AND Current Interrupt Enable -// assign Exception = ((IP & IM) || OVF_i || SYS_i || SI_i) && IEc; - assign ExceptionP = ((rCAUSE[`IP] & rSTATUS[`IM]) || OVF_i || SYS_i || SI_i) && IEc; + assign wExceptionDetect = ((rCAUSE[`IP] & rSTATUS[`IM]) || OVF_i || SYS_i || SI_i) && IEc; always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i) if (rst_i) - Exception = `CLEAR; + rExceptionSave = `CLEAR; else if (wStall) - Exception = Exception; + rExceptionSave = rExceptionSave; else - Exception = ExceptionP; + rExceptionSave = wExceptionDetect; + assign wException = wExceptionDetect; // Used for "Stall the pipeline" - assign Exception_o = Exception; + assign Exception_o = wException || rExceptionSave; /* ************************* */ /* STATUS Register statement */ @@ -197,7 +204,7 @@ rSTATUS = rSTATUS; else if (ptrSTATUS && rw_i) rSTATUS = data_i; - else if (Exception) + else if (wException) rSTATUS[5:0] = {rSTATUS[3:0],2'b0}; else if (rfe_i) rSTATUS[3:0] = rSTATUS[5:2]; @@ -206,18 +213,15 @@ /* ************************ */ /* CAUSE Register statement */ /* ************************ */ -// assign ptr_CAUSE = (addr_rw_i == `CAUSE_adr); - - always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i) +// always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i) + always@(rst_i, wStall, wException, INT_i, SI_i)// Asynchrone begin if (rst_i) begin rCAUSE = `ZERO; end else if (wStall) rCAUSE = rCAUSE; -// else if (ptr_CAUSE && rw_i) -// rCAUSE = data_i; - else if (Exception) + else if (wException) begin if (SYS_i) begin rCAUSE[`ExcCode] = `SYS_MNE; @@ -236,9 +240,9 @@ /* ************************ */ /* Vector statement: Gated */ /* ************************ */ - always@(Exception) + always@(wException) begin - if (Exception) begin + if (wException) begin if (SYS_i) begin if (BEV) rPC_vec = `GRL_VECTOR_BEV; @@ -260,16 +264,17 @@ /* ********************** */ /* EPC Register statement */ /* ********************** */ -// assign ptr_EPC = (addr_rw_i == `EPC_adr); - always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i) begin if (rst_i) rEPC = `ZERO; else if (wStall) rEPC = rEPC; - else if (Exception) - rEPC = EPC_i;// + 4; + else if (wException) + if (wRepeat) + rEPC = EPC_rpt_i; // Repeat + else + rEPC = EPC_ctn_i; // Continue end // Ouput 1.9 r2000/r2000pl/rtl/verilog/r2000/r2000_cpu_pipe.v http://www.opencores.org/cvsweb.shtml/r2000/r2000pl/rtl/verilog/r2000/r2000_cpu_pipe.v.diff?r1=1.8&r2=1.9 (In the diff below, changes in quantity of whitespace are not shown.) Index: r2000_cpu_pipe.v =================================================================== RCS file: /cvsroot/ameziti/r2000/r2000pl/rtl/verilog/r2000/r2000_cpu_pipe.v,v retrieving revision 1.8 retrieving revision 1.9 diff -u -b -r1.8 -r1.9 --- r2000_cpu_pipe.v 11 Feb 2008 06:44:23 -0000 1.8 +++ r2000_cpu_pipe.v 16 Mar 2008 23:05:33 -0000 1.9 @@ -160,8 +160,8 @@ wire [3:0] ID_cmp_status ; wire [`SELWIDTH-1:0]ID_mux_branch_sel `ifdef EXCEPTION - , EX_mux_branch_sel , MEM_mux_branch_sel ; - reg MEM_branch_Slot // Detect branch slot when exception + , EX_mux_branch_sel , MEM_mux_branch_sel , WB_mux_branch_sel; + reg WB_branch_Slot // Detect branch slot when exception `endif //EXCEPTION ; @@ -241,13 +241,13 @@ wire IFID_stall , IDEX_stall , EXMEM_stall , MEMWB_stall ; // co-processor 0 - wire ID_sig_clt_sys , EX_sig_clt_sys , MEM_sig_clt_sys ; - wire ID_sig_clt_brk , EX_sig_clt_brk , MEM_sig_clt_brk ; + wire ID_sig_clt_sys , EX_sig_clt_sys , MEM_sig_clt_sys , WB_sig_clt_sys; + wire ID_sig_clt_brk , EX_sig_clt_brk , MEM_sig_clt_brk , WB_sig_clt_brk; wire ID_clt_rfe , EX_clt_rfe , MEM_clt_rfe , WB_clt_rfe ; wire ID_clt_CoMf ; wire ID_clt_CoMt , EX_clt_CoMt , MEM_clt_CoMt , WB_clt_CoMt ; `ifdef EXCEPTION - wire [`dw-1:0] IF_EPC , ID_EPC , EX_EPC , MEM_EPC ; + wire [`dw-1:0] IF_EPC , ID_EPC , EX_EPC , MEM_EPC , WB_EPC ; reg [4:0] IF_EXC , ID_EXC , EX_EXC , MEM_EXC ; wire [`dw-1:0] wEPC_Vector ; @@ -255,9 +255,9 @@ EX_Carry , EX_Zero , EX_Neg ; - wire EX_sig_ovf , MEM_sig_ovf ; - wire [5:0] MEM_sig_int ; - wire [1:0] MEM_sig_si ; + wire EX_sig_ovf , MEM_sig_ovf , WB_sig_ovf; + wire [5:0] MEM_sig_int , WB_sig_int ; + wire [1:0] MEM_sig_si , WB_sig_si ; wire wException ; wire [`dw-1:0] WB_cp0_dout ; @@ -345,7 +345,7 @@ `ifdef EXCEPTION assign IF_EPC = wPC; - r2000_pipe #(`dw) IFID_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(IFID_flush) , .D_i(IF_EPC) , .Q_o(ID_EPC) ); + r2000_pipe #(`dw) IFID_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(`CLEAR) , .D_i(IF_EPC) , .Q_o(ID_EPC) ); `endif //EXCEPTION /*======================================================================================================================================================*/ @@ -576,25 +576,25 @@ r2000_pipe #( 1) IDEX_ctl_reg_src_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_clt_reg_src) , .Q_o(EX_clt_reg_src) ); /* DATAPATH */ - r2000_pipe #(`dw) IDEX_pc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_PCplus8) , .Q_o(EX_PCplus8) ); + r2000_pipe #(`dw) IDEX_pc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_PCplus8) , .Q_o(EX_PCplus8) ); r2000_pipe #(`dw) IDEX_inst_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_inst) , .Q_o(EX_inst) ); - r2000_pipe #(`dw) IDEX_rs_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_reg_rs_forward) , .Q_o(EX_reg_rs) ); - r2000_pipe #(`dw) IDEX_rt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_reg_rt_forward) , .Q_o(EX_reg_rt) ); + r2000_pipe #(`dw) IDEX_rs_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_reg_rs_forward) , .Q_o(EX_reg_rs) ); + r2000_pipe #(`dw) IDEX_rt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_reg_rt_forward) , .Q_o(EX_reg_rt) ); - r2000_pipe #(`dw) IDEX_se_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_signextend) , .Q_o(EX_signextend) ); - r2000_pipe #(`dw) IDEX_ze_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_zeroextend) , .Q_o(EX_zeroextend) ); - r2000_pipe #(`dw) IDEX_up_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_imup) , .Q_o(EX_imup) ); - r2000_pipe #(`iw) IDEX_rd_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_mux_rd_index_out) , .Q_o(EX_rd_index) ); + r2000_pipe #(`dw) IDEX_se_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_signextend) , .Q_o(EX_signextend) ); + r2000_pipe #(`dw) IDEX_ze_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_zeroextend) , .Q_o(EX_zeroextend) ); + r2000_pipe #(`dw) IDEX_up_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_imup) , .Q_o(EX_imup) ); + r2000_pipe #(`iw) IDEX_rd_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_mux_rd_index_out) , .Q_o(EX_rd_index) ); `ifdef EXCEPTION r2000_pipe #( 1) IDEX_sig_brk_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_sig_clt_brk) , .Q_o(EX_sig_clt_brk) ); r2000_pipe #( 1) IDEX_sig_sys_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_sig_clt_sys) , .Q_o(EX_sig_clt_sys) ); - r2000_pipe #( 1) IDEX_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_clt_rfe) , .Q_o(EX_clt_rfe) ); - r2000_pipe #( 1) IDEX_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_clt_CoMt) , .Q_o(EX_clt_CoMt) ); - r2000_pipe #(`dw) IDEX_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_EPC) , .Q_o(EX_EPC) ); - r2000_pipe #(`SELWIDTH) IDEX_brc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_mux_branch_sel) , .Q_o(EX_mux_branch_sel) ); + r2000_pipe #( 1) IDEX_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_clt_rfe) , .Q_o(EX_clt_rfe) ); + r2000_pipe #( 1) IDEX_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_clt_CoMt) , .Q_o(EX_clt_CoMt) ); + r2000_pipe #(`dw) IDEX_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_EPC) , .Q_o(EX_EPC) ); + r2000_pipe #(`SELWIDTH) IDEX_brc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_mux_branch_sel) , .Q_o(EX_mux_branch_sel) ); `endif //EXCEPTION /*======================================================================================================================================================*/ /* EX:Execution STAGE */ @@ -723,13 +723,13 @@ `ifdef EXCEPTION r2000_pipe #( 1) EXMEM_sig_brk_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_sig_clt_brk) , .Q_o(MEM_sig_clt_brk) ); r2000_pipe #( 1) EXMEM_sig_sys_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_sig_clt_sys) , .Q_o(MEM_sig_clt_sys) ); - r2000_pipe #( 6) EXMEM_sig_int_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(EXMEM_flush) , .D_i(sig_int_i) , .Q_o(MEM_sig_int) ); - r2000_pipe #( 2) EXMEM_sig_si_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(EXMEM_flush) , .D_i(sig_si_i) , .Q_o(MEM_sig_si) ); + r2000_pipe #( 6) EXMEM_sig_int_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(sig_int_i) , .Q_o(MEM_sig_int) ); + r2000_pipe #( 2) EXMEM_sig_si_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(sig_si_i) , .Q_o(MEM_sig_si) ); r2000_pipe #( 1) EXMEM_sig_ovf_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_sig_ovf) , .Q_o(MEM_sig_ovf) ); r2000_pipe #( 1) EXMEM_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_clt_CoMt) , .Q_o(MEM_clt_CoMt) ); r2000_pipe #( 1) EXMEM_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_clt_rfe) , .Q_o(MEM_clt_rfe) ); - r2000_pipe #(`dw) EXMEM_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_EPC) , .Q_o(MEM_EPC) ); + r2000_pipe #(`dw) EXMEM_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(`CLEAR) , .D_i(EX_EPC) , .Q_o(MEM_EPC) ); r2000_pipe #(`SELWIDTH) EXMEM_brc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_mux_branch_sel) , .Q_o(MEM_mux_branch_sel) ); `endif //EXCEPTION /*======================================================================================================================================================*/ @@ -777,9 +777,9 @@ // Enable assign mem_data_en_o = MEM_freeze; - // Read write - assign mem_data_wr_o = MEM_ctl_mem_write; - assign mem_data_rd_o = MEM_ctl_mem_read; + // Read write (when freeze or stall; don't let memory operations) + assign mem_data_wr_o = (MEM_freeze) ? MEM_ctl_mem_write : `LOW; + assign mem_data_rd_o = (MEM_freeze) ? MEM_ctl_mem_read : `LOW; // Adress assign MemDataAddrInt = MEM_alu_out; @@ -809,16 +809,46 @@ .out_o (MEM_RegDatain) // the result write back to the registerfile ); + /* *************** */ + /* MEM/WB PIPELINE */ + /* *************** */ + /* CONTROL */ + // WB + r2000_pipe #( 1) MEMWB_ctl_reg_write_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_ctl_reg_write) , .Q_o(WB_ctl_reg_write) ); + + /* DATAPATH */ +`ifdef DEBUG + r2000_pipe #(`dw) MEMWB_inst_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_inst) , .Q_o(WB_inst) ); +`endif//DEBUG + r2000_pipe #(`dw) MEMWB_regdatain_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_RegDatain) , .Q_o(WB_RegDatain) ); + r2000_pipe #(`iw) MEMWB_rd_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_rd_index) , .Q_o(WB_rd_index) ); + +`ifdef EXCEPTION + r2000_pipe #( 1) MEMWB_sig_brk_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_sig_clt_brk) , .Q_o(WB_sig_clt_brk) ); + r2000_pipe #( 1) MEMWB_sig_sys_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_sig_clt_sys) , .Q_o(WB_sig_clt_sys) ); + r2000_pipe #( 6) MEMWB_sig_int_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(MEM_sig_int) , .Q_o(WB_sig_int) ); + r2000_pipe #( 2) MEMWB_sig_si_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(MEM_sig_si) , .Q_o(WB_sig_si) ); + r2000_pipe #( 1) MEMWB_sig_ovf_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_sig_ovf) , .Q_o(WB_sig_ovf) ); + + r2000_pipe #( 1) MEMWB_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_clt_CoMt) , .Q_o(WB_clt_CoMt) ); + r2000_pipe #( 1) MEMWB_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_clt_rfe) , .Q_o(WB_clt_rfe) ); + r2000_pipe #(`dw) MEMWB_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(`CLEAR) , .D_i(MEM_EPC) , .Q_o(WB_EPC) ); + r2000_pipe #(`SELWIDTH) MEMWB_brc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_mux_branch_sel) , .Q_o(WB_mux_branch_sel) ); +`endif //EXCEPTION + /*======================================================================================================================================================*/ + /* WB:Write Back STAGE */ + /*======================================================================================================================================================*/ + `ifdef EXCEPTION always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i) begin if (rst_i == `RESET_ON) - MEM_branch_Slot = `CLEAR; + WB_branch_Slot = `CLEAR; else - // Branch Slot instruction in MEM stage (see mux_pc) - MEM_branch_Slot = ((MEM_mux_branch_sel == 1) || - (MEM_mux_branch_sel == 2) || - (MEM_mux_branch_sel == 3)); + // Branch Slot instruction in WB stage (see mux_pc) + WB_branch_Slot = ((WB_mux_branch_sel == 1) || + (WB_mux_branch_sel == 2) || + (WB_mux_branch_sel == 3)); end /*==================================================*/ @@ -837,17 +867,19 @@ .rfe_i (WB_clt_rfe) , // Signal of the rfe instruction // Exception events signals - .brch_i (MEM_branch_Slot) , // Detect exception in Branch Slot + .brch_i (WB_branch_Slot) , // Detect exception in Branch Slot - .OVF_i (MEM_sig_ovf) , // Overflow exception - .SYS_i (MEM_sig_clt_sys) , // System exception - .INT_i (MEM_sig_int) , // Interrupt interrupt - .SI_i (MEM_sig_si) , // + .OVF_i (WB_sig_ovf) , // Overflow exception + .SYS_i (WB_sig_clt_sys) , // System exception + .INT_i (WB_sig_int) , // Interrupt interrupt + .SI_i (WB_sig_si) , // // Exception control signals .Exception_o (wException) , // Exception occured - .EPC_i (MEM_EPC) , // PC to EPC + .EPC_ctn_i (MEM_EPC) , // PC to EPC continue + .EPC_rpt_i (WB_EPC) , // PC to EPC repeat + .PC_vec_o (wEPC_Vector) , // Exception Vector // System signals @@ -857,27 +889,6 @@ ); `endif //EXCEPTION - /* *************** */ - /* MEM/WB PIPELINE */ - /* *************** */ - /* CONTROL */ - // WB - r2000_pipe #( 1) MEMWB_ctl_reg_write_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_ctl_reg_write) , .Q_o(WB_ctl_reg_write) ); - - /* DATAPATH */ -`ifdef DEBUG - r2000_pipe #(`dw) MEMWB_inst_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_inst) , .Q_o(WB_inst) ); -`endif//DEBUG - r2000_pipe #(`dw) MEMWB_regdatain_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_RegDatain) , .Q_o(WB_RegDatain) ); - r2000_pipe #(`iw) MEMWB_rd_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_rd_index) , .Q_o(WB_rd_index) ); - -`ifdef EXCEPTION - r2000_pipe #( 1) MEMWB_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_clt_CoMt) , .Q_o(WB_clt_CoMt) ); - r2000_pipe #( 1) MEMWB_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_clt_rfe) , .Q_o(WB_clt_rfe) ); -`endif //EXCEPTION - /*======================================================================================================================================================*/ - /* WB:Write Back STAGE */ - /*======================================================================================================================================================*/ endmodule

     
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