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Message
From: cvs at opencores.org<cvs@o...>
Date: Sun Mar 16 10:27:43 CET 2008
Subject: [cvs-checkins] MODIFIED: mips789 ...
Date: 00/08/03 16:10:27 Modified: mips789/rtl/verilog ulit.v mips_core.v mips789_defs.v
mem_module.v forward.v EXEC_stage.v decode_pipe.v
Log:
no message
Revision Changes Path
1.11 mips789/rtl/verilog/ulit.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/ulit.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ulit.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/ulit.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- ulit.v 16 Mar 2008 05:31:18 -0000 1.10
+++ ulit.v 16 Mar 2008 09:27:42 -0000 1.11
@@ -27,7 +27,7 @@
always @(posedge clk )
if (~rst )ins_no=0;
- else if (0==is_nop)
+ else if (0 == is_nop)
ins_no = 1+ins_no;
endmodule
1.9 mips789/rtl/verilog/mips_core.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_core.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_core.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_core.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- mips_core.v 16 Mar 2008 05:31:18 -0000 1.8
+++ mips_core.v 16 Mar 2008 09:27:42 -0000 1.9
@@ -81,6 +81,7 @@
mem_module MEM_CTL
(
.pause(0),
+// .rt_i(BUS9884),
.Zz_addr(zz_addr_o),
.Zz_dout(zz_dout),
.Zz_wr_en(zz_wr_en_o),
@@ -240,6 +241,7 @@
forward iforward
(
+ .pause(0),
.alu_rs_fw(BUS1158),
.alu_rt_fw(BUS1196),
.alu_we(NET767),
1.7 mips789/rtl/verilog/mips789_defs.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips789_defs.v.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips789_defs.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips789_defs.v,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- mips789_defs.v 16 Mar 2008 05:31:18 -0000 1.6
+++ mips789_defs.v 16 Mar 2008 09:27:42 -0000 1.7
@@ -42,8 +42,15 @@
`define DMEM_LHS 8
`define DMEM_LH 9
`define DMEM_LHU 10
+
+ `define DMEM_LWL 11
+ `define DMEM_LWR 12
+ `define DMEM_SWL 13
+ `define DMEM_SWR 14
+
`define DMEM_NOP 0
+
`define ALU_SRL 1
`define ALU_SLL 2
`define ALU_SRA 4
@@ -182,7 +189,8 @@
-//`define ALTERA //this is DEBUG model ,
+`define ALTERA
+//this is DEBUG model ,
`else
1.10 mips789/rtl/verilog/mem_module.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mem_module.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mem_module.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mem_module.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- mem_module.v 16 Mar 2008 05:31:18 -0000 1.9
+++ mem_module.v 16 Mar 2008 09:27:42 -0000 1.10
@@ -15,6 +15,7 @@
module mem_module (
+ //input [31:0] rt_i,
input pause,
input clk,
input [31:0] din,
@@ -27,13 +28,29 @@
output [31:0] dout
) ;
+ /*module r32_reg_clr_cls(
+ input[`R32_LEN-1:0] r32_i,
+ output reg[`R32_LEN-1:0] r32_o,
+ input clk,input clr,input cls
+ );always@(posedge clk)if(clr) r32_o<=0;else if(cls)r32_o<=r32_o;else r32_o<=r32_i;endmodule
+ */
wire [3:0] BUS512;
wire [1:0] BUS629;
wire [31:0] BUS650;
+ wire [31:0]rt_r;
+
+ r32_reg_clr_cls rt_latch(
+ .r32_i(din),
+ .r32_o(rt_r),
+ .clk(clk),
+ .cls(pause),
+ .clr(0)
+ );
+
infile_dmem_ctl_reg dmem_ctl_post
( .pause(pause),
.byte_addr_o(BUS629),
@@ -64,7 +81,9 @@
mem_dout_ctl i_mem_dout_ctl
+
(
+ .rt_r(rt_r),
.byte_addr(BUS629),
.ctl(BUS512),
.din(zZ_din),
@@ -115,7 +134,6 @@
1:wr_en = 4'b0100;
2:wr_en = 4'b0010;
3:wr_en = 4'b0001;
- default :wr_en = 4'b000;
endcase
end
`DMEM_SH :
@@ -126,6 +144,26 @@
default :wr_en = 4'b0000;
endcase
end
+
+ `DMEM_SWL :
+ begin
+ case(addr_i[1:0])
+ 0:wr_en = 4'b0001;
+ 1:wr_en = 4'b0011;
+ 2:wr_en = 4'b0111;
+ 3:wr_en = 4'b1111;
+ endcase
+ end
+
+ `DMEM_SWR :
+ begin
+ case(addr_i[1:0])
+ 0:wr_en = 4'b1000;
+ 1:wr_en = 4'b1100;
+ 2:wr_en = 4'b1110;
+ 3:wr_en = 4'b1111;
+ endcase
+ end
`DMEM_SW :
begin
wr_en=4'b1111;
@@ -137,6 +175,7 @@
module mem_dout_ctl(
+ input [31:0] rt_r,
input [1:0]byte_addr,
input [3:0]ctl,
input [31:0] din,
@@ -153,8 +192,6 @@
'd1:dout={{24{din[23]}},din[23:16]};
'd2:dout={{24{din[15]}},din[15:8]};
'd3:dout={{24{din[7]}},din[7:0] };
- default :
- dout=32'bX;
endcase
`DMEM_LBU :
case (byte_addr)
@@ -162,8 +199,6 @@
'd2:dout={24'b0,din[15:8]};
'd1:dout={24'b0,din[23:16]};
'd0:dout={24'b0,din[31:24]};
- default :
- dout=32'bX;
endcase
`DMEM_LHU :
case (byte_addr)
@@ -177,11 +212,34 @@
'd2 :dout={{16{din[15]}},din[15:8],din[7 :0]};
default:dout=32'bX;
endcase
+
+ `DMEM_LWL :begin
+ case (byte_addr)
+
+ 'd0:dout={din[31:24],rt_r[23:0]};
+ 'd1:dout={din[31:16],rt_r[15:0]};
+ 'd2:dout={din[31:8],rt_r[7:0]};
+ default :
+ dout=din;
+ endcase
+ end
+ `DMEM_LWR : begin
+ case (byte_addr)
+ 'd1:dout={rt_r[31:24],din[23:0]};
+ 'd2:dout={rt_r[31:16],din[15:0]};
+ 'd3:dout={rt_r[31:8],din[7:0]};
+ default :
+ dout=din;
+ endcase
+ end
+
+
`DMEM_LW :
dout=din;
default :
- dout=0;
+ dout=32'b0;
endcase
+
endmodule
module mem_din_ctl(
@@ -197,6 +255,25 @@
dout={din[7:0],din[7:0],din[7:0],din[7:0]};
`DMEM_SH :
dout = {din[15:0],din[15:0]};
+ `DMEM_SWL ,/*:
+ begin
+ case(addr_i[1:0])
+ 0:dout = 4'b0001;
+ 1:dout = 4'b0011;
+ 2:dout = 4'b0111;
+ 3:dout = 4'b1111;
+ endcase
+ end
+ */
+ `DMEM_SWR ,/* :
+ begin
+ case(addr_i[1:0])
+ 0:dout = 4'b1000;
+ 1:dout = 4'b1100;
+ 2:dout = 4'b1110;
+ 3:dout = 4'b1111;
+ endcase
+ end */
`DMEM_SW :
dout =din;
default dout=32'bX;
1.10 mips789/rtl/verilog/forward.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/forward.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: forward.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/forward.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- forward.v 29 Nov 2007 03:50:36 -0000 1.9
+++ forward.v 16 Mar 2008 09:27:42 -0000 1.10
@@ -13,14 +13,15 @@
`include "mips789_defs.v"
-
-module fw_latch5(input clk,input[4:0]d,output reg [4:0]q);
- always @ (posedge clk) q<=d;
+/*
+module fw_latch5(input clk,input[4:0]d,output reg [4:0]q,input cls);
+ always @ (posedge clk)if (cls==0) q<=d;
endmodule
-module fw_latch1(input clk,input d,output reg q);
- always @ (posedge clk) q<=d;
+module fw_latch1(input clk,input d,output reg q,input cls);
+ always @ (posedge clk)if (cls==0) q<=d;
endmodule
+*/
module forward_node (
input [4:0]rn,
@@ -53,35 +54,22 @@
endmodule
module forward (
-alu_we,clk,mem_We,fw_alu_rn,
-fw_mem_rn,rns_i,rnt_i,alu_rs_fw,
-alu_rt_fw,cmp_rs_fw,cmp_rt_fw,dmem_fw
+input pause,
+ input alu_we,
+ input clk,
+ input mem_We,
+ input [4:0] fw_alu_rn,
+ input [4:0] fw_mem_rn,
+ input [4:0] rns_i,
+ input [4:0] rnt_i,
+ output [2:0] alu_rs_fw,
+ output [2:0] alu_rt_fw,
+ output [2:0] cmp_rs_fw,
+ output [2:0] cmp_rt_fw,
+ output [2:0] dmem_fw
) ;
- input alu_we;
- wire alu_we;
- input clk;
- wire clk;
- input mem_We;
- wire mem_We;
- input [4:0] fw_alu_rn;
- wire [4:0] fw_alu_rn;
- input [4:0] fw_mem_rn;
- wire [4:0] fw_mem_rn;
- input [4:0] rns_i;
- wire [4:0] rns_i;
- input [4:0] rnt_i;
- wire [4:0] rnt_i;
- output [2:0] alu_rs_fw;
- wire [2:0] alu_rs_fw;
- output [2:0] alu_rt_fw;
- wire [2:0] alu_rt_fw;
- output [2:0] cmp_rs_fw;
- wire [2:0] cmp_rs_fw;
- output [2:0] cmp_rt_fw;
- wire [2:0] cmp_rt_fw;
- output [2:0] dmem_fw;
- wire [2:0] dmem_fw;
+
wire [2:0] BUS1345;
wire [4:0] BUS82;
@@ -135,20 +123,21 @@
- fw_latch5 fw_reg_rns
+ r5_reg_clr_cls fw_reg_rns
(
- .clk(clk),
- .d(rns_i),
- .q(BUS82)
+ .clk(clk),.cls(pause),.clr(0),
+ .r5_i(rns_i),
+ .r5_o(BUS82)
);
- fw_latch5 fw_reg_rnt
+ r1_reg_clr_cls fw_reg_rnt
(
+.cls(pause),.clr(0),
.clk(clk),
- .d(rnt_i),
- .q(BUS937)
+ .r1_i(rnt_i),
+ .r1_o(BUS937)
);
1.12 mips789/rtl/verilog/EXEC_stage.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/EXEC_stage.v.diff?r1=1.11&r2=1.12
(In the diff below, changes in quantity of whitespace are not shown.)
Index: EXEC_stage.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/EXEC_stage.v,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -b -r1.11 -r1.12
--- EXEC_stage.v 16 Mar 2008 05:31:18 -0000 1.11
+++ EXEC_stage.v 16 Mar 2008 09:27:42 -0000 1.12
@@ -145,9 +145,9 @@
- r32_reg_cls spc
+ r32_reg_clr_cls spc
(
- .clk(clk),
+ .clk(clk),.clr(0),
.cls(spc_cls_i|pause),
.r32_i(pc_i),
.r32_o(zz_spc_o)
@@ -485,15 +485,16 @@
hi=0;
lo=0;
end
+
always @( posedge clk /*or negedge rst */)
if (~rst)
begin
mul_bit=0;
div_bit=0;
- /*
- hi=0;
- lo=0;
- */
+
+ hi=32'bx;
+ lo=32'bx;
+
negative_output = 0;
end
else
1.11 mips789/rtl/verilog/decode_pipe.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/decode_pipe.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: decode_pipe.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/decode_pipe.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- decode_pipe.v 16 Mar 2008 05:31:18 -0000 1.10
+++ decode_pipe.v 16 Mar 2008 09:27:42 -0000 1.11
@@ -966,18 +966,19 @@
'd34://LWL rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LWL ;
- ext_ctl = `IGN;
- rd_sel = `IGN;
- cmp_ctl = `IGN;
- pc_gen_ctl = `IGN;
- fsm_dly = `IGN;
- muxa_ctl = `IGN;
- muxb_ctl = `IGN;
- alu_func = `IGN;
- alu_we = `IGN;
- dmem_ctl = `IGN;
- wb_we = `IGN;
- wb_mux = `IGN;
+ //replaceID = `LW ;
+ ext_ctl = `EXT_SIGN;
+ rd_sel = `RD_RT;
+ cmp_ctl = `CMP_NOP;
+ pc_gen_ctl = `PC_NEXT;
+ fsm_dly = `FSM_NOP;
+ muxa_ctl = `MUXA_RS;
+ muxb_ctl = `MUXB_EXT;
+ alu_func = `ALU_ADD;
+ alu_we = `DIS;
+ dmem_ctl = `DMEM_LWL;
+ wb_we = `EN;
+ wb_mux = `WB_MEM;
//end of `LWL ;
end
'd35://LW rt,offset(base) (offset:signed;base:rs)
@@ -1034,18 +1035,18 @@
'd38://LWR rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LWR ;
- ext_ctl = `IGN;
- rd_sel = `IGN;
- cmp_ctl = `IGN;
- pc_gen_ctl = `IGN;
- fsm_dly = `IGN;
- muxa_ctl = `IGN;
- muxb_ctl = `IGN;
- alu_func = `IGN;
- alu_we = `IGN;
- dmem_ctl = `IGN;
- wb_we = `IGN;
- wb_mux = `IGN;
+ ext_ctl = `EXT_SIGN;
+ rd_sel = `RD_RT;
+ cmp_ctl = `CMP_NOP;
+ pc_gen_ctl = `PC_NEXT;
+ fsm_dly = `FSM_NOP;
+ muxa_ctl = `MUXA_RS;
+ muxb_ctl = `MUXB_EXT;
+ alu_func = `ALU_ADD;
+ alu_we = `DIS;
+ dmem_ctl = `DMEM_LWR;
+ wb_we = `EN;
+ wb_mux = `WB_MEM;
//end of `LWR ;
end
'd40://SB rt,offset(base) (offset:signed;base:rs)
@@ -1085,18 +1086,18 @@
'd42://SWL rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SWL ;
- ext_ctl = `IGN;
- rd_sel = `IGN;
- cmp_ctl = `IGN;
- pc_gen_ctl = `IGN;
- fsm_dly = `IGN;
- muxa_ctl = `IGN;
- muxb_ctl = `IGN;
- alu_func = `IGN;
- alu_we = `IGN;
- dmem_ctl = `IGN;
- wb_we = `IGN;
- wb_mux = `IGN;
+ ext_ctl = `EXT_SIGN;
+ rd_sel = `RD_NOP;
+ cmp_ctl = `CMP_NOP;
+ pc_gen_ctl = `PC_NEXT;
+ fsm_dly = `FSM_NOP;
+ muxa_ctl = `MUXA_RS;
+ muxb_ctl = `MUXB_EXT;
+ alu_func = `ALU_ADD;
+ alu_we = `DIS;
+ dmem_ctl = `DMEM_SWL;
+ wb_we = `DIS;
+ wb_mux = `WB_NOP;
//end of `SWL ;
end
'd43://SW rt,offset(base) (offset:signed;base:rs)
@@ -1119,18 +1120,18 @@
'd46://SWR rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SWR ;
- ext_ctl = `IGN;
- rd_sel = `IGN;
- cmp_ctl = `IGN;
- pc_gen_ctl = `IGN;
- fsm_dly = `IGN;
- muxa_ctl = `IGN;
- muxb_ctl = `IGN;
- alu_func = `IGN;
- alu_we = `IGN;
- dmem_ctl = `IGN;
- wb_we = `IGN;
- wb_mux = `IGN;
+ ext_ctl = `EXT_SIGN;
+ rd_sel = `RD_NOP;
+ cmp_ctl = `CMP_NOP;
+ pc_gen_ctl = `PC_NEXT;
+ fsm_dly = `FSM_NOP;
+ muxa_ctl = `MUXA_RS;
+ muxb_ctl = `MUXB_EXT;
+ alu_func = `ALU_ADD;
+ alu_we = `DIS;
+ dmem_ctl = `DMEM_SWR;
+ wb_we = `DIS;
+ wb_mux = `WB_NOP;
//end of `SWR ;
end
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