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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Jan 28 01:28:16 CET 2008
Subject: [cvs-checkins] MODIFIED: mlite ...
Date: 00/08/01 28:01:28 Modified: mlite/vhdl mlite_pack.vhd
Log:
Added eth_dma
Revision Changes Path
1.18 mlite/vhdl/mlite_pack.vhd
http://www.opencores.org/cvsweb.shtml/mlite/vhdl/mlite_pack.vhd.diff?r1=1.17&r2=1.18
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mlite_pack.vhd
===================================================================
RCS file: /cvsroot/rhoads/mlite/vhdl/mlite_pack.vhd,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -b -r1.17 -r1.18
--- mlite_pack.vhd 15 Dec 2007 16:14:39 -0000 1.17
+++ mlite_pack.vhd 28 Jan 2008 00:28:15 -0000 1.18
@@ -349,36 +349,6 @@
data_read : out std_logic_vector(31 downto 0));
end component; --ram
- component ddr_ctrl
- port(clk : in std_logic;
- clk_2x : in std_logic;
- reset_in : in std_logic;
-
- address : in std_logic_vector(25 downto 2);
- byte_we : in std_logic_vector(3 downto 0);
- data_w : in std_logic_vector(31 downto 0);
- data_r : out std_logic_vector(31 downto 0);
- active : in std_logic;
- pause : out std_logic;
-
- SD_CK_P : out std_logic; --clock_positive
- SD_CK_N : out std_logic; --clock_negative
- SD_CKE : out std_logic; --clock_enable
-
- SD_BA : out std_logic_vector(1 downto 0); --bank_address
- SD_A : out std_logic_vector(12 downto 0); --address(row or col)
- SD_CS : out std_logic; --chip_select
- SD_RAS : out std_logic; --row_address_strobe
- SD_CAS : out std_logic; --column_address_strobe
- SD_WE : out std_logic; --write_enable
-
- SD_DQ : inout std_logic_vector(15 downto 0); --data
- SD_UDM : out std_logic; --upper_byte_enable
- SD_UDQS : inout std_logic; --upper_data_strobe
- SD_LDM : out std_logic; --low_byte_enable
- SD_LDQS : inout std_logic); --low_data_strobe
- end component; --ddr
-
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
@@ -393,9 +363,37 @@
data_avail : out std_logic);
end component; --uart
+ component eth_dma
+ port(clk : in std_logic; --25 MHz
+ reset : in std_logic;
+ enable_eth : in std_logic;
+ select_eth : in std_logic;
+ rec_isr : out std_logic;
+ send_isr : out std_logic;
+
+ address : out std_logic_vector(31 downto 2); --to DDR
+ byte_we : out std_logic_vector(3 downto 0);
+ data_write : out std_logic_vector(31 downto 0);
+ data_read : in std_logic_vector(31 downto 0);
+ pause_in : in std_logic;
+
+ mem_address : in std_logic_vector(31 downto 2); --from CPU
+ mem_byte_we : in std_logic_vector(3 downto 0);
+ data_w : in std_logic_vector(31 downto 0);
+ pause_out : out std_logic;
+
+ E_RX_CLK : in std_logic; --2.5 MHz receive
+ E_RX_DV : in std_logic; --data valid
+ E_RXD : in std_logic_vector(3 downto 0); --receive nibble
+ E_TX_CLK : in std_logic; --2.5 MHz transmit
+ E_TX_EN : out std_logic; --transmit enable
+ E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
+ end component; --eth_dma
+
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
- log_file : string := "UNUSED");
+ log_file : string := "UNUSED";
+ ethernet : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
@@ -411,6 +409,36 @@
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
+ component ddr_ctrl
+ port(clk : in std_logic;
+ clk_2x : in std_logic;
+ reset_in : in std_logic;
+
+ address : in std_logic_vector(25 downto 2);
+ byte_we : in std_logic_vector(3 downto 0);
+ data_w : in std_logic_vector(31 downto 0);
+ data_r : out std_logic_vector(31 downto 0);
+ active : in std_logic;
+ pause : out std_logic;
+
+ SD_CK_P : out std_logic; --clock_positive
+ SD_CK_N : out std_logic; --clock_negative
+ SD_CKE : out std_logic; --clock_enable
+
+ SD_BA : out std_logic_vector(1 downto 0); --bank_address
+ SD_A : out std_logic_vector(12 downto 0); --address(row or col)
+ SD_CS : out std_logic; --chip_select
+ SD_RAS : out std_logic; --row_address_strobe
+ SD_CAS : out std_logic; --column_address_strobe
+ SD_WE : out std_logic; --write_enable
+
+ SD_DQ : inout std_logic_vector(15 downto 0); --data
+ SD_UDM : out std_logic; --upper_byte_enable
+ SD_UDQS : inout std_logic; --upper_data_strobe
+ SD_LDM : out std_logic; --low_byte_enable
+ SD_LDQS : inout std_logic); --low_data_strobe
+ end component; --ddr
+
end; --package mlite_pack
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