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From: cvs at opencores.org<cvs@o...>
Date: Wed Jan 23 10:09:47 CET 2008
Subject: [cvs-checkins] MODIFIED: tg68 ...
Date: 00/08/01 23:10:09

Modified: tg68/VHDL TG68.vhd
Log:
bugfix Timing


Revision Changes Path
1.3 tg68/VHDL/TG68.vhd

http://www.opencores.org/cvsweb.shtml/tg68/VHDL/TG68.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: TG68.vhd
===================================================================
RCS file: /cvsroot/tobiflex/tg68/VHDL/TG68.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- TG68.vhd 28 Nov 2007 13:44:57 -0000 1.2
+++ TG68.vhd 23 Jan 2008 09:09:46 -0000 1.3
@@ -3,7 +3,7 @@
-- --
-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --
-- --
--- Copyright (c) 2007 Tobias Gubener <tobiflex@o...> --
+-- Copyright (c) 2007-2008 Tobias Gubener <tobiflex@o...> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
@@ -21,6 +21,9 @@
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
+-- Revision 1.02 2008/01/23
+-- bugfix Timing
+--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
@@ -55,7 +58,8 @@
as : out std_logic;
uds : out std_logic;
lds : out std_logic;
- rw : out std_logic
+ rw : out std_logic;
+ drive_data : out std_logic --enable for data_out driver
);
end TG68;

@@ -96,17 +100,21 @@
SIGNAL lds_in : std_logic;
SIGNAL state : std_logic_vector(1 downto 0);
SIGNAL clkena : std_logic;
+ SIGNAL n_clk : std_logic;
+ SIGNAL cpuIPL : std_logic_vector(2 downto 0);


BEGIN

+ n_clk <= NOT clk;
+
TG68_fast_inst: TG68_fast
PORT MAP (
- clk => not clk, -- : in std_logic;
+ clk => n_clk, -- : in std_logic;
reset => reset, -- : in std_logic;
clkena_in => clkena, -- : in std_logic;
data_in => data_in, -- : in std_logic_vector(15 downto 0);
- IPL => IPL, -- : in std_logic_vector(2 downto 0);
+ IPL => cpuIPL, -- : in std_logic_vector(2 downto 0);
test_IPL => '0', -- : in std_logic;
address => addr, -- : out std_logic_vector(31 downto 0);
data_write => data_out, -- : out std_logic_vector(15 downto 0);
@@ -117,20 +125,13 @@
LDS => lds_in -- : out std_logic;
);

--- clkena <= '1' WHEN clkena_in='1' AND ((clkena_e OR decode)='1')
--- ELSE '0';
-
-
PROCESS (clk)
BEGIN
- IF rising_edge(clk) THEN
--- IF clkena_in='1' AND ((clkena_e OR decode)='1') THEN
IF clkena_in='1' AND (clkena_e='1' OR state="01") THEN
clkena <= '1';
ELSE
clkena <= '0';
END IF;
- END IF;
END PROCESS;

PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
@@ -179,6 +180,7 @@
END IF;
WHEN "11" =>
S_state <= "00";
+ WHEN OTHERS => null;
END CASE;
END IF; END IF; @@ -189,6 +191,8 @@ uds_e <= '1'; lds_e <= '1'; clkena_e <= '0'; + cpuIPL <= "111"; + drive_data <= '0'; ELSIF falling_edge(clk) THEN IF clkena_in='1' THEN as_e <= '1'; @@ -196,12 +200,15 @@ uds_e <= '1'; lds_e <= '1'; clkena_e <= '0'; + drive_data <= '0'; CASE S_state IS - WHEN "00" => - WHEN "01" => + WHEN "00" => null; + WHEN "01" => drive_data <= NOT wr; WHEN "10" => as_e <= '0'; uds_e <= uds_in; lds_e <= lds_in; + cpuIPL <= IPL; + drive_data <= NOT wr; IF state="01" THEN clkena_e <= '1'; waitm <= '0'; @@ -209,7 +216,7 @@ clkena_e <= NOT dtack; waitm <= dtack; END IF; - WHEN "11" => + WHEN OTHERS => null; END CASE; END IF; END IF;