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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Jan 19 16:57:36 CET 2008
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/08/01 19:16:57 Modified: aemb/rtl/verilog aeMB_xecu.v
Log:
Fix MTS during interrupt vectoring bug (reported by M. Ettus).
Revision Changes Path
1.11 aemb/rtl/verilog/aeMB_xecu.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_xecu.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB_xecu.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_xecu.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- aeMB_xecu.v 25 Dec 2007 22:15:09 -0000 1.10
+++ aeMB_xecu.v 19 Jan 2008 15:57:36 -0000 1.11
@@ -1,4 +1,4 @@
-/* $Id: aeMB_xecu.v,v 1.10 2007/12/25 22:15:09 sybreon Exp $
+/* $Id: aeMB_xecu.v,v 1.11 2008/01/19 15:57:36 sybreon Exp $
**
** AEMB MAIN EXECUTION ALU
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -255,7 +255,7 @@
// --- MSR REGISTER -----------------
// C
- wire fMTS = (rOPC == 6'o45) & rIMM[14];
+ wire fMTS = (rOPC == 6'o45) & rIMM[14] & !fSKIP;
wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
@@ -272,11 +272,11 @@
3'o4: xMSR_C <= rMSR_C;
3'o5: xMSR_C <= rMSR_C;
default: xMSR_C <= 1'hX;
- endcase
+ endcase // case (rMXALU)
// IE/BIP/BE
- wire fRTID = (rOPC == 6'o55) & rRD[0];
- wire fRTBD = (rOPC == 6'o55) & rRD[1];
+ wire fRTID = (rOPC == 6'o55) & rRD[0] & !fSKIP;
+ wire fRTBD = (rOPC == 6'o55) & rRD[1] & !fSKIP;
wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
@@ -361,7 +361,7 @@
rMSR_IE <= 1'h0;
rRESULT <= 32'h0;
// End of automatics
- end else if (gena) begin
+ end else if (gena) begin // if (grst)
rRESULT <= #1 xRESULT;
rDWBSEL <= #1 xDWBSEL;
rMSR_C <= #1 xMSR_C;
@@ -375,6 +375,9 @@
/*
$Log: aeMB_xecu.v,v $
+ Revision 1.11 2008/01/19 15:57:36 sybreon
+ Fix MTS during interrupt vectoring bug (reported by M. Ettus).
+
Revision 1.10 2007/12/25 22:15:09 sybreon
Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
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