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Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Dec 28 22:44:50 CET 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/12 28:22:44 Modified: aemb/sim/verilog aemb2.v
Log:
Minor typo
Revision Changes Path
1.3 aemb/sim/verilog/aemb2.v
http://www.opencores.org/cvsweb.shtml/aemb/sim/verilog/aemb2.v.diff?r1=1.2&r2=1.3
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aemb2.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/sim/verilog/aemb2.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- aemb2.v 18 Dec 2007 18:54:37 -0000 1.2
+++ aemb2.v 28 Dec 2007 21:44:50 -0000 1.3
@@ -1,7 +1,6 @@
-/* $Id: aemb2.v,v 1.2 2007/12/18 18:54:37 sybreon Exp $
+/* $Id: aemb2.v,v 1.3 2007/12/28 21:44:50 sybreon Exp $
**
** AEMB2 TEST BENCH
-**
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
**
** This file is part of AEMB.
@@ -24,7 +23,7 @@
parameter IWB=16;
parameter DWB=16;
- parameter TXE = 1; ///< thread execution enable
+ parameter TXE = 0; ///< thread execution enable
parameter MUL = 1; ///< enable hardware multiplier
parameter BSF = 1; ///< enable barrel shifter
@@ -97,7 +96,7 @@
reg [15:2] dadr, iadr;
wire [31:0] dwb_dat_t = ram[dwb_adr_o];
- wire [31:0] iwb_dat_i = ram[iadr];
+ wire [31:0] iwb_dat_i = rom[iadr];
wire [31:0] dwb_dat_i = ram[dadr];
wire [31:0] cwb_dat_i = cwb_adr_o;
@@ -143,6 +142,7 @@
for (i=0;i<65535;i=i+1) begin
ram[i] <= $random;
end
+ #1 $readmemh("dump.vmem",rom);
#1 $readmemh("dump.vmem",ram);
end
@@ -193,7 +193,15 @@
// INTERNAL WIRING ////////////////////////////////////////////////////
aeMB2_sim
- #(/*AUTOINSTPARAM*/)
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .IWB (IWB),
+ .DWB (DWB),
+ .TXE (TXE),
+ .MUL (MUL),
+ .BSF (BSF),
+ .FSL (FSL),
+ .DIV (DIV))
dut (/*AUTOINST*/
// Outputs
.cwb_adr_o (cwb_adr_o[6:2]),
@@ -226,7 +234,6 @@
endmodule // edk32
-
/* $Log $ */
// Local Variables:
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