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From: cvs at opencores.org<cvs@o...>
Date: Fri Dec 21 23:39:39 CET 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/12 21:23:39

Modified: aemb/rtl/verilog aeMB2_bpcu.v
Log:
Prevent fHZD & rBRA[1]




Revision Changes Path
1.5 aemb/rtl/verilog/aeMB2_bpcu.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_bpcu.v.diff?r1=1.4&r2=1.5

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB2_bpcu.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_bpcu.v,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- aeMB2_bpcu.v 17 Dec 2007 12:53:43 -0000 1.4
+++ aeMB2_bpcu.v 21 Dec 2007 22:39:38 -0000 1.5
@@ -1,4 +1,4 @@
-/* $Id: aeMB2_bpcu.v,v 1.4 2007/12/17 12:53:43 sybreon Exp $
+/* $Id: aeMB2_bpcu.v,v 1.5 2007/12/21 22:39:38 sybreon Exp $
**
** AEMB2 BRANCH/PROGRAMME COUNTER
**
@@ -115,7 +115,7 @@
wire fOPBHZD = (rRB_IF == rRD_EX) & (fLOAD | fMULT) & !fMOV & !rOPC_IF[3] & fWRE;
wire fOPAHZD = (rRA_IF == rRD_EX) & (fLOAD | fMULT) & !fBRU & fWRE;
wire fOPDHZD = (rRD_IF == rRD_EX) & (fLOAD | fMULT) & fSTR & fWRE;
- wire fHZD = fOPBHZD | fOPAHZD | fOPDHZD;
+ wire fHZD = (fOPBHZD | fOPAHZD | fOPDHZD) & !rBRA[1];

/*
IWB PC OUTPUT
@@ -243,6 +243,9 @@
endmodule // aeMB2_bpcu

/* $Log: aeMB2_bpcu.v,v $
+/* Revision 1.5 2007/12/21 22:39:38 sybreon
+/* Prevent fHZD & rBRA[1]
+/*
/* Revision 1.4 2007/12/17 12:53:43 sybreon
/* Made idle thread PC track main PC.
/*