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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Dec 17 13:53:13 CET 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/12 17:13:53 Modified: aemb/rtl/verilog aeMB2_edk32.v
Log:
Changed simulation kernel.
Revision Changes Path
1.7 aemb/rtl/verilog/aeMB2_edk32.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_edk32.v.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB2_edk32.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_edk32.v,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- aeMB2_edk32.v 16 Dec 2007 03:25:22 -0000 1.6
+++ aeMB2_edk32.v 17 Dec 2007 12:53:13 -0000 1.7
@@ -1,4 +1,4 @@
-/* $Id: aeMB2_edk32.v,v 1.6 2007/12/16 03:25:22 sybreon Exp $
+/* $Id: aeMB2_edk32.v,v 1.7 2007/12/17 12:53:13 sybreon Exp $
**
** AEMB2 HI-PERFORMANCE CPU
**
@@ -466,15 +466,10 @@
$writeh(" MSR=", wMSR," ");
case (rALU_OF)
- 3'o0: if (dwb_stb_o)
- $write(" RAM");
- else
- $write(" ADD");
- 3'o1: $write(" LOG");
- 3'o2: $write(" SFT");
+ 3'o0: $write(" ADD");
+ 3'o1: $write(" BSF");
+ 3'o2: $write(" SLM");
3'o3: $write(" MOV");
- 3'o4: $write(" MUL");
- 3'o5: $write(" BSF");
default: $write(" XXX");
endcase // case (rALU_OF)
@@ -526,6 +521,9 @@
endmodule // aeMB2_edk32
/* $Log: aeMB2_edk32.v,v $
+/* Revision 1.7 2007/12/17 12:53:13 sybreon
+/* Changed simulation kernel.
+/*
/* Revision 1.6 2007/12/16 03:25:22 sybreon
/* Replaced OF/ID blocks with combined block.
/*
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