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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Fri Nov 30 21:21:20 CET 2007
    Subject: [cvs-checkins] MODIFIED: spi_slave ...
    Top
    Date: 00/07/11 30:21:21

    Added: spi_slave/sim/rtl_sim/modelsim_sim/run/opb_spi_slave
    opb_spi_slave_tb_c.do opb_spi_slave_tb_s.do
    opb_spi_slave_tb_w.do
    Log:
    Initial Release


    Revision Changes Path
    1.1 spi_slave/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_c.do

    http://www.opencores.org/cvsweb.shtml/spi_slave/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_c.do?rev=1.1&content-type=text/x-cvsweb-markup

    Index: opb_spi_slave_tb_c.do
    ===================================================================
    vlib work
    # packages
    vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd

    # DUT
    vcom -93 ../../../../../rtl/vhdl/bin2gray.vhd
    vcom -93 ../../../../../rtl/vhdl/gray2bin.vhd
    vcom -93 ../../../../../rtl/vhdl/gray_adder.vhd
    vcom -93 ../../../../../rtl/vhdl/fifo_prog_flags.vhd
    vcom -93 ../../../../../rtl/vhdl/ram.vhd
    vcom -93 ../../../../../rtl/vhdl/fifo.vhd
    vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd
    vcom -93 ../../../../../rtl/vhdl/opb_if.vhd
    vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd
    vcom -93 ../../../../../rtl/vhdl/shift_register.vhd
    vcom -93 ../../../../../rtl/vhdl/irq_ctl.vhd
    vcom -93 ../../../../../rtl/vhdl/opb_spi_slave.vhd
    # Testbench
    vcom -93 ../../../../../bench/vhdl/opb_spi_slave_tb.vhd


    1.1 spi_slave/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_s.do

    http://www.opencores.org/cvsweb.shtml/spi_slave/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_s.do?rev=1.1&content-type=text/x-cvsweb-markup

    Index: opb_spi_slave_tb_s.do
    ===================================================================
    vsim -t ps opb_spi_slave_tb
    view wave
    do opb_spi_slave_tb_w.do
    run -all


    1.1 spi_slave/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_w.do

    http://www.opencores.org/cvsweb.shtml/spi_slave/sim/rtl_sim/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_w.do?rev=1.1&content-type=text/x-cvsweb-markup

    Index: opb_spi_slave_tb_w.do
    ===================================================================
    onerror {resume}
    quietly WaveActivateNextPane {} 0
    add wave -noupdate -divider OPB-Bus
    add wave -noupdate -format Logic /opb_spi_slave_tb/opb_rst
    add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/opb_abus
    add wave -noupdate -format Literal /opb_spi_slave_tb/opb_be
    add wave -noupdate -format Logic /opb_spi_slave_tb/opb_clk
    add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/opb_dbus
    add wave -noupdate -format Logic /opb_spi_slave_tb/opb_rnw
    add wave -noupdate -format Logic /opb_spi_slave_tb/opb_select
    add wave -noupdate -format Logic /opb_spi_slave_tb/opb_seqaddr
    add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/sln_dbus
    add wave -noupdate -format Logic /opb_spi_slave_tb/sln_xferack
    add wave -noupdate -divider SPI
    add wave -noupdate -format Logic /opb_spi_slave_tb/sclk
    add wave -noupdate -format Logic /opb_spi_slave_tb/ss_n
    add wave -noupdate -format Logic /opb_spi_slave_tb/mosi
    add wave -noupdate -format Logic /opb_spi_slave_tb/miso
    add wave -noupdate -divider Internal
    add wave -noupdate -format Literal /opb_spi_slave_tb/opb_read_data
    add wave -noupdate -format Literal /opb_spi_slave_tb/dut/rx_fifo_1/dout
    add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/tx_thresh
    add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/rx_thresh
    add wave -noupdate -format Literal /opb_spi_slave_tb/spi_value_in
    add wave -noupdate -divider TX_FIFO
    add wave -noupdate -format Literal /opb_spi_slave_tb/dut/tx_fifo_1/prog_full_thresh
    add wave -noupdate -format Literal /opb_spi_slave_tb/dut/tx_fifo_1/prog_empty_thresh
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/wr_clk
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/wr_en
    add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/tx_fifo_1/din
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/prog_empty
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/empty
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/underflow
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/prog_full
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/full
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/overflow
    add wave -noupdate -divider RX_FIFO
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/wr_clk
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/wr_en
    add wave -noupdate -format Literal /opb_spi_slave_tb/dut/rx_fifo_1/din
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/empty
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/prog_empty
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/underflow
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/prog_full
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/full
    add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/overflow
    TreeUpdate [SetDefaultTree]
    WaveRestoreCursors {{Cursor 1} {7450000 ps} 0} configure wave -namecolwidth 302 configure wave -valuecolwidth 53 configure wave -justifyvalue left configure wave -signalnamewidth 0 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update WaveRestoreZoom {2506325 ps} {13562825 ps}

     
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