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From: cvs at opencores.org<cvs@o...>
Date: Fri Nov 30 18:08:29 CET 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/11 30:18:08

Modified: aemb/rtl/verilog aeMB_edk32.v
Log:
Moved simulation kernel into code.


Revision Changes Path
1.11 aemb/rtl/verilog/aeMB_edk32.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_edk32.v.diff?r1=1.10&r2=1.11

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_edk32.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_edk32.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- aeMB_edk32.v 16 Nov 2007 21:52:03 -0000 1.10
+++ aeMB_edk32.v 30 Nov 2007 17:08:29 -0000 1.11
@@ -1,4 +1,4 @@
-// $Id: aeMB_edk32.v,v 1.10 2007/11/16 21:52:03 sybreon Exp $
+// $Id: aeMB_edk32.v,v 1.11 2007/11/30 17:08:29 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core
//
@@ -20,6 +20,9 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_edk32.v,v $
+// Revision 1.11 2007/11/30 17:08:29 sybreon
+// Moved simulation kernel into code.
+//
// Revision 1.10 2007/11/16 21:52:03 sybreon
// Added fsl_tag_o to FSL bus (tag either address or data).
//
@@ -132,6 +135,8 @@
wire gclk = sys_clk_i;
wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);

+ // --- INSTANTIATIONS -------------------------------------
+
aeMB_ibuf
ibuf (/*AUTOINST*/
// Outputs
@@ -266,4 +271,203 @@
.gena (gena));


+ // --- SIMULATION KERNEL ----------------------------------
+ // synopsys translate_off
+
+`ifdef AEMB_SIMULATION_KERNEL
+
+ wire [IW-1:0] iwb_adr = {iwb_adr_o, 2'd0};
+ wire [DW-1:0] dwb_adr = {dwb_adr_o,2'd0};
+ wire [1:0] wBRA = {rBRA, rDLY};
+ wire [3:0] wMSR = {xecu.rMSR_BIP, xecu.rMSR_C, xecu.rMSR_IE, xecu.rMSR_BE};
+
+ always @(posedge gclk) if (gena) begin
+
+ $write ("\n", ($stime/10));
+ $writeh (" PC=", iwb_adr );
+ $writeh ("\t");
+
+ case (wBRA)
+ 2'b00: $write(" ");
+ 2'b01: $write(".");
+ 2'b10: $write("-");
+ 2'b11: $write("+");
+ endcase // case (wBRA)
+
+ case (rOPC)
+ 6'o00: if (rRD == 0) $write(" "); else $write("ADD");
+ 6'o01: $write("RSUB");
+ 6'o02: $write("ADDC");
+ 6'o03: $write("RSUBC");
+ 6'o04: $write("ADDK");
+ 6'o05: case (rIMM[1:0])
+ 2'o0: $write("RSUBK");
+ 2'o1: $write("CMP");
+ 2'o3: $write("CMPU");
+ default: $write("XXX");
+ endcase // case (rIMM[1:0])
+ 6'o06: $write("ADDKC");
+ 6'o07: $write("RSUBKC");
+
+ 6'o10: $write("ADDI");
+ 6'o11: $write("RSUBI");
+ 6'o12: $write("ADDIC");
+ 6'o13: $write("RSUBIC");
+ 6'o14: $write("ADDIK");
+ 6'o15: $write("RSUBIK");
+ 6'o16: $write("ADDIKC");
+ 6'o17: $write("RSUBIKC");
+
+ 6'o20: $write("MUL");
+ 6'o21: case (rALT[10:9])
+ 2'o0: $write("BSRL");
+ 2'o1: $write("BSRA");
+ 2'o2: $write("BSLL"); + default: $write("XXX"); + endcase // case (rALT[10:9]) + 6'o22: $write("IDIV"); + + 6'o30: $write("MULI"); + 6'o31: case (rALT[10:9]) + 2'o0: $write("BSRLI"); + 2'o1: $write("BSRAI"); + 2'o2: $write("BSLLI"); + default: $write("XXX"); + endcase // case (rALT[10:9]) + 6'o33: case (rRB[4:2]) + 3'o0: $write("GET"); + 3'o4: $write("PUT"); + 3'o2: $write("NGET"); + 3'o6: $write("NPUT"); + 3'o1: $write("CGET"); + 3'o5: $write("CPUT"); + 3'o3: $write("NCGET"); + 3'o7: $write("NCPUT"); + endcase // case (rRB[4:2]) + + 6'o40: $write("OR"); + 6'o41: $write("AND"); + 6'o42: if (rRD == 0) $write(" "); else $write("XOR"); + 6'o43: $write("ANDN"); + 6'o44: case (rIMM[6:5]) + 2'o0: $write("SRA"); + 2'o1: $write("SRC"); + 2'o2: $write("SRL"); + 2'o3: if (rIMM[0]) $write("SEXT16"); else $write("SEXT8"); + endcase // case (rIMM[6:5]) + + 6'o45: $write("MOV"); + 6'o46: case (rRA[3:2]) + 3'o0: $write("BR"); + 3'o1: $write("BRL"); + 3'o2: $write("BRA"); + 3'o3: $write("BRAL"); + endcase // case (rRA[3:2]) + + 6'o47: case (rRD[2:0]) + 3'o0: $write("BEQ"); + 3'o1: $write("BNE"); + 3'o2: $write("BLT"); + 3'o3: $write("BLE"); + 3'o4: $write("BGT"); + 3'o5: $write("BGE"); + default: $write("XXX"); + endcase // case (rRD[2:0]) + + 6'o50: $write("ORI"); + 6'o51: $write("ANDI"); + 6'o52: $write("XORI"); + 6'o53: $write("ANDNI"); + 6'o54: $write("IMMI"); + 6'o55: case (rRD[1:0]) + 2'o0: $write("RTSD"); + 2'o1: $write("RTID"); + 2'o2: $write("RTBD"); + default: $write("XXX"); + endcase // case (rRD[1:0]) + 6'o56: case (rRA[3:2]) + 3'o0: $write("BRI"); + 3'o1: $write("BRLI"); + 3'o2: $write("BRAI"); + 3'o3: $write("BRALI"); + endcase // case (rRA[3:2]) + 6'o57: case (rRD[2:0]) + 3'o0: $write("BEQI"); + 3'o1: $write("BNEI"); + 3'o2: $write("BLTI"); + 3'o3: $write("BLEI"); + 3'o4: $write("BGTI"); + 3'o5: $write("BGEI"); + default: $write("XXX"); + endcase // case (rRD[2:0]) + + 6'o60: $write("LBU"); + 6'o61: $write("LHU"); + 6'o62: $write("LW"); + 6'o64: $write("SB"); + 6'o65: $write("SH"); + 6'o66: $write("SW"); + + 6'o70: $write("LBUI"); + 6'o71: $write("LHUI"); + 6'o72: $write("LWI"); + 6'o74: $write("SBI"); + 6'o75: $write("SHI"); + 6'o76: $write("SWI"); + + default: $write("XXX"); + endcase // case (rOPC) + + case (rOPC[3]) + 1'b1: $writeh("\tr",rRD,", r",rRA,", h",rIMM); + 1'b0: $writeh("\tr",rRD,", r",rRA,", r",rRB," "); + endcase // case (rOPC[3]) + + + // ALU + $write("\t"); + $writeh(" A=",xecu.rOPA); + $writeh(" B=",xecu.rOPB); + + case (rMXALU) + 3'o0: $write(" ADD"); + 3'o1: $write(" LOG"); + 3'o2: $write(" SFT"); + 3'o3: $write(" MOV"); + 3'o4: $write(" MUL"); + 3'o5: $write(" BSF"); + default: $write(" XXX"); + endcase // case (rMXALU) + $writeh("=h",xecu.xRESULT); + + // WRITEBACK + $writeh("\tSR=", wMSR," "); + + if (regf.fRDWE) begin + case (rMXDST) + 2'o2: begin + if (dwb_stb_o) $writeh("R",rRW,"=RAM(h",regf.xWDAT,")"); + if (fsl_stb_o) $writeh("R",rRW,"=FSL(h",regf.xWDAT,")"); + end + 2'o1: $writeh("R",rRW,"=LNK(h",regf.xWDAT,")"); + 2'o0: $writeh("R",rRW,"=ALU(h",regf.xWDAT,")"); + endcase // case (rMXDST) + end + + // STORE + if (dwb_stb_o & dwb_wre_o) begin + $writeh("RAM(", dwb_adr ,")=", dwb_dat_o); + case (dwb_sel_o) + 4'hF: $write(":L"); + 4'h3,4'hC: $write(":W"); + 4'h1,4'h2,4'h4,4'h8: $write(":B"); + endcase // case (dwb_sel_o) + + end + + end // if (gena) + +`endif // `ifdef AEMB_SIMULATION_KERNEL + // synopsys translate_on + endmodule // aeMB_edk32