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From: cvs at opencores.org<cvs@o...>
Date: Wed Oct 24 23:50:55 CEST 2007
Subject: [cvs-checkins] MODIFIED: s1_core ...
Date: 00/07/10 24:23:50

Modified: s1_core/tools/src build_dc.cmd
Log:
Modified to use XG syntax




Revision Changes Path
1.2 s1_core/tools/src/build_dc.cmd

http://www.opencores.org/cvsweb.shtml/s1_core/tools/src/build_dc.cmd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: build_dc.cmd
===================================================================
RCS file: /cvsroot/fafa1971/s1_core/tools/src/build_dc.cmd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- build_dc.cmd 4 Jan 2007 02:22:22 -0000 1.1
+++ build_dc.cmd 24 Oct 2007 21:50:55 -0000 1.2
@@ -7,13 +7,13 @@
/* check_design */

create_clock -period 2.0 -name sys_clock_i find(port, "sys_clock_i")
-set_input_delay 1 -max -clock sys_clock_i all_inputs() - find(port, "sys_clock_i")
+set_input_delay -max -clock sys_clock_i 1 all_inputs () find (port, "sys_clock_i")
set_output_delay 1 -max -clock sys_clock_i all_outputs()

compile -map_effort high

-write -format db -hierarchy -output s1_top.db
-write -format verilog -hierarchy -output s1_top.v
+write -output s1_top.db -format ddc -hierarchy
+write -output s1_top.v -format verilog -hierarchy

report_area > report_area.txt
report_timing > report_timing.txt