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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Jun 4 21:38:51 CEST 2007
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/07/06 04:21:38 Modified: jop/vhdl/top jop_256x16.vhd
Log:
records
Revision Changes Path
1.3 jop/vhdl/top/jop_256x16.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/top/jop_256x16.vhd.diff?r1=1.2&r2=1.3
(In the diff below, changes in quantity of whitespace are not shown.)
Index: jop_256x16.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/top/jop_256x16.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- jop_256x16.vhd 17 Aug 2006 00:42:12 -0000 1.2
+++ jop_256x16.vhd 4 Jun 2007 19:38:51 -0000 1.3
@@ -4,6 +4,7 @@
-- top level for a 256x16 SRMA board (e.g. Altera DE2 board)
--
-- 2006-08-06 adapted from jopcyc.vhd
+-- 2007-06-04 Use jopcpu and change component interface to records
--
--
@@ -13,14 +14,13 @@
use ieee.numeric_std.all;
use work.jop_types.all;
+use work.sc_pack.all;
use work.jop_config.all;
entity jop is
generic (
- exta_width : integer := 3; -- length of exta part in JOP microcode
- io_addr_bits : integer := 7; -- address bits of internal io
ram_cnt : integer := 2; -- clock cycles for external ram
-- rom_cnt : integer := 3; -- clock cycles for external rom OK for 20 MHz
rom_cnt : integer := 15; -- clock cycles for external rom for 100 MHz
@@ -69,70 +69,36 @@
);
end component;
-component core is
-generic(jpc_width : integer); -- address bits of java bytecode pc
-port (
- clk, reset : in std_logic;
-
--- memio connection
-
- bsy : in std_logic;
- din : in std_logic_vector(31 downto 0);
- ext_addr : out std_logic_vector(exta_width-1 downto 0);
- rd, wr : out std_logic;
-
--- jbc connections
- jbc_addr : out std_logic_vector(jpc_width-1 downto 0);
- jbc_data : in std_logic_vector(7 downto 0);
-
--- interrupt from io
-
- irq : in std_logic;
- irq_ena : in std_logic;
-
- exc_int : in std_logic;
- sp_ov : out std_logic;
+--
+-- Signals
+--
+ signal clk_int : std_logic;
- aout : out std_logic_vector(31 downto 0);
- bout : out std_logic_vector(31 downto 0)
-);
-end component;
+ signal int_res : std_logic;
+ signal res_cnt : unsigned(2 downto 0) := "000"; -- for the simulation
+ attribute altera_attribute : string;
+ attribute altera_attribute of res_cnt : signal is "POWER_UP_LEVEL=LOW";
--
--- Signals
+-- jopcpu connections
--
- signal clk_int : std_logic;
+ signal sc_mem_out : sc_mem_out_type;
+ signal sc_mem_in : sc_in_type;
+ signal sc_io_out : sc_io_out_type;
+ signal sc_io_in : sc_in_type;
+ signal irq_in : irq_in_type;
+ signal exc_req : exception_type;
- signal stack_tos : std_logic_vector(31 downto 0);
- signal stack_nos : std_logic_vector(31 downto 0);
- signal rd, wr : std_logic;
- signal ext_addr : std_logic_vector(exta_width-1 downto 0);
- signal stack_din : std_logic_vector(31 downto 0);
-
--- extension/mem interface
-
- signal mem_rd : std_logic;
- signal mem_wr : std_logic;
- signal mem_addr_wr : std_logic;
- signal mem_bc_rd : std_logic;
- signal mem_dout : std_logic_vector(31 downto 0);
- signal mem_bcstart : std_logic_vector(31 downto 0);
- signal mem_bsy : std_logic;
- signal bsy : std_logic;
-
- signal jbc_addr : std_logic_vector(jpc_width-1 downto 0);
- signal jbc_data : std_logic_vector(7 downto 0);
-
--- mem/sc interface
-
- signal sc_address : std_logic_vector(17 downto 0);
- signal sc_wr_data : std_logic_vector(31 downto 0);
- signal sc_rd, sc_wr : std_logic;
- signal sc_rd_data : std_logic_vector(31 downto 0);
- signal sc_rdy_cnt : unsigned(1 downto 0);
+--
+-- IO interface
+--
+ signal ser_in : ser_in_type;
+ signal ser_out : ser_out_type;
+ signal wd_out : std_logic;
+ -- for generation of internal reset
-- memory interface
signal ram_addr : std_logic_vector(17 downto 0);
@@ -143,35 +109,10 @@
signal ram_noe : std_logic;
signal ram_nwe : std_logic;
--- SimpCon io interface
-
- signal scio_address : std_logic_vector(io_addr_bits-1 downto 0);
- signal scio_wr_data : std_logic_vector(31 downto 0);
- signal scio_rd : std_logic;
- signal scio_wr : std_logic;
- signal scio_rd_data : std_logic_vector(31 downto 0);
- signal scio_rdy_cnt : unsigned(1 downto 0);
-
--- interrupt io interface
-
- signal io_irq : std_logic;
- signal io_irq_ena : std_logic;
-
- signal exc_req : exception_type;
- signal exc_int : std_logic;
-
- signal int_res : std_logic;
- signal res_cnt : unsigned(2 downto 0) := "000"; -- for the simulation
-
- signal wd_out, sp_ov : std_logic;
-
- -- for generation of internal reset
- attribute altera_attribute : string;
- attribute altera_attribute of res_cnt : signal is "POWER_UP_LEVEL=LOW";
-
-- not available at this board:
signal ser_ncts : std_logic;
signal ser_nrts : std_logic;
+
begin
ser_ncts <= '0';
@@ -204,76 +145,23 @@
);
-- clk_int <= clk;
- -- sp_ov indicates stack overflow
- -- We can use the wd LED
- -- wd <= sp_ov;
wd <= wd_out;
- cmp_core: core generic map(jpc_width)
- port map (clk_int, int_res,
- bsy,
- stack_din, ext_addr,
- rd, wr,
- jbc_addr, jbc_data,
- io_irq, io_irq_ena,
- exc_int, sp_ov,
- stack_tos, stack_nos
- );
- exc_req.spov <= sp_ov;
-
- cmp_ext: entity work.extension
- generic map (
- exta_width => exta_width,
- io_addr_bits => io_addr_bits
+ cpm_cpu: entity work.jopcpu
+ generic map(
+ jpc_width => jpc_width,
+ block_bits => block_bits
)
- port map (
- clk => clk_int,
- reset => int_res,
- ain => stack_tos,
- bin => stack_nos,
-
- ext_addr => ext_addr,
- rd => rd,
- wr => wr,
- bsy => bsy,
- dout => stack_din,
-
- mem_rd => mem_rd,
- mem_wr => mem_wr,
- mem_addr_wr => mem_addr_wr,
- mem_bc_rd => mem_bc_rd,
- mem_data => mem_dout,
- mem_bcstart => mem_bcstart,
- mem_bsy => mem_bsy,
-
- scio_address => scio_address,
- scio_wr_data => scio_wr_data,
- scio_rd => scio_rd,
- scio_wr => scio_wr,
- scio_rd_data => scio_rd_data,
- scio_rdy_cnt => scio_rdy_cnt
- );
+ port map(clk_int, int_res,
+ sc_mem_out, sc_mem_in,
+ sc_io_out, sc_io_in,
+ irq_in, exc_req);
cmp_io: entity work.scio
- generic map (
- addr_bits => io_addr_bits
- )
- port map (
- clk => clk_int,
- reset => int_res,
-
- address => scio_address,
- wr_data => scio_wr_data,
- rd => scio_rd,
- wr => scio_wr,
- rd_data => scio_rd_data,
- rdy_cnt => scio_rdy_cnt,
-
- irq => io_irq,
- irq_ena => io_irq_ena,
- exc_req => exc_req,
- exc_int => exc_int,
+ port map (clk_int, int_res,
+ sc_io_out, sc_io_in,
+ irq_in, exc_req,
txd => ser_txd,
rxd => ser_rxd,
@@ -286,51 +174,13 @@
b => open
);
- cmp_mem: entity work.mem_sc
- generic map (
- jpc_width => jpc_width,
- block_bits => block_bits,
- addr_bits => 18
- )
- port map (
- clk => clk_int,
- reset => int_res,
- din => stack_tos,
-
- mem_rd => mem_rd,
- mem_wr => mem_wr,
- mem_addr_wr => mem_addr_wr,
- mem_bc_rd => mem_bc_rd,
- dout => mem_dout,
- bcstart => mem_bcstart,
- bsy => mem_bsy,
-
- jbc_addr => jbc_addr,
- jbc_data => jbc_data,
-
- address => sc_address,
- wr_data => sc_wr_data,
- rd => sc_rd,
- wr => sc_wr,
- rd_data => sc_rd_data,
- rdy_cnt => sc_rdy_cnt
- );
-
cmp_scm: entity work.sc_mem_if
generic map (
ram_ws => ram_cnt-1,
addr_bits => 18
)
- port map (
- clk => clk_int,
- reset => int_res,
-
- address => sc_address,
- wr_data => sc_wr_data,
- rd => sc_rd,
- wr => sc_wr,
- rd_data => sc_rd_data,
- rdy_cnt => sc_rdy_cnt,
+ port map (clk_int, int_res,
+ sc_mem_out, sc_mem_in,
ram_addr => ram_addr,
ram_dout => ram_dout,
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