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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Mon Jun 4 21:37:12 CEST 2007
    Subject: [cvs-checkins] MODIFIED: jop ...
    Top
    Date: 00/07/06 04:21:37

    Modified: jop/vhdl/scio scio_usb.vhd
    Log:
    no message


    Revision Changes Path
    1.3 jop/vhdl/scio/scio_usb.vhd

    http://www.opencores.org/cvsweb.shtml/jop/vhdl/scio/scio_usb.vhd.diff?r1=1.2&r2=1.3

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: scio_usb.vhd
    ===================================================================
    RCS file: /cvsroot/martin/jop/vhdl/scio/scio_usb.vhd,v
    retrieving revision 1.2
    retrieving revision 1.3
    diff -u -b -r1.2 -r1.3
    --- scio_usb.vhd 14 Feb 2006 15:08:21 -0000 1.2
    +++ scio_usb.vhd 4 Jun 2007 19:37:11 -0000 1.3
    @@ -37,6 +37,7 @@
    use work.jop_config.all;

    entity scio is
    +generic (cpu_id : integer := 0);
    generic (addr_bits : integer);

    port (
    @@ -144,26 +145,27 @@
    end if;
    end process;

    - cmp_cnt: entity work.sc_cnt generic map (
    + cmp_sys: entity work.sc_sys generic map (
    addr_bits => SLAVE_ADDR_BITS,
    - clk_freq => clk_freq
    + clk_freq => clk_freq,
    + cpu_id => cpu_id
    )
    port map(
    clk => clk,
    reset => reset,

    - address => address(SLAVE_ADDR_BITS-1 downto 0),
    - wr_data => wr_data,
    + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0),
    + wr_data => sc_io_out.wr_data,
    rd => sc_rd(0),
    wr => sc_wr(0),
    rd_data => sc_dout(0),
    rdy_cnt => sc_rdy_cnt(0),

    - irq => irq,
    - irq_ena => irq_ena,
    -
    + irq_in => irq_in,
    exc_req => exc_req,
    - exc_int => exc_int,
    +
    + sync_out => sync_out,
    + sync_in => sync_in,

    wd => wd
    );
    @@ -181,8 +183,8 @@
    clk => clk,
    reset => reset,

    - address => address(SLAVE_ADDR_BITS-1 downto 0),
    - wr_data => wr_data,
    + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0),
    + wr_data => sc_io_out.wr_data,
    rd => sc_rd(1),
    wr => sc_wr(1),
    rd_data => sc_dout(1),
    @@ -202,8 +204,8 @@
    clk => clk,
    reset => reset,

    - address => address(SLAVE_ADDR_BITS-1 downto 0),
    - wr_data => wr_data,
    + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0),
    + wr_data => sc_io_out.wr_data,
    rd => sc_rd(2),
    wr => sc_wr(2),
    rd_data => sc_dout(2),



     
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