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Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Jun 1 18:51:40 CEST 2007
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/07/06 01:18:51 Modified: jop/quartus/cycmin jop.qsf Log: no message Revision Changes Path 1.19 jop/quartus/cycmin/jop.qsf http://www.opencores.org/cvsweb.shtml/jop/quartus/cycmin/jop.qsf.diff?r1=1.18&r2=1.19 (In the diff below, changes in quantity of whitespace are not shown.) Index: jop.qsf =================================================================== RCS file: /cvsroot/9914pich/jop/quartus/cycmin/jop.qsf,v retrieving revision 1.18 retrieving revision 1.19 diff -u -b -r1.18 -r1.19 --- jop.qsf 18 Mar 2007 01:46:57 -0000 1.18 +++ jop.qsf 1 Jun 2007 16:51:40 -0000 1.19 @@ -28,34 +28,7 @@ set_global_assignment -name SMART_RECOMPILE OFF set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:05:59 APRIL 04, 2004" -set_global_assignment -name LAST_QUARTUS_VERSION 6.1 -set_global_assignment -name VHDL_FILE ../../vhdl/top/jop_config_80.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/jop_types.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/simpcon/sc_pack.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/altera/cyc_pll.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/scio/fifo.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/scio/sc_uart.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/scio/sc_cnt.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/scio/scio_min.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/offtbl.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/jtbl.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/altera/arom.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/altera/aram.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/bcfetch.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/core.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/decode.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/fetch.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/memory/sc_sram32_flash.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/altera/cyc_jbc.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/memory/mem_sc.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/extension.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/cache.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/mul.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/shift.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/stack.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/core/jopcpu.vhd -set_global_assignment -name VHDL_FILE ../../vhdl/top/jopcyc.vhd -set_global_assignment -name CDF_FILE jop.cdf +set_global_assignment -name LAST_QUARTUS_VERSION 7.0 # Pin & Location Assignments # ========================== @@ -507,4 +480,34 @@ set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF + +set_global_assignment -name VHDL_FILE ../../vhdl/top/jop_config_80.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/jop_types.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/simpcon/sc_pack.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/altera/cyc_pll.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/scio/fifo.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/scio/sc_uart.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/scio/sc_sys.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/scio/scio_min.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/offtbl.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/jtbl.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/altera/arom.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/altera/aram.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/bcfetch.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/core.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/decode.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/fetch.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/memory/sc_sram32_flash.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/altera/cyc_jbc.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/memory/mem_sc.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/extension.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/cache.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/mul.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/shift.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/stack.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/core/jopcpu.vhd +set_global_assignment -name VHDL_FILE ../../vhdl/top/jopcyc.vhd +set_global_assignment -name CDF_FILE jop.cdf set_global_assignment -name VECTOR_WAVEFORM_FILE jop.vwf +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top \ No newline at end of file
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