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From: cvs at opencores.org<cvs@o...>
Date: Fri Apr 27 17:15:49 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/04 27:17:15

Modified: aemb/rtl/verilog aeMB_regfile.v
Log:
Fixed simulation bug.


Revision Changes Path
1.14 aemb/rtl/verilog/aeMB_regfile.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_regfile.v.diff?r1=1.13&r2=1.14

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_regfile.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_regfile.v,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -b -r1.13 -r1.14
--- aeMB_regfile.v 27 Apr 2007 04:22:40 -0000 1.13
+++ aeMB_regfile.v 27 Apr 2007 15:15:49 -0000 1.14
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.13 2007/04/27 04:22:40 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.14 2007/04/27 15:15:49 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -27,6 +27,9 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.14 2007/04/27 15:15:49 sybreon
+ * Fixed simulation bug.
+ *
* Revision 1.13 2007/04/27 04:22:40 sybreon
* Fixed minor synthesis bug.
*
@@ -230,7 +233,7 @@
// synopsys translate_off
integer i;
initial begin
- for (i=0;i<31;i=i+1) begin
+ for (i=0;i<32;i=i+1) begin
rMEMA[i] <= $random;
rMEMB[i] <= $random;
rMEMD[i] <= $random;