|
Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Apr 27 02:23:56 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/04 27:02:23 Modified: aemb/rtl/verilog aeMB_aslu.v aeMB_control.v aeMB_core.v
aeMB_decode.v aeMB_fetch.v aeMB_regfile.v
Log:
Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v
Revision Changes Path
1.7 aemb/rtl/verilog/aeMB_aslu.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_aslu.v.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB_aslu.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_aslu.v,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- aeMB_aslu.v 26 Apr 2007 14:29:53 -0000 1.6
+++ aeMB_aslu.v 27 Apr 2007 00:23:55 -0000 1.7
@@ -1,28 +1,34 @@
/*
- * $Id: aeMB_aslu.v,v 1.6 2007/04/26 14:29:53 sybreon Exp $
+ * $Id: aeMB_aslu.v,v 1.7 2007/04/27 00:23:55 sybreon Exp $
*
* AEMB Arithmetic Shift Logic Unit
- * Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
+ * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
- * This library is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation; either version 2.1 of the License,
- * or (at your option) any later version.
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
- * License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
*
* DESCRIPTION
- * Arithmetic, shift and logic execution unit
+ * Arithmetic, shift and logic execution unit. It also performs the
+ * necessary calculations for branch and load/store targets.
*
* HISTORY
* $Log: aeMB_aslu.v,v $
+ * Revision 1.7 2007/04/27 00:23:55 sybreon
+ * Added code documentation.
+ * Improved size & speed of rtl/verilog/aeMB_aslu.v
+ *
* Revision 1.6 2007/04/26 14:29:53 sybreon
* Made minor performance optimisations.
*
@@ -44,7 +50,6 @@
*
*/
-// 246 at 101
module aeMB_aslu (/*AUTOARG*/
// Outputs
dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL,
@@ -77,98 +82,72 @@
reg [31:0] rRESULT, xRESULT;
reg rMSR_C, xMSR_C;
- // Operands
- wire [31:0] wOPA, wOPB;
-
- // DWB I/F
- reg [31:0] rDWBADR;
- wire [31:0] wDWBADR;
-
- assign dwb_adr_o = {rDWBADR[DSIZ-1:2],2'b00};
- //assign wDWBADR = (wOPA + wOPB);
-
- reg [3:0] rDWBSEL, xDWBSEL;
-
- always @(/*AUTOSENSE*/rOPC or wDWBADR)
- case (wDWBADR[1:0])
- 2'o0: case (rOPC[1:0])
- 2'o0: xDWBSEL <= 4'h8;
- 2'o1: xDWBSEL <= 4'hC;
- default: xDWBSEL <= 4'hF;
- endcase // case (rOPC[1:0])
- 2'o1: case (rOPC[1:0])
- 2'o0: xDWBSEL <= 4'h4;
- default: xDWBSEL <= 4'h0;
- endcase // case (rOPC[1:0])
- 2'o2: case (rOPC[1:0])
- 2'o0: xDWBSEL <= 4'h2;
- 2'o1: xDWBSEL <= 4'h3;
- default: xDWBSEL <= 4'h0;
- endcase // case (rOPC[1:0])
- 2'o3: case (rOPC[1:0])
- 2'o0: xDWBSEL <= 4'h1;
- default: xDWBSEL <= 4'h0;
- endcase // case (rOPC[1:0])
- endcase // case (wDWBADR[1:0])
-
+ /**
+ Operand Selection
+ -----------------
+ Selects the A and B operands depending on the source. All
+ forwarding information is controlled by the decode unit.
+ */
- // Endian correction
- wire [31:0] wDWBDAT;
- assign dwb_sel_o = {rDWBSEL[0],rDWBSEL[1],rDWBSEL[2],rDWBSEL[3]};
- assign wDWBDAT = sDWBDAT;
+ wire [31:0] wOPA, wOPB;
- // Source and Target Select
assign wOPA =
- (rMXSRC == 2'b11) ? wDWBDAT :
+ (rMXSRC == 2'b11) ? sDWBDAT :
(rMXSRC == 2'b10) ? rRESULT :
(rMXSRC == 2'b01) ? rPC :
rREGA;
assign wOPB =
- (rMXTGT == 2'b11) ? wDWBDAT :
+ (rMXTGT == 2'b11) ? sDWBDAT :
(rMXTGT == 2'b10) ? rRESULT :
(rMXTGT == 2'b01) ? rSIMM :
rREGB;
- // ARITHMETIC
- //wire wADDC_ = (rOPC[1] & (rMXLDST == 2'o0)) ? rMSR_C : 1'b0;
- wire wADDC_ = (rOPC[1] & rMSR_C) & ~|rMXLDST;
- wire wSUBC_ = (rOPC[1] & rMSR_C | ~rOPC[1]);
+ /**
+ Simple Arithmetic
+ -----------------
+ Performs addition and subtraction using a single 32-bit adder with
+ carry in and out. This is done in parallel with other
+ operations. The adder is also used to calculate branch target
+ addresses as well as load/store memory addresses.
+
+ TODO: Verify signed compare
+ */
+
wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;
- // TODO: verify signed compare
-
wire wCMP0 = (wOPA[7:0] > wOPB[7:0]);
wire wCMP1 = (wOPA[15:8] > wOPB[15:8]);
wire wCMP2 = (wOPA[23:16] > wOPB[23:16]);
wire wCMP3 = (wOPA[31:24] > wOPB[31:24]);
- wire wCMPU = wCMP3 | (wCMP2 & ~wCMP3) | (wCMP1 & ~wCMP2 & ~wCMP3) | (wCMP0 & ~wCMP2 & ~wCMP3 & ~wCMP1);
-
- //wire wCMPU = (wOPA > wOPB);
+ wire wCMPU = (wOPA > wOPB);
wire wCMPF = (rIMM[1]) ? wCMPU :
((wCMPU & ~(wOPB[31] ^ wOPA[31])) | (wOPB[31] & ~wOPA[31]));
+
assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
- //assign {wADDC,wADD} = (wOPB + wOPA) + wADDC_;
- //assign {wSUBC,wSUB} = (wOPB + ~wOPA) + wSUBC_;
assign wOPX = (rOPC[0] & !rOPC[5]) ? ~wOPA : wOPA ;
- assign wOPC = (rOPC[0] & !rOPC[5]) ? wSUBC_ : wADDC_ ;
+ assign wOPC = ((rMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) & (!rOPC[5] & !rMXLDST[1]);
+
assign {wSUBC,wSUB} = {wADDC,wADD};
assign {wADDC,wADD} = (wOPB + wOPX) + wOPC;
- assign wDWBADR = wADD;
-
reg rRES_AC;
reg [31:0] rRES_A;
always @(/*AUTOSENSE*/rIMM or rOPC or wADD or wADDC or wCMP
or wCMPC or wSUB or wSUBC)
- //{rRES_AC,rRES_A} <= #1 (rOPC[0] & ~rOPC[5]) ? {~wSUBC,wSUB} : {wADDC,wADD};
case ({rOPC[3],rOPC[0],rIMM[0]})
4'h2, 4'h6, 4'h7: {rRES_AC,rRES_A} <= #1 {~wSUBC,wSUB}; // SUB
4'h3: {rRES_AC,rRES_A} <= #1 {~wCMPC,wCMP}; // CMP
default: {rRES_AC,rRES_A} <= #1 {wADDC,wADD};
- endcase // case ({rOPC[5],rOPC[3],rOPC[0],rIMM[0]})
+ endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
+
+ /**
+ Logic
+ -----
+ Performs all the simple logic functions in parallel with other
+ operations.
+ */
- // LOGIC
wire [31:0] wOR = wOPA | wOPB;
wire [31:0] wAND = wOPA & wOPB;
wire [31:0] wXOR = wOPA ^ wOPB;
@@ -183,7 +162,13 @@
2'o3: rRES_L <= #1 wANDN;
endcase // case (rOPC[1:0])
- // SHIFT
+ /**
+ Shifter
+ -------
+ Performs shift instructions as well as sign extension. This is
+ done in parallel with the other operations.
+ */
+
wire wSRAC, wSRCC, wSRLC, wRES_SC;
wire [31:0] wSRA,wSRC, wSRL, wSEXT8, wSEXT16, wRES_S;
assign {wSRAC,wSRA} = {wOPA[0],wOPA[0],wOPA[31:1]};
@@ -204,40 +189,80 @@
2'o3: {rRES_SC,rRES_S} <= #1 (rIMM[0]) ? {rMSR_C,wSEXT16} : {rMSR_C,wSEXT8};
endcase // case (rIMM[6:5])
- // MOVE
+ /**
+ Mover
+ -----
+ Moves an operand from source to destination for move instructions
+ done in parallel with other operations.
+ */
+
reg [31:0] rRES_M;
always @(/*AUTOSENSE*/rRA or wOPA or wOPB)
rRES_M <= #1 (rRA[3]) ? wOPB : wOPA;
- // RESULT + C
- always @(/*AUTOSENSE*/drun or rMSR_C or rMXALU or rOPC or rRES_A
- or rRES_AC or rRES_L or rRES_M or rRES_S or rRES_SC)
- if (drun) begin
+ /**
+ Data WISHBONE Bus
+ -----------------
+ Asserts the appropriate byte select signals depending on the size
+ of the operation and the address location. For faster operation,
+ the result of the adder is used as the end selector.
+
+ FIXME: It does not check for invalid memory locations.
+ FIXME: Endian correction!
+ */
+
+ reg [3:0] rDWBSEL, xDWBSEL;
+ assign dwb_adr_o = {rRESULT[DSIZ-1:2],2'b00};
+ assign dwb_sel_o = {rDWBSEL[0],rDWBSEL[1],rDWBSEL[2],rDWBSEL[3]};
+
+ always @(/*AUTOSENSE*/rOPC or wADD)
+ case (wADD[1:0])
+ 2'o0: case (rOPC[1:0])
+ 2'o0: xDWBSEL <= 4'h8;
+ 2'o1: xDWBSEL <= 4'hC;
+ default: xDWBSEL <= 4'hF;
+ endcase // case (rOPC[1:0])
+ 2'o1: xDWBSEL <= 4'h4;
+ 2'o2: xDWBSEL <= (rOPC[0]) ? 4'h3 : 4'h2;
+ 2'o3: xDWBSEL <= 4'h1;
+ endcase // case (wADD[1:0])
+
+ /**
+ RESULT + C
+ ----------
+ The RESULT and MSR[C] are collected at the end of the pipeline,
+ depending on the operation selected. This was done in order to
+ allow the operations to proceed in parallel for faster speed.
+
+ FIXME: rMSR[C] might need to be blocked (drun) during a branch.
+ TODO: MTS/MFS instruction
+ */
+
+ always @(/*AUTOSENSE*/rMXALU or rRES_A or rRES_L or rRES_M
+ or rRES_S) begin
case (rMXALU)
2'o0: xRESULT <= #1 rRES_A;
2'o1: xRESULT <= #1 rRES_L;
2'o2: xRESULT <= #1 rRES_S;
2'o3: xRESULT <= #1 rRES_M;
endcase // case (rMXALU)
+ end
+
+ always @(/*AUTOSENSE*/rMSR_C or rMXALU or rOPC or rRES_AC
+ or rRES_SC) begin
case (rMXALU)
2'o0: xMSR_C <= #1 (rOPC[2]) ? rMSR_C : rRES_AC;
2'o2: xMSR_C <= #1 rRES_SC;
default: xMSR_C <= #1 rMSR_C;
endcase // case (rMXALU)
- end else begin // if (drun)
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- xMSR_C <= 1'h0;
- xRESULT <= 32'h0;
- // End of automatics
- end // else: !if(drun)
+ end
// PIPELINE REGISTER //////////////////////////////////////////////////
+
always @(negedge nclk or negedge nrst)
if (!nrst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
- rDWBADR <= 32'h0;
rDWBSEL <= 4'h0;
rMSR_C <= 1'h0;
rRESULT <= 32'h0;
@@ -245,7 +270,6 @@
end else if (nrun) begin
rRESULT <= #1 xRESULT;
rMSR_C <= #1 xMSR_C;
- rDWBADR <= #1 wDWBADR;
rDWBSEL <= #1 xDWBSEL;
end
1.4 aemb/rtl/verilog/aeMB_control.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_control.v.diff?r1=1.3&r2=1.4
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB_control.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_control.v,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- aeMB_control.v 11 Apr 2007 04:30:43 -0000 1.3
+++ aeMB_control.v 27 Apr 2007 00:23:55 -0000 1.4
@@ -1,28 +1,33 @@
/*
- * $Id: aeMB_control.v,v 1.3 2007/04/11 04:30:43 sybreon Exp $
+ * $Id: aeMB_control.v,v 1.4 2007/04/27 00:23:55 sybreon Exp $
*
* AE68 System Control Unit
- * Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
+ * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
- * This library is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation; either version 2.1 of the License,
- * or (at your option) any later version.
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
- * License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
*
* DESCRIPTION
* Controls the state of the processor.
*
* HISTORY
* $Log: aeMB_control.v,v $
+ * Revision 1.4 2007/04/27 00:23:55 sybreon
+ * Added code documentation.
+ * Improved size & speed of rtl/verilog/aeMB_aslu.v
+ *
* Revision 1.3 2007/04/11 04:30:43 sybreon
* Added pipeline stalling from incomplete bus cycles.
* Separated sync and async portions of code.
@@ -35,7 +40,6 @@
*
*/
-// 6 at 250
module aeMB_control (/*AUTOARG*/
// Outputs
rFSM, nclk, nrst, nrun, frun, drun,
@@ -47,7 +51,6 @@
input sys_rst_i, sys_clk_i;
input sys_int_i;
input sys_exc_i;
- //input sys_run_i;
// Instruction WB
input rIWBSTB;
@@ -64,13 +67,25 @@
output nclk, nrst, nrun;
output frun, drun;
- // Clock code here
- assign nclk = sys_clk_i;
+ /**
+ RUN Signal
+ ----------
+ This master run signal will pause or run the entire pipeline. It
+ will pause for any incomplete bus transaction.
+ */
+
+ assign nrun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
+
+ /**
+ Debounce
+ --------
+ The following external signals are debounced and synchronised:
+ - Reset
+ - Interrupt
+ */
- // Debounce reset
reg [1:0] rRST;
- assign nrst = rRST[1];
- always @(posedge nclk or negedge sys_rst_i)
+ always @(negedge nclk or negedge sys_rst_i)
if (!sys_rst_i) begin
//rNRST <= 2'h3;
/*AUTORESET*/
@@ -81,24 +96,27 @@
rRST <= {rRST[0],1'b1};
end
- // Quiet RUN signal
- assign nrun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
-
- // Debounce Interrupt/Exception Signals
reg [2:0] rEXC, rINT;
always @(negedge nclk or negedge nrst)
if (!nrst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
- rEXC <= 3'h0;
rINT <= 3'h0;
// End of automatics
end else if (nrun) begin
- rEXC <= #1 {rEXC[1:0], sys_exc_i};
+ //rEXC <= #1 {rEXC[1:0], sys_exc_i};
rINT <= #1 {rINT[1:0], sys_int_i};
end
- // Machine States
+ /**
+ Machine States
+ --------------
+ The internal machine state is affected by external interrupt,
+ exception and software exceptions. Only interrupts are
+ implemented.
+
+ TODO: Implement exceptions.
+ */
parameter [1:0]
FSM_RUN = 2'o0,
FSM_SWEXC = 2'o3,
@@ -116,19 +134,26 @@
rFSM <= #1 rNXT;
end
- always @(/*AUTOSENSE*/rEXC or rFSM or rINT)
+ always @(/*AUTOSENSE*/rFSM or rINT)
case (rFSM)
FSM_HWEXC: rNXT <= FSM_RUN;
//FSM_SWEXC: rNXT <= FSM_RUN;
FSM_HWINT: rNXT <= FSM_RUN;
default: begin
- rNXT <= (rEXC == 3'h3) ? FSM_HWEXC :
+ rNXT <= //(rEXC == 3'h3) ? FSM_HWEXC :
(rINT == 3'h3) ? FSM_HWINT :
FSM_RUN;
end
endcase // case (rFSM)
- // Pause/Bubble
+ /**
+ Bubble
+ ------
+ Pipeline bubbles are introduced during a branch or interrupt.
+
+ TODO: Implement interrupt bubble.
+ */
+
reg [1:0] rRUN;
assign {drun,frun} = rRUN;
@@ -140,4 +165,15 @@
rRUN <= #1 {~(rBRA ^ rDLY), ~rBRA};
end
+ /**
+ Clock/Reset
+ -----------
+ This controls the internal clock/reset signal for the core. Any
+ DCM/PLL/DPLL can be instantiated here if needed.
+ */
+
+ assign nclk = sys_clk_i;
+ assign nrst = rRST[1];
+
+
endmodule // aeMB_control
1.5 aemb/rtl/verilog/aeMB_core.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_core.v.diff?r1=1.4&r2=1.5
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB_core.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_core.v,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- aeMB_core.v 25 Apr 2007 22:15:04 -0000 1.4
+++ aeMB_core.v 27 Apr 2007 00:23:55 -0000 1.5
@@ -1,22 +1,23 @@
/*
- * $Id: aeMB_core.v,v 1.4 2007/04/25 22:15:04 sybreon Exp $
+ * $Id: aeMB_core.v,v 1.5 2007/04/27 00:23:55 sybreon Exp $
*
* AEMB 32-bit Microblaze Compatible Core
- * Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
+ * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
- * This library is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation; either version 2.1 of the License,
- * or (at your option) any later version.
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
- * License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
*
* DESCRIPTION
* Microblaze compatible, WISHBONE compliant hardware core. This core is
@@ -25,6 +26,10 @@
*
* HISTORY
* $Log: aeMB_core.v,v $
+ * Revision 1.5 2007/04/27 00:23:55 sybreon
+ * Added code documentation.
+ * Improved size & speed of rtl/verilog/aeMB_aslu.v
+ *
* Revision 1.4 2007/04/25 22:15:04 sybreon
* Added support for 8-bit and 16-bit data types.
*
@@ -61,7 +66,7 @@
output dwb_stb_o; // From decode of aeMB_decode.v
output dwb_we_o; // From decode of aeMB_decode.v
output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v
- output iwb_stb_o; // From decode of aeMB_decode.v
+ output iwb_stb_o; // From fetch of aeMB_fetch.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
@@ -88,7 +93,7 @@
wire rDWBWE; // From decode of aeMB_decode.v
wire [1:0] rFSM; // From control of aeMB_control.v
wire [15:0] rIMM; // From decode of aeMB_decode.v
- wire rIWBSTB; // From decode of aeMB_decode.v
+ wire rIWBSTB; // From fetch of aeMB_fetch.v
wire rLNK; // From decode of aeMB_decode.v
wire [1:0] rMXALU; // From decode of aeMB_decode.v
wire [1:0] rMXLDST; // From decode of aeMB_decode.v
@@ -99,7 +104,6 @@
wire [4:0] rRA; // From decode of aeMB_decode.v
wire [4:0] rRB; // From decode of aeMB_decode.v
wire [4:0] rRD; // From decode of aeMB_decode.v
- wire [4:0] rRD_; // From decode of aeMB_decode.v
wire [31:0] rREGA; // From regfile of aeMB_regfile.v
wire [31:0] rREGB; // From regfile of aeMB_regfile.v
wire [31:0] rRESULT; // From aslu of aeMB_aslu.v
@@ -108,6 +112,8 @@
wire [31:0] sDWBDAT; // From regfile of aeMB_regfile.v
// End of automatics
+ // INSTANTIATIONS /////////////////////////////////////////////////////////////////
+
aeMB_regfile #(DSIZ)
regfile (/*AUTOINST*/
// Outputs
@@ -122,7 +128,6 @@
.rRA (rRA[4:0]),
.rRB (rRB[4:0]),
.rRD (rRD[4:0]),
- .rRD_ (rRD_[4:0]),
.rRESULT (rRESULT[31:0]),
.rFSM (rFSM[1:0]),
.rPC (rPC[31:0]),
@@ -139,7 +144,9 @@
fetch (/*AUTOINST*/
// Outputs
.iwb_adr_o (iwb_adr_o[ISIZ-1:0]),
+ .iwb_stb_o (iwb_stb_o),
.rPC (rPC[31:0]),
+ .rIWBSTB (rIWBSTB),
// Inputs
.iwb_dat_i (iwb_dat_i[31:0]),
.nclk (nclk),
@@ -208,18 +215,15 @@
.rRA (rRA[4:0]),
.rRB (rRB[4:0]),
.rRD (rRD[4:0]),
- .rRD_ (rRD_[4:0]),
.rOPC (rOPC[5:0]),
.rIMM (rIMM[15:0]),
.rDWBSTB (rDWBSTB),
.rDWBWE (rDWBWE),
- .rIWBSTB (rIWBSTB),
.rDLY (rDLY),
.rLNK (rLNK),
.rBRA (rBRA),
.rRWE (rRWE),
.rMXLDST (rMXLDST[1:0]),
- .iwb_stb_o (iwb_stb_o),
.dwb_stb_o (dwb_stb_o),
.dwb_we_o (dwb_we_o),
// Inputs
1.6 aemb/rtl/verilog/aeMB_decode.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_decode.v.diff?r1=1.5&r2=1.6
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB_decode.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_decode.v,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -b -r1.5 -r1.6
--- aeMB_decode.v 25 Apr 2007 22:15:04 -0000 1.5
+++ aeMB_decode.v 27 Apr 2007 00:23:55 -0000 1.6
@@ -1,28 +1,33 @@
/*
- * $Id: aeMB_decode.v,v 1.5 2007/04/25 22:15:04 sybreon Exp $
+ * $Id: aeMB_decode.v,v 1.6 2007/04/27 00:23:55 sybreon Exp $
*
* AEMB Instruction Decoder
- * Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
+ * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
- * This library is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation; either version 2.1 of the License,
- * or (at your option) any later version.
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
- * License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
*
* DESCRIPTION
* Instruction decoder
*
* HISTORY
* $Log: aeMB_decode.v,v $
+ * Revision 1.6 2007/04/27 00:23:55 sybreon
+ * Added code documentation.
+ * Improved size & speed of rtl/verilog/aeMB_aslu.v
+ *
* Revision 1.5 2007/04/25 22:15:04 sybreon
* Added support for 8-bit and 16-bit data types.
*
@@ -41,12 +46,10 @@
*
*/
-// 88 at 143
module aeMB_decode (/*AUTOARG*/
// Outputs
- rSIMM, rMXALU, rMXSRC, rMXTGT, rRA, rRB, rRD, rRD_, rOPC, rIMM,
- rDWBSTB, rDWBWE, rIWBSTB, rDLY, rLNK, rBRA, rRWE, rMXLDST,
- iwb_stb_o, dwb_stb_o, dwb_we_o,
+ rSIMM, rMXALU, rMXSRC, rMXTGT, rRA, rRB, rRD, rOPC, rIMM, rDWBSTB,
+ rDWBWE, rDLY, rLNK, rBRA, rRWE, rMXLDST, dwb_stb_o, dwb_we_o,
// Inputs
sDWBDAT, rDWBSEL, rREGA, rRESULT, iwb_dat_i, nclk, nrst, drun,
frun, nrun
@@ -55,10 +58,10 @@
output [31:0] rSIMM;
output [1:0] rMXALU;
output [1:0] rMXSRC, rMXTGT;
- output [4:0] rRA, rRB, rRD, rRD_;
+ output [4:0] rRA, rRB, rRD;
output [5:0] rOPC;
output [15:0] rIMM;
- output rDWBSTB, rDWBWE, rIWBSTB;
+ output rDWBSTB, rDWBWE;
output rDLY, rLNK, rBRA, rRWE;
output [1:0] rMXLDST;
input [31:0] sDWBDAT;
@@ -67,32 +70,35 @@
// External I/F
input [31:0] iwb_dat_i;
- //, dwb_dat_i;
- output iwb_stb_o;
output dwb_stb_o, dwb_we_o;
// System I/F
input nclk, nrst, drun, frun, nrun;
- // Endian Correction
+ /**
+ rOPC/rRD/rRA/rRB/rIMM
+ ---------------------
+ Instruction latch for the different fields of the instruction
+ ISA. This part may be changed in the future to incorporate an
+ instruction cache.
+
+ FIXME: Endian correction!
+ TODO: Modify this for block RAM based instruction cache.
+ */
wire [31:0] wIREG;
- wire [31:0] wWBDAT;
assign wIREG = {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]};
- assign wWBDAT = sDWBDAT;
- // Decode
wire [5:0] wOPC = wIREG[31:26];
wire [4:0] wRD = wIREG[25:21];
wire [4:0] wRA = wIREG[20:16];
wire [4:0] wRB = wIREG[15:11];
wire [15:0] wIMM = wIREG[15:0];
- // rOPC, rRD, rRA, rRB, rIMM;
reg [5:0] rOPC;
- reg [4:0] rRD, rRA, rRB, rRD_;
+ reg [4:0] rRD, rRA, rRB;
reg [15:0] rIMM;
reg [5:0] xOPC;
- reg [4:0] xRD, xRA, xRB, xRD_;
+ reg [4:0] xRD, xRA, xRB;
reg [15:0] xIMM;
always @(/*AUTOSENSE*/frun or wIMM or wOPC or wRA or wRB or wRD)
@@ -113,17 +119,13 @@
// End of automatics
end // else: !if(frun)
- always @(/*AUTOSENSE*/drun or rRD)
- if (drun) begin
- xRD_ <= rRD;
- end else begin
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- xRD_ <= 5'h0;
- // End of automatics
- end
+ /**
+ Opcode Groups
+ -------------
+ Start decoding by breaking up the opcode into groups. This should
+ infer a bunch of decoders on appropriate synthesis tools.
+ */
- // Groups
wire fGH0 = (wOPC[5:3] == 3'o0);
wire fGH1 = (wOPC[5:3] == 3'o1);
wire fGH2 = (wOPC[5:3] == 3'o2);
@@ -141,7 +143,13 @@
wire fGL6 = (wOPC[2:0] == 3'o6);
wire fGL7 = (wOPC[2:0] == 3'o7);
- // Decode Logic
+ /*
+ Main Decoder
+ ------------
+ As there aren't many instruction groups to decode, we will decode
+ all the instruction families here.
+ */
+
wire fADD = ({wOPC[5:4],wOPC[0]} == 3'o0);
wire fSUB = ({wOPC[5:4],wOPC[0]} == 3'o1);
wire fLOGIC = ({wOPC[5:4],wOPC[2]} == 3'o4);
@@ -159,7 +167,12 @@
wire fRET = fGH5 & fGL5;
wire fMISC = fGH4 & fGL5;
- // MXALU
+ /**
+ MXALU
+ -----
+ This signal controls the MXALU mux inside the ASLU unit.
+ */
+
reg [1:0] rMXALU, xMXALU;
always @(/*AUTOSENSE*/fBRA or fLOGIC or fSHIFT or frun)
if (frun) begin
@@ -175,7 +188,13 @@
// End of automatics
end // else: !if(frun)
- // BCC/BRA/RET
+ /**
+ BCC/BRA/RET
+ -----------
+ This signal controls the associated muxes for BRANCH, DELAY and
+ LINK operations.
+ */
+
reg rMXDLY,rMXLNK,xMXDLY,xMXLNK;
reg [1:0] rMXBRA,xMXBRA;
always @(/*AUTOSENSE*/fBCC or fBRU or fRET or frun or wRA or wRD)
@@ -201,7 +220,13 @@
// End of automatics
end // else: !if(frun)
- // LD ST
+ /**
+ LD/ST
+ -----
+ This signal controls the mux that controls the LOAD and STORE
+ operations.
+ */
+
reg [1:0] rMXLDST,xMXLDST;
always @(/*AUTOSENSE*/fLD or fST or frun)
if (frun) begin
@@ -216,10 +241,15 @@
// End of automatics
end // else: !if(frun)
- // SRC/TGT - incorporates forwarding
+ /**
+ SRC/TGT
+ -------
+ Controls the muxes that select the appropriate sources for the A,
+ B and D operands. All data hazards are resolved here.
+ */
+
reg [1:0] rMXSRC, rMXTGT, rMXALT, xMXSRC,xMXTGT,xMXALT;
wire fRWE = (rRD != 5'd0) & (rMXBRA != 2'o3);
- //wire fFWDBCC = (rMXBRA != 2'o3);
always @(/*AUTOSENSE*/fBCC or fBRU or fRWE or frun or rMXLDST
or rRD or wOPC or wRA or wRB)
@@ -248,7 +278,13 @@
// End of automatics
end // else: !if(frun)
- // IMM processing
+ /**
+ IMM Latching
+ ------------
+ The logic to generate either a full 32-bit or sign extended 32-bit
+ immediate is done here.
+ */
+
reg [31:0] rSIMM, xSIMM;
reg [15:0] rIMMHI, xIMMHI;
reg rFIMM, xFIMM;
@@ -267,11 +303,16 @@
// End of automatics
end // else: !if(frun)
- // CC
- // COMPARATOR
- //wire [31:0] wREGA = rREGA;
+ /**
+ COMPARATOR
+ ----------
+ This performs the comparison for conditional branches. It handles
+ the necessary data hazards. It generates a branch flag that is
+ used by the execution stage.
+ */
+
wire [31:0] wREGA =
- (rMXALT == 2'o3) ? wWBDAT :
+ (rMXALT == 2'o3) ? sDWBDAT :
(rMXALT == 2'o2) ? rRESULT :
rREGA;
@@ -295,7 +336,13 @@
default: rBCC <= 1'b0;
endcase // case (rRD[2:0])
- // Branch Signal
+ /**
+ Branch Signals
+ --------------
+ This controls the generation of the BRANCH, DELAY and LINK
+ signals.
+ */
+
reg rBRA, rDLY, rLNK, xBRA, xDLY, xLNK;
always @(/*AUTOSENSE*/drun or rBCC or rMXBRA or rMXDLY or rMXLNK)
if (drun) begin
@@ -324,9 +371,14 @@
// End of automatics
end // else: !if(drun)
- // MXRWE
+ /**
+ MXRWE
+ -----
+ This signal controls the flag that determines whether a D register
+ is open for writing.
+ */
reg rRWE, xRWE;
- wire wRWE = (rRD != 5'd0);
+ wire wRWE = |rRD;
always @(/*AUTOSENSE*/drun or rMXBRA or rMXLDST or wRWE)
if (drun) begin
case (rMXBRA)
@@ -341,7 +393,13 @@
// End of automatics
end // else: !if(drun)
- // DWB logic
+ /**
+ Data WISHBONE Bus
+ -----------------
+ The STB and WE signals for the DWB are decoded here depending on
+ the LOAD/STORE control signal.
+ */
+
reg rDWBSTB, rDWBWE, xDWBSTB, xDWBWE;
assign dwb_stb_o = rDWBSTB;
assign dwb_we_o = rDWBWE;
@@ -358,10 +416,6 @@
// End of automatics
end
- // WB other signals
- assign iwb_stb_o = rIWBSTB;
- assign rIWBSTB = 1'b1;
-
// PIPELINE REGISTERS ///////////////////////////////////////////////
always @(negedge nclk or negedge nrst)
@@ -369,9 +423,14 @@
rOPC <= 6'o40;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
+ rBRA <= 1'h0;
+ rDLY <= 1'h0;
+ rDWBSTB <= 1'h0;
+ rDWBWE <= 1'h0;
rFIMM <= 1'h0;
rIMM <= 16'h0;
rIMMHI <= 16'h0;
+ rLNK <= 1'h0;
rMXALT <= 2'h0;
rMXALU <= 2'h0;
rMXBRA <= 2'h0;
@@ -383,6 +442,7 @@
rRA <= 5'h0;
rRB <= 5'h0;
rRD <= 5'h0;
+ rRWE <= 1'h0;
rSIMM <= 32'h0;
// End of automatics
end else if (nrun) begin // if (!nrst)
@@ -405,29 +465,14 @@
rSIMM <= #1 xSIMM;
rFIMM <= #1 xFIMM;
rIMMHI <= #1 xIMMHI;
- end // if (nrun)
- always @(negedge nclk or negedge nrst)
- if (!nrst) begin
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- rBRA <= 1'h0;
- rDLY <= 1'h0;
- rDWBSTB <= 1'h0;
- rDWBWE <= 1'h0;
- rLNK <= 1'h0;
- rRD_ <= 5'h0;
- rRWE <= 1'h0;
- // End of automatics
- end else if (nrun) begin // if (!nrst)
- rRD_ <= #1 xRD_;
rBRA <= #1 xBRA;
rDLY <= #1 xDLY;
rLNK <= #1 xLNK;
rRWE <= #1 xRWE;
rDWBSTB <= #1 xDWBSTB;
rDWBWE <= #1 xDWBWE;
- end
+ end // if (nrun)
endmodule // aeMB_decode
1.4 aemb/rtl/verilog/aeMB_fetch.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_fetch.v.diff?r1=1.3&r2=1.4
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB_fetch.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_fetch.v,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- aeMB_fetch.v 11 Apr 2007 04:30:43 -0000 1.3
+++ aeMB_fetch.v 27 Apr 2007 00:23:55 -0000 1.4
@@ -1,28 +1,34 @@
/*
- * $Id: aeMB_fetch.v,v 1.3 2007/04/11 04:30:43 sybreon Exp $
+ * $Id: aeMB_fetch.v,v 1.4 2007/04/27 00:23:55 sybreon Exp $
*
* AEMB Instruction Fetch
- * Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
+ * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
- * This library is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation; either version 2.1 of the License,
- * or (at your option) any later version.
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
- * License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
*
* DESCRIPTION
- * Controls the instruction side of AEMB.
+ * Controls the instruction side of AEMB. Instruction cache and branch
+ * prediction can be incorporated if needed.
*
* HISTORY
* $Log: aeMB_fetch.v,v $
+ * Revision 1.4 2007/04/27 00:23:55 sybreon
+ * Added code documentation.
+ * Improved size & speed of rtl/verilog/aeMB_aslu.v
+ *
* Revision 1.3 2007/04/11 04:30:43 sybreon
* Added pipeline stalling from incomplete bus cycles.
* Separated sync and async portions of code.
@@ -35,11 +41,9 @@
*
*/
-// 50 at 135
-
module aeMB_fetch (/*AUTOARG*/
// Outputs
- iwb_adr_o, rPC,
+ iwb_adr_o, iwb_stb_o, rPC, rIWBSTB,
// Inputs
iwb_dat_i, nclk, nrst, nrun, rFSM, rBRA, rRESULT
);
@@ -47,6 +51,7 @@
// Instruction WB I/F
output [ISIZ-1:0] iwb_adr_o;
+ output iwb_stb_o;
input [31:0] iwb_dat_i;
// System
@@ -54,16 +59,22 @@
// Internal
output [31:0] rPC;
- //output [31:0] rPCNXT;
+ output rIWBSTB;
input [1:0] rFSM;
input rBRA;
input [31:0] rRESULT;
- // WB ADR signal
- reg [31:0] rIWBADR, rPC, xIWBADR, xPC;
+ /**
+ Instruction WISHBONE bus
+ ------------------------
+ Signals for the instruction side of the bus.
+ */
+ reg [31:0] rIWBADR, rPC, xIWBADR, xPC;
wire [31:0] wPCNXT = {(rIWBADR[ISIZ-1:2] + 1'b1),2'b00};
assign iwb_adr_o = {rIWBADR[ISIZ-1:2],2'b00}; // Word Aligned
+ assign iwb_stb_o = 1'b1;
+ assign rIWBSTB = 1'b1;
always @(/*AUTOSENSE*/rBRA or rFSM or rIWBADR or rRESULT or wPCNXT)
begin
1.12 aemb/rtl/verilog/aeMB_regfile.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_regfile.v.diff?r1=1.11&r2=1.12
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB_regfile.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_regfile.v,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -b -r1.11 -r1.12
--- aeMB_regfile.v 26 Apr 2007 14:29:53 -0000 1.11
+++ aeMB_regfile.v 27 Apr 2007 00:23:55 -0000 1.12
@@ -1,30 +1,36 @@
/*
- * $Id: aeMB_regfile.v,v 1.11 2007/04/26 14:29:53 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.12 2007/04/27 00:23:55 sybreon Exp $
*
* AEMB Register File
- * Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
+ * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
- * This library is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation; either version 2.1 of the License,
- * or (at your option) any later version.
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
- * License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
*
* DESCRIPTION
- * Implements the 32 registers as registers. Some registers require
- * special actions during hardware exception/interrupts. Data forwarding
- * is also taken care of inside here to simplify decode logic.
+ * Implements the 32 registers as memory. Some registers require
+ * special actions during hardware exception/interrupts. Data
+ * forwarding is also taken care of inside here to simplify decode
+ * logic.
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.12 2007/04/27 00:23:55 sybreon
+ * Added code documentation.
+ * Improved size & speed of rtl/verilog/aeMB_aslu.v
+ *
* Revision 1.11 2007/04/26 14:29:53 sybreon
* Made minor performance optimisations.
*
@@ -62,144 +68,169 @@
*
*/
-// 1284 at 78 - REG
-// 227 at 141 - RAM
module aeMB_regfile(/*AUTOARG*/
// Outputs
dwb_dat_o, rREGA, rREGB, sDWBDAT,
// Inputs
- dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRD_, rRESULT, rFSM,
- rPC, rOPC, rDWBSEL, rLNK, rRWE, nclk, nrst, drun, nrun
+ dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRESULT, rFSM, rPC,
+ rOPC, rDWBSEL, rLNK, rRWE, nclk, nrst, drun, nrun
);
- // Data WB bus width
+ // Data WB address bus width
parameter DSIZ = 32;
- // Data WB I/F
+ // Data WB Signals
output [31:0] dwb_dat_o;
input [31:0] dwb_dat_i;
- // Internal I/F
+ // Internal Signals
output [31:0] rREGA, rREGB;
output [31:0] sDWBDAT;
-
input rDWBSTB, rDWBWE;
- input [4:0] rRA, rRB, rRD, rRD_;
+ input [4:0] rRA, rRB, rRD;
input [31:0] rRESULT;
input [1:0] rFSM;
input [31:0] rPC;
input [5:0] rOPC;
input [3:0] rDWBSEL;
- //, rPCNXT;
input rLNK, rRWE;
input nclk, nrst, drun, nrun;
- // Register File
- reg [31:0] r00,r01,r02,r03,r04,r05,r06,r07;
- reg [31:0] r08,r09,r0A,r0B,r0C,r0D,r0E,r0F;
- reg [31:0] r10,r11,r12,r13,r14,r15,r16,r17;
- reg [31:0] r18,r19,r1A,r1B,r1C,r1D,r1E,r1F;
+ // ASYNCHRONOUS ////////////////////////////////////////////////////////////////////
- // FLAGS
- wire fWE = rRWE & ~rDWBWE;
+ wire [31:0] wRESULT;
+ wire fWE = rRWE & !rDWBWE;
wire fLNK = rLNK;
wire fLD = rDWBSTB ^ rDWBWE;
+ wire fDFWD = !(rRD ^ rRD_) & fWE;
+ wire fMFWD = rDWBSTB & !rDWBWE;
- // PC Latch
- reg [31:0] rPC_;
- always @(negedge nclk or negedge nrst)
- if (!nrst) begin
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- rPC_ <= 32'h0;
- // End of automatics
- end else if (nrun) begin
- rPC_ <= #1 rPC;
+ /**
+ Delay Latches
+ ----------
+ The PC and RD are latched internally as it will be needed for
+ linking and interrupt handling.
+
+ FIXME: May need to be blocked (drun).
+ */
+
+ reg [31:2] rPC_, xPC_;
+ reg [4:0] rRD_, xRD_;
+
+ always @(/*AUTOSENSE*/rPC or rRD) begin
+ xPC_ <= rPC[31:2];
+ xRD_ <= rRD;
end
- // DWB data - Endian Correction
+ /**
+ Data WISHBONE Bus
+ -----------------
+ The data word that is read or written between the core and the
+ external bus may need to be re-ordered.
+
+ FIXME: Endian correction!
+ */
+
wire [31:0] wDWBDAT;
reg [31:0] sDWBDAT;
reg [31:0] rDWBDAT;
assign dwb_dat_o = {rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
assign wDWBDAT = {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
- always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
- case (rDWBSEL)
- default: sDWBDAT <= wDWBDAT;
- 4'hC: sDWBDAT <= {16'd0,wDWBDAT[31:16]};
- 4'h3: sDWBDAT <= {16'd0,wDWBDAT[15:0]};
- 4'h8: sDWBDAT <= {24'd0,wDWBDAT[31:24]};
- 4'h4: sDWBDAT <= {24'd0,wDWBDAT[23:16]};
- 4'h2: sDWBDAT <= {24'd0,wDWBDAT[15:8]};
- 4'h1: sDWBDAT <= {24'd0,wDWBDAT[7:0]};
- //default: sDWBDAT <= 32'h0;
- endcase // case (rDWBSEL)
-
- // Forwarding Control
- wire fDFWD = (rRD == rRD_) & fWE;
- wire fMFWD = rDWBSTB & ~rDWBWE;
- wire [31:0] wRESULT = (fMFWD) ? sDWBDAT : rRESULT;
+ /**
+ RAM Based Register File
+ -----------------------
+ This approach was chosen for implementing the register file as it
+ was easier to implement and resulted in a higher speed than a pure
+ register based implementation. A comparison was made using
+ synthesis data obtained from Xilinx ISE:
+ Reg : 1284 slices @ 78 MHz
+ RAM : 227 slices @ 141 MHz
+ */
- // Alternative Design
reg [31:0] rMEMA[0:31], rMEMB[0:31], rMEMD[0:31];
wire [31:0] wDDAT, wREGA, wREGB, wREGD, wWBDAT;
wire wDWE = (fLD | fLNK | fWE) & |rRD_ & nrun;
assign wDDAT = (fLD) ? sDWBDAT :
- (fLNK) ? rPC_ : rRESULT;
+ (fLNK) ? {rPC_,2'd0} :
+ rRESULT;
assign wWBDAT = (fDFWD) ? wRESULT : wREGD;
+ assign wRESULT = (fMFWD) ? sDWBDAT : rRESULT;
- assign wREGA = rMEMA[rRA];
- assign wREGB = rMEMB[rRB];
+ assign rREGA = rMEMA[rRA];
+ assign rREGB = rMEMB[rRB];
assign wREGD = rMEMD[rRD];
always @(negedge nclk)
- if (wDWE) begin
+ if (wDWE | !nrst) begin
rMEMA[rRD_] <= wDDAT;
rMEMB[rRD_] <= wDDAT;
rMEMD[rRD_] <= wDDAT;
end
- // Resize
+ /**
+ Memory Resizer
+ --------------
+ This moves the appropriate bytes around depending on the size of
+ the operation. There is no checking for invalid size selection.
+ */
+
reg [31:0] sWBDAT;
always @(/*AUTOSENSE*/rOPC or wWBDAT)
case (rOPC[1:0])
+ // 8-bit
2'o0: sWBDAT <= {(4){wWBDAT[7:0]}};
+ // 16-bit
2'o1: sWBDAT <= {(2){wWBDAT[15:0]}};
+ // 32-bit
default: sWBDAT <= wWBDAT;
endcase // case (rOPC[1:0])
- // PIPELINE REGISTERS //////////////////////////////////////////////////
+ always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
+ case (rDWBSEL)
+ // 8-bit
+ 4'h8: sDWBDAT <= {24'd0,wDWBDAT[31:24]};
+ 4'h4: sDWBDAT <= {24'd0,wDWBDAT[23:16]};
+ 4'h2: sDWBDAT <= {24'd0,wDWBDAT[15:8]};
+ 4'h1: sDWBDAT <= {24'd0,wDWBDAT[7:0]};
+ // 16-bit
+ 4'hC: sDWBDAT <= {16'd0,wDWBDAT[31:16]};
+ 4'h3: sDWBDAT <= {16'd0,wDWBDAT[15:0]};
+ // 32-bit
+ default: sDWBDAT <= wDWBDAT;
+ endcase // case (rDWBSEL)
- reg [31:0] rREGA, rREGB;
- always @(/*AUTOSENSE*/wREGA or wREGB)
- begin
- rREGA <= #1 wREGA;
- rREGB <= #1 wREGB;
- end
+ // PIPELINE REGISTERS //////////////////////////////////////////////////
always @(negedge nclk or negedge nrst)
if (!nrst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBDAT <= 32'h0;
+ rPC_ <= 30'h0;
+ rRD_ <= 5'h0;
// End of automatics
end else if (nrun) begin
rDWBDAT <= #1 sWBDAT;
+ rPC_ <= xPC_;
+ rRD_ <= xRD_;
end
// SIMULATION ONLY ///////////////////////////////////////////////////
+ /**
+ The register file is initialised with random values to reflect a
+ realistic situation where the values are undefined at power-up.
+ */
integer i;
initial begin
for (i=0;i<31;i=i+1) begin
- rMEMA[i] <= 0;
- rMEMB[i] <= 0;
- rMEMD[i] <= 0;
+ rMEMA[i] <= $random;
+ rMEMB[i] <= $random;
+ rMEMD[i] <= $random;
end
end
endmodule // aeMB_regfile
-
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-files:("")
|
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