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Message
From: cvs at opencores.org<cvs@o...>
Date: Thu Apr 26 16:29:54 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/04 26:16:29 Modified: aemb/rtl/verilog aeMB_aslu.v aeMB_regfile.v
Log:
Made minor performance optimisations.
Revision Changes Path
1.6 aemb/rtl/verilog/aeMB_aslu.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_aslu.v.diff?r1=1.5&r2=1.6
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB_aslu.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_aslu.v,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -b -r1.5 -r1.6
--- aeMB_aslu.v 25 Apr 2007 22:15:04 -0000 1.5
+++ aeMB_aslu.v 26 Apr 2007 14:29:53 -0000 1.6
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_aslu.v,v 1.5 2007/04/25 22:15:04 sybreon Exp $
+ * $Id: aeMB_aslu.v,v 1.6 2007/04/26 14:29:53 sybreon Exp $
*
* AEMB Arithmetic Shift Logic Unit
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -23,6 +23,9 @@
*
* HISTORY
* $Log: aeMB_aslu.v,v $
+ * Revision 1.6 2007/04/26 14:29:53 sybreon
+ * Made minor performance optimisations.
+ *
* Revision 1.5 2007/04/25 22:15:04 sybreon
* Added support for 8-bit and 16-bit data types.
*
@@ -41,7 +44,7 @@
*
*/
-// 268 at 91
+// 246 at 101
module aeMB_aslu (/*AUTOARG*/
// Outputs
dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL,
@@ -82,7 +85,7 @@
wire [31:0] wDWBADR;
assign dwb_adr_o = {rDWBADR[DSIZ-1:2],2'b00};
- assign wDWBADR = (wOPA + wOPB);
+ //assign wDWBADR = (wOPA + wOPB);
reg [3:0] rDWBSEL, xDWBSEL;
@@ -128,25 +131,38 @@
// ARITHMETIC
//wire wADDC_ = (rOPC[1] & (rMXLDST == 2'o0)) ? rMSR_C : 1'b0;
- wire wADDC_ = (rOPC[1]) ? rMSR_C : 1'b0;
- wire wSUBC_ = (rOPC[1]) ? rMSR_C : 1'b1;
- wire wADDC, wSUBC, wRES_AC,wCMPC;
- wire [31:0] wADD,wSUB,wRES_A,wCMP;
+ wire wADDC_ = (rOPC[1] & rMSR_C) & ~|rMXLDST;
+ wire wSUBC_ = (rOPC[1] & rMSR_C | ~rOPC[1]);
+ wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
+ wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;
// TODO: verify signed compare
- wire wCMPU = (wOPA > wOPB);
+
+ wire wCMP0 = (wOPA[7:0] > wOPB[7:0]);
+ wire wCMP1 = (wOPA[15:8] > wOPB[15:8]);
+ wire wCMP2 = (wOPA[23:16] > wOPB[23:16]);
+ wire wCMP3 = (wOPA[31:24] > wOPB[31:24]);
+ wire wCMPU = wCMP3 | (wCMP2 & ~wCMP3) | (wCMP1 & ~wCMP2 & ~wCMP3) | (wCMP0 & ~wCMP2 & ~wCMP3 & ~wCMP1);
+
+ //wire wCMPU = (wOPA > wOPB);
wire wCMPF = (rIMM[1]) ? wCMPU :
((wCMPU & ~(wOPB[31] ^ wOPA[31])) | (wOPB[31] & ~wOPA[31]));
assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
- assign {wADDC,wADD} = (wOPB + wOPA) + wADDC_;
- assign {wSUBC,wSUB} = (wOPB + ~wOPA) + wSUBC_;
+ //assign {wADDC,wADD} = (wOPB + wOPA) + wADDC_;
+ //assign {wSUBC,wSUB} = (wOPB + ~wOPA) + wSUBC_;
+ assign wOPX = (rOPC[0] & !rOPC[5]) ? ~wOPA : wOPA ;
+ assign wOPC = (rOPC[0] & !rOPC[5]) ? wSUBC_ : wADDC_ ;
+ assign {wSUBC,wSUB} = {wADDC,wADD};
+ assign {wADDC,wADD} = (wOPB + wOPX) + wOPC;
+ assign wDWBADR = wADD;
+
reg rRES_AC;
reg [31:0] rRES_A;
always @(/*AUTOSENSE*/rIMM or rOPC or wADD or wADDC or wCMP
or wCMPC or wSUB or wSUBC)
//{rRES_AC,rRES_A} <= #1 (rOPC[0] & ~rOPC[5]) ? {~wSUBC,wSUB} : {wADDC,wADD};
- case ({rOPC[5],rOPC[3],rOPC[0],rIMM[0]})
+ case ({rOPC[3],rOPC[0],rIMM[0]})
4'h2, 4'h6, 4'h7: {rRES_AC,rRES_A} <= #1 {~wSUBC,wSUB}; // SUB
4'h3: {rRES_AC,rRES_A} <= #1 {~wCMPC,wCMP}; // CMP
default: {rRES_AC,rRES_A} <= #1 {wADDC,wADD};
1.11 aemb/rtl/verilog/aeMB_regfile.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_regfile.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB_regfile.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_regfile.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- aeMB_regfile.v 25 Apr 2007 22:52:53 -0000 1.10
+++ aeMB_regfile.v 26 Apr 2007 14:29:53 -0000 1.11
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.10 2007/04/25 22:52:53 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.11 2007/04/26 14:29:53 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.11 2007/04/26 14:29:53 sybreon
+ * Made minor performance optimisations.
+ *
* Revision 1.10 2007/04/25 22:52:53 sybreon
* Fixed minor simulation bug.
*
@@ -122,14 +125,14 @@
always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
case (rDWBSEL)
- 4'hF: sDWBDAT <= wDWBDAT;
+ default: sDWBDAT <= wDWBDAT;
4'hC: sDWBDAT <= {16'd0,wDWBDAT[31:16]};
4'h3: sDWBDAT <= {16'd0,wDWBDAT[15:0]};
4'h8: sDWBDAT <= {24'd0,wDWBDAT[31:24]};
4'h4: sDWBDAT <= {24'd0,wDWBDAT[23:16]};
4'h2: sDWBDAT <= {24'd0,wDWBDAT[15:8]};
4'h1: sDWBDAT <= {24'd0,wDWBDAT[7:0]};
- default: sDWBDAT <= 32'h0;
+ //default: sDWBDAT <= 32'h0;
endcase // case (rDWBSEL)
// Forwarding Control
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