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Message
From: cvs at opencores.org<cvs@o...>
Date: Thu Apr 26 00:15:05 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/04 26:00:15 Modified: aemb/sim/verilog testbench.v
Log:
Added support for 8-bit and 16-bit data types.
Revision Changes Path
1.2 aemb/sim/verilog/testbench.v
http://www.opencores.org/cvsweb.shtml/aemb/sim/verilog/testbench.v.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: testbench.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/sim/verilog/testbench.v,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- testbench.v 12 Apr 2007 20:21:34 -0000 1.1
+++ testbench.v 25 Apr 2007 22:15:05 -0000 1.2
@@ -1,5 +1,5 @@
/*
- * $Id: testbench.v,v 1.1 2007/04/12 20:21:34 sybreon Exp $
+ * $Id: testbench.v,v 1.2 2007/04/25 22:15:05 sybreon Exp $
*
* AEMB Generic Testbench
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -23,30 +23,24 @@
*
* HISTORY
* $Log: testbench.v,v $
+ * Revision 1.2 2007/04/25 22:15:05 sybreon
+ * Added support for 8-bit and 16-bit data types.
+ *
* Revision 1.1 2007/04/12 20:21:34 sybreon
* Moved testbench into /sim/verilog.
* Simulation cleanups.
*
- * Revision 1.4 2007/04/11 04:30:43 sybreon
- * Added pipeline stalling from incomplete bus cycles.
- * Separated sync and async portions of code.
- *
- * Revision 1.3 2007/04/04 14:08:34 sybreon
- * Added initial interrupt/exception support.
- *
- * Revision 1.2 2007/04/04 06:11:59 sybreon
- * Extended testbench code
- *
- * Revision 1.1 2007/03/09 17:52:17 sybreon
- * initial import
- *
*/
module testbench ();
parameter ISIZ = 16;
parameter DSIZ = 16;
+
+ // INITIAL SETUP //////////////////////////////////////////////////////
+
reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
+ always #5 sys_clk_i = ~sys_clk_i;
initial begin
$dumpfile("dump.vcd");
@@ -68,36 +62,46 @@
//#11000 $finish;
join
- always #5 sys_clk_i = ~sys_clk_i;
+ // FAKE MEMORY ////////////////////////////////////////////////////////
- // FAKE ROM
- reg [31:0] rom [0:65535];
- wire [31:0] iwb_dat_i;
- reg iwb_ack_i, dwb_ack_i;
wire [ISIZ-1:0] iwb_adr_o;
wire iwb_stb_o;
wire dwb_stb_o;
+ reg [31:0] rom [0:65535];
+ wire [31:0] iwb_dat_i;
+ reg iwb_ack_i, dwb_ack_i;
- // FAKE RAM
- reg [31:0] ram [0:65535];
+ reg [31:0] ram[0:65535];
wire [31:0] dwb_dat_i;
reg [31:0] dwblat;
wire dwb_we_o;
reg [DSIZ-1:2] dadr,iadr;
+ wire [3:0] dwb_sel_o;
wire [31:0] dwb_dat_o;
wire [DSIZ-1:0] dwb_adr_o;
+ wire [31:0] dwb_dat_t;
assign dwb_dat_i = ram[dadr];
assign iwb_dat_i = ram[iadr];
+ assign dwb_dat_t = ram[dwb_adr_o[DSIZ-1:2]];
+
always @(posedge sys_clk_i) begin
iwb_ack_i <= #1 iwb_stb_o;
- //& $random;
dwb_ack_i <= #1 dwb_stb_o;
- //& $random;
iadr <= #1 iwb_adr_o[ISIZ-1:2];
- ram[dwb_adr_o[DSIZ-1:2]] <= (dwb_we_o & dwb_stb_o) ? dwb_dat_o : ram[dwb_adr_o[DSIZ-1:2]];
- dwblat <= dwb_adr_o;
dadr <= dwb_adr_o[DSIZ-1:2];
+
+ if (dwb_we_o & dwb_stb_o) begin
+ case (dwb_sel_o)
+ 4'h1: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:8],dwb_dat_o[7:0]};
+ 4'h2: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:16],dwb_dat_o[15:8],dwb_dat_t[7:0]};
+ 4'h4: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:24],dwb_dat_o[23:16],dwb_dat_t[15:0]};
+ 4'h8: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:24],dwb_dat_t[23:0]};
+ 4'h3: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:16],dwb_dat_o[15:0]};
+ 4'hC: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:16],dwb_dat_t[15:0]};
+ 4'hF: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:0]};
+ endcase // case (dwb_sel_o)
+ end
end
integer i;
@@ -108,31 +112,46 @@
#1 $readmemh("aeMB.rom",ram);
end
+ // DISPLAY OUTPUTS ///////////////////////////////////////////////////
+
always @(negedge sys_clk_i) begin
+
$write("\nT: ",$stime);
if (iwb_stb_o & iwb_ack_i)
$writeh("\tPC: 0x",iwb_adr_o,"=0x",iwb_dat_i);
if (dwb_stb_o & dwb_we_o & dwb_ack_i)
- $writeh("\tST: 0x",dwb_adr_o,"=0x",dwb_dat_o);
+ $writeh("\tST: 0x",dwb_adr_o,"=0x",dwb_dat_o," S=0x",dwb_sel_o);
if (dwb_stb_o & ~dwb_we_o & dwb_ack_i)
- $writeh("\tLD: 0x",dwb_adr_o,"=0x",dwb_dat_i);
-
+ $writeh("\tLD: 0x",dwb_adr_o,"=0x",dwb_dat_i," S=0x",dwb_sel_o);
if (dut.regfile.wDWE)
$writeh("\tR",dut.regfile.rRD_,"=",dut.regfile.wDDAT,";");
if ((dwb_adr_o == 16'h8888) && (dwb_dat_o == 32'h7a55ed00))
$display("*** SERVICE ***");
-
if (dut.control.rFSM == 2'o1)
$display("*** INTERRUPT ***");
+ if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
+ $display("\tFAIL");
+ $finish;
+ end
+ if (dwb_we_o & (dwb_dat_o == "PASS")) begin
+ $display("\tPASS");
+ end
+ if (iwb_dat_i == 32'h000000b8) begin
+ $display("\n\t*** PASSED ALL TESTS ***");
+ $finish;
+ end
end // always @ (posedge sys_clk_i)
+ // INTERNAL WIRING ////////////////////////////////////////////////////
+
aeMB_core #(ISIZ,DSIZ)
dut (
.sys_int_i(sys_int_i),.sys_exc_i(sys_exc_i),
.dwb_ack_i(dwb_ack_i),.dwb_stb_o(dwb_stb_o),.dwb_adr_o(dwb_adr_o),
.dwb_dat_o(dwb_dat_o),.dwb_dat_i(dwb_dat_i),.dwb_we_o(dwb_we_o),
+ .dwb_sel_o(dwb_sel_o),
.iwb_adr_o(iwb_adr_o),.iwb_dat_i(iwb_dat_i),.iwb_stb_o(iwb_stb_o),
.iwb_ack_i(iwb_ack_i),
.sys_clk_i(sys_clk_i), .sys_rst_i(sys_rst_i)
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