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Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Apr 20 16:46:00 CEST 2007
Subject: [cvs-checkins] MODIFIED: mlite ...
Date: 00/07/04 20:16:45 Modified: mlite/vhdl mlite_pack.vhd
Log:
Defined outputing PC as stage #0
Revision Changes Path
1.16 mlite/vhdl/mlite_pack.vhd
http://www.opencores.org/cvsweb.shtml/mlite/vhdl/mlite_pack.vhd.diff?r1=1.15&r2=1.16
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mlite_pack.vhd
===================================================================
RCS file: /cvsroot/rhoads/mlite/vhdl/mlite_pack.vhd,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -b -r1.15 -r1.16
--- mlite_pack.vhd 14 Feb 2007 18:56:07 -0000 1.15
+++ mlite_pack.vhd 20 Apr 2007 14:45:56 -0000 1.16
@@ -358,7 +358,7 @@
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
- pipeline_stages : natural := 3); --3 or 4
+ pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
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