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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Apr 14 21:26:37 CEST 2007
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/07/04 14:21:26 Modified: jop/vhdl/memory mem_sc.vhd
Log:
Hardware implementation of iaload and iastore
Revision Changes Path
1.8 jop/vhdl/memory/mem_sc.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/memory/mem_sc.vhd.diff?r1=1.7&r2=1.8
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mem_sc.vhd
===================================================================
RCS file: /cvsroot/martin/jop/vhdl/memory/mem_sc.vhd,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- mem_sc.vhd 14 Apr 2007 18:38:11 -0000 1.7
+++ mem_sc.vhd 14 Apr 2007 19:26:37 -0000 1.8
@@ -176,8 +176,7 @@
if sc_mem_in.rdy_cnt=3 then
mem_out.bsy <= '1';
else
- if state/=ialrb and state/=iasw
- and state/=iasst and bcl_arr_bsy='1' then
+ if state/=ialrb and state/=iasw and bcl_arr_bsy='1' then
mem_out.bsy <= '1';
end if;
end if;
@@ -492,9 +491,6 @@
when iasst =>
next_state <= iasw;
- if sc_mem_in.rdy_cnt(1)='0' then
- next_state <= idl;
- end if;
when iasw =>
-- either 1 or 0
@@ -517,21 +513,6 @@
end process;
--
--- state machine combinatorial output
--- from next_state
--- read for single cycle memory could be
--- speed up
---
-process(next_state)
-begin
- arr_wr <= '0';
- if next_state=iasst then
- arr_wr <= '1';
- end if;
-
-end process;
-
---
-- state machine register
-- output register
--
@@ -547,6 +528,7 @@
bcl_arr_bsy <= '0';
null_pointer <= '0';
bounds_error <= '0';
+ arr_wr <= '0';
elsif rising_edge(clk) then
@@ -558,6 +540,7 @@
bc_arr_rd <= '0';
null_pointer <= '0';
bounds_error <= '0';
+ arr_wr <= '0';
case next_state is
@@ -622,6 +605,7 @@
when iasrb =>
when iasst =>
+ arr_wr <= '1';
when iasw =>
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