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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Apr 14 00:18:52 CEST 2007
Subject: [cvs-checkins] MODIFIED: ae18 ...
Date: 00/07/04 14:00:18 Modified: ae18/rtl/verilog ae18_core.v
Removed: ae18/rtl/verilog ae18_aram.v ae18_core_tb.v ae18_sram.v
Log:
Moved testbench into sim/verilog/testbench.v
Minor cleanup.
Revision Changes Path
1.7 ae18/rtl/verilog/ae18_core.v
http://www.opencores.org/cvsweb.shtml/ae18/rtl/verilog/ae18_core.v.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ae18_core.v
===================================================================
RCS file: /cvsroot/sybreon/ae18/rtl/verilog/ae18_core.v,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- ae18_core.v 3 Apr 2007 22:13:25 -0000 1.6
+++ ae18_core.v 13 Apr 2007 22:18:51 -0000 1.7
@@ -1,15 +1,5 @@
-// -*- Mode: Verilog -*-
-// Filename : ae18_core.v
-// Description : PIC18 compatible core.
-// Author : Shawn Tan Ser Ngiap <shawn.tan@a...>
-// Created On : Fri Dec 22 16:09:33 2006
-// Last Modified By: $Author: sybreon $
-// Last Modified On: $Date: 2007/04/03 22:13:25 $
-// Update Count : $Revision: 1.6 $
-// Status : $State: Exp $
-
/*
- * $Id: ae18_core.v,v 1.6 2007/04/03 22:13:25 sybreon Exp $
+ * $Id: ae18_core.v,v 1.7 2007/04/13 22:18:51 sybreon Exp $
*
* AE18 8-bit Microprocessor Core
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -20,13 +10,14 @@
* or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
- * License for more details.
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
*
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+ * USA
*
* DESCRIPTION
* This core provides a PIC18 software compatible core. It does not provide
@@ -37,6 +28,10 @@
*
* HISTORY
* $Log: ae18_core.v,v $
+ * Revision 1.7 2007/04/13 22:18:51 sybreon
+ * Moved testbench into sim/verilog/testbench.v
+ * Minor cleanup.
+ *
* Revision 1.6 2007/04/03 22:13:25 sybreon
* Fixed various bugs:
* - STATUS,C not correct for subtraction instructions
@@ -1209,13 +1204,12 @@
wire [ISIZ-1:0] wSTKR;
wire wSTKE = (qena[1]);
- ae18_aram #(ISIZ,5)
- stack (
- .wdat(wSTKW), .rdat(wSTKR),
- .radr(rSTKPTR[4:0]), .wadr(rSTKPTR_[4:0]),
- .we(wSTKE),
- // Inputs
- .clk (clk));
+ reg [ISIZ-1:0] rSTKRAM [0:31];
+
+ assign wSTKR = rSTKRAM[rSTKPTR[4:0]];
+ always @(posedge clk)
+ if (wSTKE)
+ rSTKRAM[rSTKPTR_[4:0]] <= wSTKW;
/*
* SFR Bank
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