OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Wed Mar 28 14:35:20 CEST 2007
Subject: [cvs-checkins] MODIFIED: jop ...

Date: 00/07/03 28:14:35

Modified: jop/vhdl/scio scio_bg.vhd Log: SimpCon with records Revision Changes Path 1.4 jop/vhdl/scio/scio_bg.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/scio/scio_bg.vhd.diff?r1=1.3&r2=1.4 (In the diff below, changes in quantity of whitespace are not shown.) Index: scio_bg.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/scio/scio_bg.vhd,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- scio_bg.vhd 12 Jan 2006 11:03:30 -0000 1.3 +++ scio_bg.vhd 28 Mar 2007 12:35:19 -0000 1.4 @@ -30,6 +30,7 @@ -- 2005-08-27 ignore ncts on uart -- 2005-12-27 change for SimpCon, HW hand shake is programmable -- for uart_tal +-- 2007-03-28 use records -- @@ -391,32 +392,26 @@ use ieee.numeric_std.all; use work.jop_types.all; +use work.sc_pack.all; use work.jop_config.all; entity scio is -generic (addr_bits : integer); port ( clk : in std_logic; reset : in std_logic; --- SimpCon interface - - address : in std_logic_vector(addr_bits-1 downto 0); - wr_data : in std_logic_vector(31 downto 0); - rd, wr : in std_logic; - rd_data : out std_logic_vector(31 downto 0); - rdy_cnt : out unsigned(1 downto 0); - --- interrupt - - irq : out std_logic; - irq_ena : out std_logic; - --- exception +-- +-- SimpCon IO interface +-- + sc_io_out : in sc_io_out_type; + sc_io_in : out sc_in_type; +-- +-- Interrupts from IO devices +-- + irq_in : out irq_in_type; exc_req : in exception_type; - exc_int : out std_logic; -- serial interface @@ -481,22 +476,19 @@ assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio"; - sel <= to_integer(unsigned(address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS))); + sel <= to_integer(unsigned(sc_io_out.address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS))); -- What happens when sel_reg > SLAVE_CNT-1?? - rd_data <= sc_dout(sel_reg); - - -- rdy_cnt <= sc_rdy_cnt(sel_reg); - -- all IO devices are single cycle - rdy_cnt <= "00"; + sc_io_in.rd_data <= sc_dout(sel_reg); + sc_io_in.rdy_cnt <= sc_rdy_cnt(sel_reg); -- -- Connect SLAVE_CNT slaves -- gsl: for i in 0 to SLAVE_CNT-1 generate - sc_rd(i) <= rd when i=sel else '0'; - sc_wr(i) <= wr when i=sel else '0'; + sc_rd(i) <= sc_io_out.rd when i=sel else '0'; + sc_wr(i) <= sc_io_out.wr when i=sel else '0'; end generate; @@ -508,7 +500,7 @@ if (reset='1') then sel_reg <= 0; elsif rising_edge(clk) then - if rd='1' then + if sc_io_out.rd='1' then sel_reg <= sel; end if; end if; @@ -522,18 +514,15 @@ clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(0), wr => sc_wr(0), rd_data => sc_dout(0), rdy_cnt => sc_rdy_cnt(0), - irq => irq, - irq_ena => irq_ena, - + irq_in => irq_in, exc_req => exc_req, - exc_int => exc_int, wd => wd ); @@ -552,8 +541,8 @@ clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(1), wr => sc_wr(1), rd_data => sc_dout(1), @@ -566,6 +555,8 @@ ); -- slave 2 is reserved for USB and System.out writes to it!!! + sc_rdy_cnt(2) <= (others => '0'); + sc_dout(2) <= (others => '0'); -- Siemens TC35 sends up to 32!!! characters after cts deasert -- WW does not like the 115200 baud :-( @@ -582,8 +573,8 @@ clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(3), wr => sc_wr(3), rd_data => sc_dout(3), @@ -609,8 +600,8 @@ clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(4), wr => sc_wr(4), rd_data => sc_dout(4), @@ -633,8 +624,8 @@ clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(6), wr => sc_wr(6), rd_data => sc_dout(6), @@ -661,8 +652,8 @@ clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(5), wr => sc_wr(5), rd_data => sc_dout(5),