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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Tue Mar 27 17:47:31 CEST 2007
    Subject: [cvs-checkins] MODIFIED: jop ...
    Top
    Date: 00/07/03 27:17:47

    Modified: jop/vhdl/fpu addsub_28.vhd fpu.vhd fpupack.vhd mul_24.vhd
    post_norm_addsub.vhd post_norm_div.vhd
    post_norm_mul.vhd readme.txt serial_div.vhd
    sqrt.vhd
    Added: jop/vhdl/fpu bug_report.txt
    Log:
    updated FPU version


    Revision Changes Path
    1.2 jop/vhdl/fpu/addsub_28.vhd

    http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/addsub_28.vhd.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: addsub_28.vhd
    ===================================================================
    RCS file: /cvsroot/martin/jop/vhdl/fpu/addsub_28.vhd,v
    retrieving revision 1.1
    retrieving revision 1.2
    diff -u -b -r1.1 -r1.2
    --- addsub_28.vhd 30 Jan 2006 13:13:56 -0000 1.1
    +++ addsub_28.vhd 27 Mar 2007 15:47:30 -0000 1.2
    @@ -103,7 +103,7 @@
    s_addop <= ((s_signa_i xor s_signb_i)and not (s_fpu_op_i)) or ((s_signa_i xnor s_signb_i)and (s_fpu_op_i));

    -- sign of result
    -s_sign_o <= '0' when s_fract_o = conv_std_logic_vector(0,28) else
    +s_sign_o <= '0' when s_fract_o = conv_std_logic_vector(0,28) and (s_signa_i and s_signb_i)='0' else
    ((not s_signa_i) and ((not fracta_lt_fractb) and (fpu_op_i xor s_signb_i))) or
    ((s_signa_i) and (fracta_lt_fractb or (fpu_op_i xor s_signb_i)));




    1.2 jop/vhdl/fpu/fpu.vhd

    http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/fpu.vhd.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: fpu.vhd
    ===================================================================
    RCS file: /cvsroot/martin/jop/vhdl/fpu/fpu.vhd,v
    retrieving revision 1.1
    retrieving revision 1.2
    diff -u -b -r1.1 -r1.2
    --- fpu.vhd 30 Jan 2006 13:13:56 -0000 1.1
    +++ fpu.vhd 27 Mar 2007 15:47:30 -0000 1.2
    @@ -103,8 +103,8 @@
    architecture rtl of fpu is


    - constant MUL_SERIAL: integer range 0 to 1 := 1; -- 0 for parallel multiplier, 1 for serial
    - constant MUL_COUNT: integer:= 33; --10 for parallel multiplier, 33 for serial
    + constant MUL_SERIAL: integer range 0 to 1 := 0; -- 0 for parallel multiplier, 1 for serial
    + constant MUL_COUNT: integer:= 11; --11 for parallel multiplier, 34 for serial

    -- Input/output registers
    signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
    @@ -117,6 +117,8 @@
    signal s_state : t_state;
    signal s_start_i : std_logic;
    signal s_count : integer;
    + signal s_output1 : std_logic_vector(FP_WIDTH-1 downto 0);
    + signal s_infa, s_infb : std_logic;

    -- ***Add/Substract units signals***

    @@ -227,7 +229,7 @@
    fractb_i => pre_norm_mul_fractb_24,
    signa_i => s_opa_i(31),
    signb_i => s_opb_i(31),
    - start_i => s_start_i,
    + start_i => start_i,
    fract_o => mul_24_fract_48,
    sign_o => mul_24_sign,
    ready_o => open);
    @@ -256,7 +258,7 @@
    exp_10_i => pre_norm_mul_exp_10,
    fract_48_i => mul_fract_48,
    sign_i => mul_24_sign,
    - rmode_i => rmode_i,
    + rmode_i => s_rmode_i,
    output_o => post_norm_mul_output,
    ine_o => post_norm_mul_ine
    );
    @@ -370,7 +372,7 @@
    if s_start_i ='1' then
    s_state <= busy;
    s_count <= 0;
    - elsif s_count=5 and ((fpu_op_i="000") or (fpu_op_i="001")) then
    + elsif s_count=6 and ((fpu_op_i="000") or (fpu_op_i="001")) then
    s_state <= waiting;
    ready_o <= '1';
    s_count <=0;
    @@ -378,7 +380,7 @@
    s_state <= waiting;
    ready_o <= '1';
    s_count <=0; - elsif s_count=32 and fpu_op_i="011" then + elsif s_count=33 and fpu_op_i="011" then s_state <= waiting; ready_o <= '1'; s_count <=0; @@ -400,31 +402,63 @@ begin if rising_edge(clk_i) then if fpu_op_i="000" or fpu_op_i="001" then - s_output_o <= postnorm_addsub_output_o; + s_output1 <= postnorm_addsub_output_o; s_ine_o <= postnorm_addsub_ine_o; elsif fpu_op_i="010" then - s_output_o <= post_norm_mul_output; + s_output1 <= post_norm_mul_output; s_ine_o <= post_norm_mul_ine; elsif fpu_op_i="011" then - s_output_o <= post_norm_div_output; + s_output1 <= post_norm_div_output; s_ine_o <= post_norm_div_ine; --- elsif fpu_op_i="100" then --- s_output_o <= post_norm_sqrt_output; --- s_ine_o <= post_norm_sqrt_ine_o; + elsif fpu_op_i="100" then + s_output1 <= post_norm_sqrt_output; + s_ine_o <= post_norm_sqrt_ine_o; else - s_output_o <= (others => '0'); + s_output1 <= (others => '0'); s_ine_o <= '0'; end if; end if; end process; + + s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0'; + s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0'; + + + --In round down: the subtraction of two equal numbers other than zero are always -0!!! + process(s_output1, s_rmode_i, s_div_zero_o, s_infa, s_infb, s_qnan_o, s_snan_o, s_zero_o, s_fpu_op_i, s_opa_i, s_opb_i ) + begin + if s_rmode_i="00" or (s_div_zero_o or (s_infa or s_infb) or s_qnan_o or s_snan_o)='1' then --round-to-nearest-even + s_output_o <= s_output1; + elsif s_rmode_i="01" and s_output1(30 downto 23)="11111111" then + --In round-to-zero: the sum of two non-infinity operands is never infinity,even if an overflow occures + s_output_o <= s_output1(31) & "1111111011111111111111111111111"; + elsif s_rmode_i="10" and s_output1(31 downto 23)="111111111" then + --In round-up: the sum of two non-infinity operands is never negative infinity,even if an overflow occures + s_output_o <= "11111111011111111111111111111111"; + elsif s_rmode_i="11" then + --In round-down: a-a= -0 + if (s_fpu_op_i="000" or s_fpu_op_i="001") and s_zero_o='1' and (s_opa_i(31) or (s_fpu_op_i(0) xor s_opb_i(31)))='1' then + s_output_o <= "1" & s_output1(30 downto 0); + --In round-down: the sum of two non-infinity operands is never postive infinity,even if an overflow occures + elsif s_output1(31 downto 23)="011111111" then + s_output_o <= "01111111011111111111111111111111"; + else + s_output_o <= s_output1; + end if; + else + s_output_o <= s_output1; + end if; + end process; + + -- Generate Exceptions - s_underflow_o <= '1' when s_output_o(30 downto 23)="00000000" and s_ine_o='1' else '0'; - s_overflow_o <= '1' when s_output_o(30 downto 23)="11111111" and s_ine_o='1' else '0'; + s_underflow_o <= '1' when s_output1(30 downto 23)="00000000" and s_ine_o='1' else '0'; + s_overflow_o <= '1' when s_output1(30 downto 23)="11111111" and s_ine_o='1' else '0'; s_div_zero_o <= serial_div_div_zero when fpu_op_i="011" else '0'; - s_inf_o <= '1' when s_output_o(30 downto 23)="11111111" and (s_qnan_o or s_snan_o)='0' else '0'; - s_zero_o <= '1' when or_reduce(s_output_o(30 downto 0))='0' else '0'; - s_qnan_o <= '1' when s_output_o(30 downto 0)=QNAN else '0'; + s_inf_o <= '1' when s_output1(30 downto 23)="11111111" and (s_qnan_o or s_snan_o)='0' else '0'; + s_zero_o <= '1' when or_reduce(s_output1(30 downto 0))='0' else '0'; + s_qnan_o <= '1' when s_output1(30 downto 0)=QNAN else '0'; s_snan_o <= '1' when s_opa_i(30 downto 0)=SNAN or s_opb_i(30 downto 0)=SNAN else '0'; 1.2 jop/vhdl/fpu/fpupack.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/fpupack.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: fpupack.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/fpu/fpupack.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- fpupack.vhd 30 Jan 2006 13:13:56 -0000 1.1 +++ fpupack.vhd 27 Mar 2007 15:47:30 -0000 1.2 @@ -58,12 +58,14 @@ -- Data width of exponent. Deafult: 8 constant EXP_WIDTH : integer := 8; + --Zero vector + constant ZERO_VECTOR: std_logic_vector(30 downto 0) := "0000000000000000000000000000000"; -- Infinty FP format constant INF : std_logic_vector(30 downto 0) := "1111111100000000000000000000000"; -- QNaN (Quit Not a Number) FP format (without sign bit) - constant QNAN : std_logic_vector(30 downto 0) := "1111111110000000000000000000001"; + constant QNAN : std_logic_vector(30 downto 0) := "1111111110000000000000000000000"; -- SNaN (Signaling Not a Number) FP format (without sign bit) constant SNAN : std_logic_vector(30 downto 0) := "1111111100000000000000000000001"; 1.2 jop/vhdl/fpu/mul_24.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/mul_24.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: mul_24.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/fpu/mul_24.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- mul_24.vhd 30 Jan 2006 13:13:56 -0000 1.1 +++ mul_24.vhd 27 Mar 2007 15:47:30 -0000 1.2 @@ -144,8 +144,8 @@ s_sign_o <= s_signa_i xor s_signb_i; --"000000000000" --- A = A_h × 2^N + A_l , B = B_h ×2^N + B_l --- A x B = A_h×B_h×2^2N + (A_h ×B_l + A_l×B_h)2^N + A_l×B_l +-- A = A_h x 2^N + A_l , B = B_h x 2^N + B_l +-- A x B = A_hxB_hx2^2N + (A_h xB_l + A_lxB_h)2^N + A_lxB_l a_h <= s_fracta_i(23 downto 12); a_l <= s_fracta_i(11 downto 0); b_h <= s_fractb_i(23 downto 12); 1.2 jop/vhdl/fpu/post_norm_addsub.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/post_norm_addsub.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: post_norm_addsub.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/fpu/post_norm_addsub.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- post_norm_addsub.vhd 30 Jan 2006 13:13:56 -0000 1.1 +++ post_norm_addsub.vhd 27 Mar 2007 15:47:30 -0000 1.2 @@ -79,26 +79,22 @@ signal s_ine_o : std_logic; signal s_overflow : std_logic; +signal s_zeros, s_shr1, s_shl1 : std_logic_vector(5 downto 0); +signal s_shr2, s_carry : std_logic; -signal s_shr1, s_shr2, s_shl : std_logic; +signal s_exp10: std_logic_vector(9 downto 0); +signal s_expo9_1, s_expo9_2, s_expo9_3: std_logic_vector(EXP_WIDTH downto 0); -signal s_expr1_9, s_expr2_9, s_expl_9 : std_logic_vector(EXP_WIDTH downto 0); -signal s_exp_shr1, s_exp_shr2, s_exp_shl : std_logic_vector(EXP_WIDTH-1 downto 0); +signal s_fracto28_1, s_fracto28_2, s_fracto28_rnd : std_logic_vector(FRAC_WIDTH+4 downto 0); -signal s_fract_shr1, s_fract_shr2, s_fract_shl : std_logic_vector(FRAC_WIDTH+4 downto 0); -signal s_zeros : std_logic_vector(5 downto 0); -signal shl_pos: std_logic_vector(5 downto 0); - -signal s_fract_1, s_fract_2 : std_logic_vector(FRAC_WIDTH+4 downto 0); -signal s_exp_1, s_exp_2 : std_logic_vector(EXP_WIDTH-1 downto 0); - -signal s_fract_rnd : std_logic_vector(FRAC_WIDTH+4 downto 0); signal s_roundup : std_logic; +signal s_sticky : std_logic; +signal s_zero_fract : std_logic; +signal s_lost : std_logic; signal s_infa, s_infb : std_logic; signal s_nan_in, s_nan_op, s_nan_a, s_nan_b, s_nan_sign : std_logic; - begin -- Input Register @@ -116,83 +112,82 @@ --end process; -- Output Register - --process(clk_i) - --begin - -- if rising_edge(clk_i) then + process(clk_i) + begin + if rising_edge(clk_i) then output_o <= s_output_o; ine_o <= s_ine_o; - -- end if; - --end process; + end if; + end process; + --*** Stage 1 **** + -- figure out the output exponent and howmuch the fraction has to be shiftd right/left - -- check if shifting is needed - s_shr1 <= s_fract_28_i(27); - s_shl <= '1' when s_fract_28_i(27 downto 26)="00" and s_exp_i /= "00000000" else '0'; - - -- stage 1a: right-shift (when necessary) - s_expr1_9 <= "0"&s_exp_i + "000000001"; - s_fract_shr1 <= shr(s_fract_28_i, "1"); - s_exp_shr1 <= s_expr1_9(7 downto 0); + s_carry <= s_fract_28_i(27); - -- stage 1b: left-shift (when necessary) - process(clk_i) - begin - if rising_edge(clk_i) then - -- count the leading zero's of fraction, needed for left-shift - s_zeros <= count_l_zeros(s_fract_28_i(26 downto 1)); - end if; - end process; + s_zeros <= count_l_zeros(s_fract_28_i(26 downto 0)) when s_fract_28_i(27)='0' else "000000"; - s_expl_9 <= ("0"&s_exp_i) - ("000"&s_zeros); - shl_pos <= "000000" when s_exp_i="00000001" else s_zeros; - s_fract_shl <= shl(s_fract_28_i, shl_pos); - s_exp_shl <= "00000000" when s_exp_i="00000001" else s_exp_i - ("00"&shl_pos); + s_exp10 <= ("00"&s_exp_i) + ("000000000"&s_carry) - ("0000"&s_zeros); -- negative flag & large flag & exp process(clk_i) begin if rising_edge(clk_i) then - if s_shr1='1' then - s_fract_1 <= s_fract_shr1; - elsif s_shl='1' then - s_fract_1 <= s_fract_shl; + if s_exp10(9)='1' or s_exp10="0000000000" then + s_shr1 <= (others =>'0'); + if or_reduce(s_exp_i)/='0' then + s_shl1 <= s_exp_i(5 downto 0) - "000001"; + else + s_shl1 <= "000000"; + end if; + s_expo9_1 <= "000000001"; + elsif s_exp10(8)='1' then + s_shr1 <= (others =>'0'); + s_shl1 <= (others =>'0'); + s_expo9_1 <= "011111111"; else - s_fract_1 <= s_fract_28_i; + s_shr1 <= ("00000"&s_carry); + s_shl1 <= s_zeros; + s_expo9_1 <= s_exp10(8 downto 0); end if; end if; end process; +--- + -- *** Stage 2 *** + -- Shifting the fraction and rounding + process(clk_i) begin if rising_edge(clk_i) then - if s_shr1='1' then - s_exp_1 <= s_exp_shr1; - elsif s_shl='1' then - s_exp_1 <= s_exp_shl; + if s_shr1 /= "000000" then + s_fracto28_1 <= shr(s_fract_28_i, s_shr1); else - s_exp_1 <= s_exp_i; + s_fracto28_1 <= shl(s_fract_28_i, s_shl1); end if; end if; end process; + s_expo9_2 <= s_expo9_1 - "000000001" when s_fracto28_1(27 downto 26)="00" else s_expo9_1; + -- round - s_roundup <= s_fract_1(2) and ((s_fract_1(1) or s_fract_1(0))or s_fract_1(3)) when s_rmode_i="00" else -- round to nearset even - (s_fract_1(2) or s_fract_1(1) or s_fract_1(0)) and (not s_sign_i) when s_rmode_i="10" else -- round up - (s_fract_1(2) or s_fract_1(1) or s_fract_1(0)) and (s_sign_i) when s_rmode_i="11" else -- round down + s_sticky <='1' when s_fracto28_1(0)='1' or (s_fract_28_i(0) and s_fract_28_i(27))='1' else '0'; --check last bit, before and after right-shift + + s_roundup <= s_fracto28_1(2) and ((s_fracto28_1(1) or s_sticky)or s_fracto28_1(3)) when s_rmode_i="00" else -- round to nearset even + (s_fracto28_1(2) or s_fracto28_1(1) or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up + (s_fracto28_1(2) or s_fracto28_1(1) or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down '0'; -- round to zero(truncate = no rounding) - s_fract_rnd <= s_fract_1 + "0000000000000000000000001000" when s_roundup='1' else s_fract_1; + s_fracto28_rnd <= s_fracto28_1 + "0000000000000000000000001000" when s_roundup='1' else s_fracto28_1; - -- stage 2: right-shift after rounding (when necessary) - s_shr2 <= s_fract_rnd(27); - s_expr2_9 <= ("0"&s_exp_1) + "000000001"; - s_fract_shr2 <= shr(s_fract_rnd, "1"); - s_exp_shr2 <= s_expr2_9(7 downto 0); - - s_fract_2 <= s_fract_shr2 when s_shr2='1' else s_fract_rnd; - s_exp_2 <= s_exp_shr2 when s_shr2='1' else s_exp_1; - ------------- + -- ***Stage 3*** + -- right-shift after rounding (if necessary) + s_shr2 <= s_fracto28_rnd(27); + + s_expo9_3 <= s_expo9_2 + "000000001" when s_shr2='1' and s_expo9_2 /= "011111111" else s_expo9_2; + s_fracto28_2 <= ("0"&s_fracto28_rnd(27 downto 1)) when s_shr2='1' else s_fracto28_rnd; +----- s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0'; s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0'; @@ -207,22 +202,24 @@ s_opb_i(31); -- check if result is inexact; - s_ine_o <= (or_reduce(s_fract_28_i(2 downto 0)) or or_reduce(s_fract_1(2 downto 0)) or or_reduce(s_fract_2(2 downto 0))) and not(s_nan_a or s_nan_b); + s_lost <= (s_shr1(0) and s_fract_28_i(0)) or (s_shr2 and s_fracto28_rnd(0)) or or_reduce(s_fracto28_2(2 downto 0)); + s_ine_o <= '1' when (s_lost or s_overflow)='1' and (s_infa or s_infb)='0' else '0'; - s_overflow <= (s_expr1_9(8) or s_expr2_9(8)) and not(s_nan_a or s_nan_b); -- if true, output is infinity + s_overflow <='1' when s_expo9_3="011111111" and (s_infa or s_infb)='0' else '0'; + s_zero_fract <= '1' when s_zeros=27 and s_fract_28_i(27)='0' else '0'; -- '1' if fraction result is zero - process(s_sign_i, s_exp_2, s_fract_2, s_nan_in, s_nan_op, s_nan_sign, s_infa, s_infb, s_overflow) + process(s_sign_i, s_expo9_3, s_fracto28_2, s_nan_in, s_nan_op, s_nan_sign, s_infa, s_infb, s_overflow, s_zero_fract) begin if (s_nan_in or s_nan_op)='1' then s_output_o <= s_nan_sign & QNAN; elsif (s_infa or s_infb)='1' or s_overflow='1' then s_output_o <= s_sign_i & INF; + elsif s_zero_fract='1' then + s_output_o <= s_sign_i & ZERO_VECTOR; else - s_output_o <= s_sign_i & s_exp_2 & s_fract_2(25 downto 3); + s_output_o <= s_sign_i & s_expo9_3(7 downto 0) & s_fracto28_2(25 downto 3); end if; end process; - - end rtl; 1.2 jop/vhdl/fpu/post_norm_div.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/post_norm_div.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: post_norm_div.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/fpu/post_norm_div.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- post_norm_div.vhd 30 Jan 2006 13:13:56 -0000 1.1 +++ post_norm_div.vhd 27 Mar 2007 15:47:30 -0000 1.2 @@ -83,6 +83,7 @@ signal s_opa_dn, s_opb_dn : std_logic; signal s_qutdn : std_logic; +signal s_exp_10b : std_logic_vector(9 downto 0); signal s_shr1, s_shl1 : std_logic_vector(5 downto 0); signal s_shr2 : std_logic; signal s_expo1, s_expo2, s_expo3 : std_logic_vector(8 downto 0); @@ -91,10 +92,10 @@ signal s_guard, s_round, s_sticky, s_roundup : std_logic; signal s_lost : std_logic; -signal s_op_0, s_opab_0 : std_logic; +signal s_op_0, s_opab_0, s_opb_0 : std_logic; signal s_infa, s_infb : std_logic; signal s_nan_in, s_nan_op, s_nan_a, s_nan_b : std_logic; -signal s_exp_10b : std_logic_vector(9 downto 0); +signal s_inf_result: std_logic; begin @@ -152,7 +153,7 @@ elsif s_exp_10b(8)='1' then v_shr := (others =>'0'); v_shl := (others =>'0'); - s_expo1 <= "011111111"; + s_expo1 <= s_exp_10b(8 downto 0); else v_shr := (others =>'0'); v_shl := "000000000"& s_qutdn; @@ -211,7 +212,7 @@ process(clk_i) begin if rising_edge(clk_i) then - if s_shr2='1' and s_expo2 /= "011111111" then + if s_shr2='1' then s_expo3 <= s_expo2 + "1"; s_fraco2 <= "0"&s_frac_rnd(24 downto 1); else @@ -229,6 +230,7 @@ s_op_0 <= not ( or_reduce(s_opa_i(30 downto 0)) and or_reduce(s_opb_i(30 downto 0)) ); s_opab_0 <= not ( or_reduce(s_opa_i(30 downto 0)) or or_reduce(s_opb_i(30 downto 0)) ); + s_opb_0 <= not or_reduce(s_opb_i(30 downto 0)); s_infa <= '1' when s_expa="11111111" else '0'; s_infb <= '1' when s_expb="11111111" else '0'; @@ -238,17 +240,20 @@ s_nan_in <= '1' when s_nan_a='1' or s_nan_b='1' else '0'; s_nan_op <= '1' when (s_infa and s_infb)='1' or s_opab_0='1' else '0';-- 0 / 0, inf / inf + s_inf_result <= '1' when (and_reduce(s_expo3(7 downto 0)) or s_expo3(8))='1' or s_opb_0='1' else '0'; - s_overflow <= '1' when s_expo3 = "011111111" and (s_infa or s_infb)='0' and or_reduce(s_opb_i(30 downto 0))='1' else '0'; + s_overflow <= '1' when s_inf_result='1' and (s_infa or s_infb)='0' and s_opb_0='0' else '0'; s_ine_o <= '1' when s_op_0='0' and (s_lost or or_reduce(s_fraco1(2 downto 0)) or s_overflow or or_reduce(s_rmndr_i))='1' else '0'; - process(s_sign_i, s_expo3, s_fraco2, s_nan_in, s_nan_op, s_infa, s_infb, s_overflow) + process(s_sign_i, s_expo3, s_fraco2, s_nan_in, s_nan_op, s_infa, s_infb, s_overflow, s_inf_result, s_op_0) begin if (s_nan_in or s_nan_op)='1' then - s_output_o <= s_sign_i & QNAN; - elsif (s_infa or s_infb)='1' or s_overflow='1' then + s_output_o <= '1' & QNAN; + elsif (s_infa or s_infb)='1' or s_overflow='1' or s_inf_result='1' then s_output_o <= s_sign_i & INF; + elsif s_op_0='1' then + s_output_o <= s_sign_i & ZERO_VECTOR; else s_output_o <= s_sign_i & s_expo3(7 downto 0) & s_fraco2(22 downto 0); end if; 1.2 jop/vhdl/fpu/post_norm_mul.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/post_norm_mul.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: post_norm_mul.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/fpu/post_norm_mul.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- post_norm_mul.vhd 30 Jan 2006 13:13:56 -0000 1.1 +++ post_norm_mul.vhd 27 Mar 2007 15:47:30 -0000 1.2 @@ -93,7 +93,6 @@ signal s_infa, s_infb : std_logic; signal s_nan_in, s_nan_op, s_nan_a, s_nan_b : std_logic; -signal s_opa_dn, s_opb_dn : std_logic; begin @@ -146,7 +145,7 @@ begin if rising_edge(clk_i) then if s_exp_10a(9)='1' or s_exp_10a="0000000000" then - v_shr1 := "0000000001" - s_exp_10a; + v_shr1 := "0000000001" - s_exp_10a + ("000000000"&s_carry); v_shl1 := (others =>'0'); s_expo1 <= "000000001"; else @@ -253,12 +252,14 @@ s_ine_o <= '1' when s_op_0='0' and (s_lost or or_reduce(s_frac2a(22 downto 0)) or s_overflow)='1' else '0'; - process(s_sign_i, s_expo3, s_frac3, s_nan_in, s_nan_op, s_infa, s_infb, s_overflow) + process(s_sign_i, s_expo3, s_frac3, s_nan_in, s_nan_op, s_infa, s_infb, s_overflow, s_r_zeros) begin if (s_nan_in or s_nan_op)='1' then s_output_o <= s_sign_i & QNAN; elsif (s_infa or s_infb)='1' or s_overflow='1' then s_output_o <= s_sign_i & INF; + elsif s_r_zeros=48 then + s_output_o <= s_sign_i & ZERO_VECTOR; else s_output_o <= s_sign_i & s_expo3(7 downto 0) & s_frac3(22 downto 0); 1.2 jop/vhdl/fpu/readme.txt http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/readme.txt.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: readme.txt =================================================================== RCS file: /cvsroot/martin/jop/vhdl/fpu/readme.txt,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- readme.txt 30 Jan 2006 13:13:56 -0000 1.1 +++ readme.txt 27 Mar 2007 15:47:30 -0000 1.2 @@ -17,6 +17,5 @@ comppack.vhd fpu.vhd -tb_fpu.vhd ( the test bench) - -To run the simulation just execute fpusim.bat in a command prompt \ No newline at end of file +***For simulation **** +To run the simulation read readme.txt in folder test_bench. \ No newline at end of file 1.2 jop/vhdl/fpu/serial_div.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/serial_div.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: serial_div.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/fpu/serial_div.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- serial_div.vhd 30 Jan 2006 13:13:56 -0000 1.1 +++ serial_div.vhd 27 Mar 2007 15:47:30 -0000 1.2 @@ -137,7 +137,11 @@ variable v_div : std_logic_vector(26 downto 0); begin if rising_edge(clk_i) then - if s_state=busy then + --Reset + if s_start_i ='1' then + s_qutnt_o <= (others =>'0'); + s_rmndr_o <= (others =>'0'); + elsif s_state=busy then if s_count=26 then v_div := "000" & s_dvdnd_i(49 downto 26); else 1.2 jop/vhdl/fpu/sqrt.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/sqrt.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: sqrt.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/fpu/sqrt.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- sqrt.vhd 30 Jan 2006 13:13:56 -0000 1.1 +++ sqrt.vhd 27 Mar 2007 15:47:30 -0000 1.2 @@ -178,7 +178,9 @@ process(clk_i) begin if rising_edge(clk_i) then - if s_count=0 then + if s_start_i = '1' then + s_sqr_o <= (others =>'0'); + elsif s_count=0 then if r1_2 > s_rad_i then s_sqr_o <= r1 - '1'; else 1.1 jop/vhdl/fpu/bug_report.txt http://www.opencores.org/cvsweb.shtml/jop/vhdl/fpu/bug_report.txt?rev=1.1&content-type=text/x-cvsweb-markup Index: bug_report.txt =================================================================== ==fpu_v16== 1) Corrected an embarrassing sytax error in "tb_fpu.vhd": start_i <= 0 to start_i <= '0' 2) In "serial_div.vhd" and "sqrt.vhd": unused bits in some signals were initialized. 3)Not need line in "fpusim.bat" was removed. ==fpu_v17== 1)Corrected bug related to adding two denormalized operands.

     
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