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Message
From: cvs at opencores.org<cvs@o...>
Date: Tue Mar 27 02:23:55 CEST 2007
Subject: [cvs-checkins] MODIFIED: s1_core ...
Date: 00/07/03 27:02:23 Modified: s1_core/docs/other ACCESSES.txt
Log:
Added comment for 8 stores to Interrupt Queue Registers that have been removed.
Revision Changes Path
1.4 s1_core/docs/other/ACCESSES.txt
http://www.opencores.org/cvsweb.shtml/s1_core/docs/other/ACCESSES.txt.diff?r1=1.3&r2=1.4
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ACCESSES.txt
===================================================================
RCS file: /cvsroot/fafa1971/s1_core/docs/other/ACCESSES.txt,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- ACCESSES.txt 26 Mar 2007 17:17:11 -0000 1.3
+++ ACCESSES.txt 27 Mar 2007 00:23:55 -0000 1.4
@@ -45,20 +45,24 @@
Fetches from RAM Bank 0 (section RED_EXT_SEC)
=============================================
+*** BEGIN ***
+
+These 8 stores to Interrupt Queue ASI Registers were removed
+to obtain clean waveforms. Further investigation will follow
+when full support for interrupts will be added.
+
0000040100: c0 f0 23 c0 stxa %g0, [ 0x3c0 ] %asi
0000040104: c0 f0 23 c8 stxa %g0, [ 0x3c8 ] %asi
0000040108: c0 f0 23 d0 stxa %g0, [ 0x3d0 ] %asi
000004010c: c0 f0 23 d8 stxa %g0, [ 0x3d8 ] %asi
-*** Here the SPARC Core of the S1 sends a dirty request and hangs ***
-
-*** The following fetches are seen only in the original T1 sims (RAM Bank may vary) ***
-
0000040110: c0 f0 23 e0 stxa %g0, [ 0x3e0 ] %asi
0000040114: c0 f0 23 e8 stxa %g0, [ 0x3e8 ] %asi
0000040118: c0 f0 23 f0 stxa %g0, [ 0x3f0 ] %asi
000004011c: c0 f0 23 f8 stxa %g0, [ 0x3f8 ] %asi
+*** END ***
+
0000040120: 8f 90 20 00 wrpr 0, %tl
0000040124: a1 90 20 00 wrpr 0, %gl
0000040128: 8d 80 20 00 wr %g0, 0, %fprs
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