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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Tue Mar 27 01:02:20 CEST 2007
    Subject: [cvs-checkins] MODIFIED: s1_core ...
    Top
    Date: 00/07/03 27:01:02

    Added: s1_core/hdl/rtl/sparc_core/include ifu.h iop.h lsu.h sys.h
    sys_paths.h tlu.h xst_defines.h
    Log:
    Fresh files taken from most recent OpenSPARC 1.4.




    Revision Changes Path
    1.3 s1_core/hdl/rtl/sparc_core/include/ifu.h

    http://www.opencores.org/cvsweb.shtml/s1_core/hdl/rtl/sparc_core/include/ifu.h.diff?r1=1.2&r2=1.3

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: ifu.h
    ===================================================================
    RCS file: ifu.h
    diff -N ifu.h
    --- /dev/null 1 Jan 1970 00:00:00 -0000
    +++ ifu.h 26 Mar 2007 23:02:19 -0000 1.3
    @@ -0,0 +1,180 @@
    +/*
    +* ========== Copyright Header Begin ==========================================
    +*
    +* OpenSPARC T1 Processor File: ifu.h
    +* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
    +* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
    +*
    +* The above named program is free software; you can redistribute it and/or
    +* modify it under the terms of the GNU General Public
    +* License version 2 as published by the Free Software Foundation.
    +*
    +* The above named program is distributed in the hope that it will be
    +* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
    +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
    +* General Public License for more details.
    +*
    +* You should have received a copy of the GNU General Public
    +* License along with this work; if not, write to the Free Software
    +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
    +*
    +* ========== Copyright Header End ============================================
    +*/
    +////////////////////////////////////////////////////////////////////////
    +/*
    +//
    +// Module Name: ifu.h
    +// Description:
    +// All ifu defines
    +*/
    +
    +//--------------------------------------------
    +// Icache Values in IFU::ICD/ICV/ICT/FDP/IFQDP
    +//--------------------------------------------
    +// Set Values
    +`define IC_SZ 16384
    +// IC_IDX_HI = log(icache_size/4ways) - 1
    +`define IC_IDX_HI 11
    +
    +// !!IMPORTANT!! a change to IC_LINE_SZ will mean a change to the code as
    +// well. Unfortunately this has not been properly parametrized.
    +// Changing the IC_LINE_SZ param alone is *not* enough.
    +`define IC_LINE_SZ 32
    +
    +// !!IMPORTANT!! a change to IC_TAG_HI will mean a change to the code as
    +// well. Changing the IC_TAG_HI param alone is *not* enough to
    +// change the PA range.
    +// highest bit of PA
    +`define IC_TAG_HI 39
    +
    +
    +// Derived Values
    +// 4095
    +`define IC_ARR_HI (`IC_SZ/4 - 1)
    +
    +// number of entries - 1 = 511
    +`define IC_ENTRY_HI ((`IC_SZ/`IC_LINE_SZ) - 1)
    +
    +// 12
    +`define IC_TAG_LO (`IC_IDX_HI + 1)
    +
    +// 28
    +`define IC_TAG_SZ (`IC_TAG_HI - `IC_IDX_HI)
    +
    +// 7
    +`define IC_IDX_SZ (`IC_IDX_HI - 4)
    +
    +// tags for all 4 ways + parity
    +// 116
    +`define IC_TAG_ALL ((`IC_TAG_SZ * 4) + 4)
    +
    +// 115
    +`define IC_TAG_ALL_HI ((`IC_TAG_SZ * 4) + 3)
    +
    +
    +//----------------------------------------------------------------------
    +// For thread scheduler in IFU::DTU::SWL
    +//----------------------------------------------------------------------
    +// thread states: (thr_state[4:0])
    +`define THRFSM_DEAD 5'b00000 +`define THRFSM_IDLE 5'b00000 +`define THRFSM_HALT 5'b00010 +`define THRFSM_RDY 5'b11001 +`define THRFSM_SPEC_RDY 5'b10011 +`define THRFSM_RUN 5'b00101 +`define THRFSM_SPEC_RUN 5'b00111 +`define THRFSM_WAIT 5'b00001 + +// thread configuration register bit fields +`define TCR_READY 4 +`define TCR_URDY 3 +`define TCR_RUNNING 2 +`define TCR_SPEC 1 +`define TCR_ACTIVE 0 + + +//---------------------------------------------------------------------- +// For MIL fsm in IFU::IFQ +//---------------------------------------------------------------------- +`define MILFSM_NULL 4'b0000 +`define MILFSM_WAIT 4'b1000 +`define MILFSM_REQ 4'b1100 +`define MILFSM_FILL0 4'b1001 +`define MILFSM_FILL1 4'b1011 + +`define MIL_V 3 +`define MIL_R 2 +`define MIL_A 1 +`define MIL_F 0 + +//--------------------------------------------------- +// Interrupt Block +//--------------------------------------------------- +`define INT_VEC_HI 5 +`define INT_VEC_LO 0 +`define INT_THR_HI 12 +`define INT_THR_LO 8 +`define INT_TYPE_HI 17 +`define INT_TYPE_LO 16 + +//------------------------------------- +// IFQ +//------------------------------------- +// valid bit plus ifill +`define CPX_IFILLPKT {1'b1, `IFILL_RET} +`define CPX_INVPKT {1'b1, `INV_RET} +`define CPX_STRPKT {1'b1, `ST_ACK} +`define CPX_STRMACK {1'b1, `STRST_ACK} +`define CPX_EVPKT {1'b1, `EVICT_REQ} +`define CPX_LDPKT {1'b1, `LOAD_RET} +`define CPX_ERRPKT {1'b1, `ERR_RET} +`define CPX_FREQPKT {1'b1, `FWD_RQ_RET} + +`define CPX_REQFIELD `CPX_RQ_HI:`CPX_RQ_LO +`define CPX_THRFIELD `CPX_TH_HI:`CPX_TH_LO +`define CPX_RQ_SIZE (`CPX_RQ_HI - `CPX_RQ_LO + 1) + +//`ifdef SPARC_L2_64B +`define BANK_ID_HI 7 +`define BANK_ID_LO 6 +//`else +//`define BANK_ID_HI 8 +//`define BANK_ID_LO 7 +//`endif + +//`define CPX_INV_PA_HI 116 +//`define CPX_INV_PA_LO 112 + +`define IFU_ASI_VA_HI 17 +`define IFU_ASI_DATA_HI 47 + +`define ICT_FILL_BITS (32 - `IC_TAG_SZ) +`define ICV_IDX_SZ (`IC_IDX_HI - 5) + +//---------------------------------------- +// IFU Traps +//---------------------------------------- +// precise +`define INST_ACC_EXC 9'h008 +`define INST_ACC_ERR 9'h00a +`define CORR_ECC_ERR 9'h063 +`define DATA_ACC_ERR 9'h032 +`define DATA_ERR 9'h078 +`define ASYN_DATA_ERR 9'h040 +`define INST_ACC_MMU_MS 9'h009 +`define FAST_MMU_MS 9'h064 +`define PRIV_OPC 9'h011 +`define ILL_INST 9'h010 +`define SIR 9'h004 +`define FP_DISABLED 9'h020 +`define REAL_TRANS_MS 9'h03e +`define INST_BRK_PT 9'h076 + +// disrupting +`define SPU_MAINT 9'h074 +`define SPU_ENCINT 9'h070 +`define HSTICK_CMP 9'h05e +`define RESUMABLE_ERR 9'h07e + + + 1.3 s1_core/hdl/rtl/sparc_core/include/iop.h http://www.opencores.org/cvsweb.shtml/s1_core/hdl/rtl/sparc_core/include/iop.h.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: iop.h =================================================================== RCS file: iop.h diff -N iop.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ iop.h 26 Mar 2007 23:02:19 -0000 1.3 @@ -0,0 +1,839 @@ +/* +* ========== Copyright Header Begin ========================================== +* +* OpenSPARC T1 Processor File: iop.h +* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +* +* The above named program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public +* License version 2 as published by the Free Software Foundation. +* +* The above named program is distributed in the hope that it will be +* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +* +* You should have received a copy of the GNU General Public +* License along with this work; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +* +* ========== Copyright Header End ============================================ +*/ +//-*- verilog -*- +//////////////////////////////////////////////////////////////////////// +/* +// +// Description: Global header file that contain definitions that +// are common/shared at the IOP chip level +*/ +//////////////////////////////////////////////////////////////////////// + + +// Address Map Defines +// =================== +`define ADDR_MAP_HI 39 +`define ADDR_MAP_LO 32 +`define IO_ADDR_BIT 39 + +// CMP space +`define DRAM_DATA_LO 8'h00 +`define DRAM_DATA_HI 8'h7f + +// IOP space +`define JBUS1 8'h80 +`define RESERVED_5 8'h81 //`define HASH_TBL_NRAM_CSR 8'h81 +`define RESERVED_1 8'h82 +`define RESERVED_6_LO 8'h83 //`define ENET_MAC_CSR 8'h83 + //`define ENET_ING_CSR 8'h84 + //`define ENET_EGR_CMD_CSR 8'h85 +`define RESERVED_6_HI 8'h86 //`define ENET_EGR_DP_CSR 8'h86 +`define RESERVED_2_LO 8'h87 +`define RESERVED_2_HI 8'h92 +`define RESERVED_7 8'h93 //`define BSC_CSR 8'h93 +`define RESERVED_3 8'h94 +`define RESERVED_8 8'h95 //`define RAND_GEN_CSR 8'h95 +`define CLOCK_UNIT_CSR 8'h96 +`define DRAM_CSR 8'h97 +`define IOB_MAN_CSR 8'h98 +`define TAP_CSR 8'h99 +`define RESERVED_4_L0 8'h9a +`define RESERVED_4_HI 8'h9d +`define CPU_ASI 8'h9e +`define IOB_INT_CSR 8'h9f + +// L2 space +`define L2C_CSR_LO 8'ha0 +`define L2C_CSR_HI 8'hbf + +// More IOP space +`define JBUS2_LO 8'hc0 +`define JBUS2_HI 8'hfe +`define SPI_CSR 8'hff + + +//Cache Crossbar Width and Field Defines +//====================================== +`define PCX_WIDTH 124 //PCX payload packet width +`define CPX_WIDTH 145 //CPX payload packet width + +`define PCX_VLD 123 //PCX packet valid +`define PCX_RQ_HI 122 //PCX request type field +`define PCX_RQ_LO 118 +`define PCX_NC 117 //PCX non-cacheable bit +`define PCX_R 117 //PCX read/!write bit +`define PCX_CP_HI 116 //PCX cpu_id field +`define PCX_CP_LO 114 +`define PCX_TH_HI 113 //PCX Thread field +`define PCX_TH_LO 112 +`define PCX_BF_HI 111 //PCX buffer id field +`define PCX_INVALL 111 +`define PCX_BF_LO 109 +`define PCX_WY_HI 108 //PCX replaced L1 way field +`define PCX_WY_LO 107 +`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01 +`define PCX_P_LO 107 +`define PCX_SZ_HI 106 //PCX load/store size field +`define PCX_SZ_LO 104 +`define PCX_ERR_HI 106 //PCX error field +`define PCX_ERR_LO 104 +`define PCX_AD_HI 103 //PCX address field +`define PCX_AD_LO 64 +`define PCX_DA_HI 63 //PCX Store data +`define PCX_DA_LO 0 + +`define PCX_SZ_1B 3'b000 // encoding for 1B access +`define PCX_SZ_2B 3'b001 // encoding for 2B access +`define PCX_SZ_4B 3'b010 // encoding for 4B access +`define PCX_SZ_8B 3'b011 // encoding for 8B access +`define PCX_SZ_16B 3'b111 // encoding for 16B access + +`define CPX_VLD 144 //CPX payload packet valid + +`define CPX_RQ_HI 143 //CPX Request type +`define CPX_RQ_LO 140 +`define CPX_ERR_HI 139 //CPX error field +`define CPX_ERR_LO 137 +`define CPX_NC 136 //CPX non-cacheable +`define CPX_R 136 //CPX read/!write bit +`define CPX_TH_HI 135 //CPX thread ID field +`define CPX_TH_LO 134 + +//bits 133:128 are shared by different fields +//for different packet types. + +`define CPX_IN_HI 133 //CPX Interrupt source +`define CPX_IN_LO 128 + +`define CPX_WYVLD 133 //CPX replaced way valid +`define CPX_WY_HI 132 //CPX replaced I$/D$ way +`define CPX_WY_LO 131 +`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits +`define CPX_BF_LO 128 + +`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits +`define CPX_SI_LO 128 //used for invalidates + +`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01 +`define CPX_P_LO 130 + +`define CPX_ASI 130 //CPX forward request to ASI +`define CPX_IF4B 130 +`define CPX_IINV 124 +`define CPX_DINV 123 +`define CPX_INVPA5 122 +`define CPX_INVPA4 121 +`define CPX_CPUID_HI 120 +`define CPX_CPUID_LO 118 +`define CPX_INV_PA_HI 116 +`define CPX_INV_PA_LO 112 +`define CPX_INV_IDX_HI 117 +`define CPX_INV_IDX_LO 112 + +`define CPX_DA_HI 127 //CPX data payload +`define CPX_DA_LO 0 + +`define LOAD_RQ 5'b00000 +`define IMISS_RQ 5'b10000 +`define STORE_RQ 5'b00001 +`define CAS1_RQ 5'b00010 +`define CAS2_RQ 5'b00011 +`define SWAP_RQ 5'b00110 +`define STRLOAD_RQ 5'b00100 +`define STRST_RQ 5'b00101 +`define STQ_RQ 5'b00111 +`define INT_RQ 5'b01001 +`define FWD_RQ 5'b01101 +`define FWD_RPY 5'b01110 +`define RSVD_RQ 5'b11111 + +`define LOAD_RET 4'b0000 +`define INV_RET 4'b0011 +`define ST_ACK 4'b0100 +`define AT_ACK 4'b0011 +`define INT_RET 4'b0111 +`define TEST_RET 4'b0101 +`define FP_RET 4'b1000 +`define IFILL_RET 4'b0001 +`define EVICT_REQ 4'b0011 +`define ERR_RET 4'b1100 +`define STRLOAD_RET 4'b0010 +`define STRST_ACK 4'b0110 +`define FWD_RQ_RET 4'b1010 +`define FWD_RPY_RET 4'b1011 +`define RSVD_RET 4'b1111 + +//End cache crossbar defines + + +// Number of COS supported by EECU +`define EECU_COS_NUM 2 + + +// +// BSC bus sizes +// ============= +// + +// General +`define BSC_ADDRESS 40 +`define MAX_XFER_LEN 7'b0 +`define XFER_LEN_WIDTH 6 + +// CTags +`define BSC_CTAG_SZ 12 +`define EICU_CTAG_PRE 5'b11101 +`define EICU_CTAG_REM 7 +`define EIPU_CTAG_PRE 3'b011 +`define EIPU_CTAG_REM 9 +`define EECU_CTAG_PRE 8'b11010000 +`define EECU_CTAG_REM 4 +`define EEPU_CTAG_PRE 6'b010000 +`define EEPU_CTAG_REM 6 +`define L2C_CTAG_PRE 2'b00 +`define L2C_CTAG_REM 10 +`define JBI_CTAG_PRE 2'b10 +`define JBI_CTAG_REM 10 +// reinstated temporarily +`define PCI_CTAG_PRE 7'b1101100 +`define PCI_CTAG_REM 5 + + +// CoS +`define EICU_COS 1'b0 +`define EIPU_COS 1'b1 +`define EECU_COS 1'b0 +`define EEPU_COS 1'b1 +`define PCI_COS 1'b0 + +// L2$ Bank +`define BSC_L2_BNK_HI 8 +`define BSC_L2_BNK_LO 6 + +// L2$ Req +`define BSC_L2_REQ_SZ 62 +`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code +`define BSC_L2_BUS 64 +`define BSC_L2_CTAG_HI 61 +`define BSC_L2_CTAG_LO 50 +`define BSC_L2_ADD_HI 49 +`define BSC_L2_ADD_LO 10 +`define BSC_L2_LEN_HI 9 +`define BSC_L2_LEN_LO 3 +`define BSC_L2_ALLOC 2 +`define BSC_L2_COS 1 +`define BSC_L2_READ 0 + +// L2$ Ack +`define L2_BSC_ACK_SZ 16 +`define L2_BSC_BUS 64 +`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address +`define L2_BSC_CBA_LO 13 +`define L2_BSC_READ 12 +`define L2_BSC_CTAG_HI 11 +`define L2_BSC_CTAG_LO 0 + +// Enet Egress Command Unit +`define EECU_REQ_BUS 44 +`define EECU_REQ_SZ 44 +`define EECU_R_QID_HI 43 +`define EECU_R_QID_LO 40 +`define EECU_R_ADD_HI 39 +`define EECU_R_ADD_LO 0 + +`define EECU_ACK_BUS 64 +`define EECU_ACK_SZ 5 +`define EECU_A_NACK 4 +`define EECU_A_QID_HI 3 +`define EECU_A_QID_LO 0 + + +// Enet Egress Packet Unit +`define EEPU_REQ_BUS 55 +`define EEPU_REQ_SZ 55 +`define EEPU_R_TLEN_HI 54 +`define EEPU_R_TLEN_LO 48 +`define EEPU_R_SOF 47 +`define EEPU_R_EOF 46 +`define EEPU_R_PORT_HI 45 +`define EEPU_R_PORT_LO 44 +`define EEPU_R_QID_HI 43 +`define EEPU_R_QID_LO 40 +`define EEPU_R_ADD_HI 39 +`define EEPU_R_ADD_LO 0 + +// This is cleaved in between Egress Datapath Ack's +`define EEPU_ACK_BUS 6 +`define EEPU_ACK_SZ 6 +`define EEPU_A_EOF 5 +`define EEPU_A_NACK 4 +`define EEPU_A_QID_HI 3 +`define EEPU_A_QID_LO 0 + + +// Enet Egress Datapath +`define EEDP_ACK_BUS 128 +`define EEDP_ACK_SZ 28 +`define EEDP_A_NACK 27 +`define EEDP_A_QID_HI 26 +`define EEDP_A_QID_LO 21 +`define EEDP_A_SOF 20 +`define EEDP_A_EOF 19 +`define EEDP_A_LEN_HI 18 +`define EEDP_A_LEN_LO 12 +`define EEDP_A_TAG_HI 11 +`define EEDP_A_TAG_LO 0 +`define EEDP_A_PORT_HI 5 +`define EEDP_A_PORT_LO 4 +`define EEDP_A_PORT_WIDTH 2 + + +// In-Order / Ordered Queue: EEPU +// Tag is: TLEN, SOF, EOF, QID = 15 +`define EEPU_TAG_ARY (7+1+1+6) +`define EEPU_ENTRIES 16 +`define EEPU_E_IDX 4 +`define EEPU_PORTS 4 +`define EEPU_P_IDX 2 + +// Nack + Tag Info + CTag +`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12) +`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX) + + +// ENET Ingress Queue Management Req +`define EICU_REQ_BUS 64 +`define EICU_REQ_SZ 62 +`define EICU_R_CTAG_HI 61 +`define EICU_R_CTAG_LO 50 +`define EICU_R_ADD_HI 49 +`define EICU_R_ADD_LO 10 +`define EICU_R_LEN_HI 9 +`define EICU_R_LEN_LO 3 +`define EICU_R_COS 1 +`define EICU_R_READ 0 + + +// ENET Ingress Queue Management Ack +`define EICU_ACK_BUS 64 +`define EICU_ACK_SZ 14 +`define EICU_A_NACK 13 +`define EICU_A_READ 12 +`define EICU_A_CTAG_HI 11 +`define EICU_A_CTAG_LO 0 + + +// Enet Ingress Packet Unit +`define EIPU_REQ_BUS 128 +`define EIPU_REQ_SZ 59 +`define EIPU_R_CTAG_HI 58 +`define EIPU_R_CTAG_LO 50 +`define EIPU_R_ADD_HI 49 +`define EIPU_R_ADD_LO 10 +`define EIPU_R_LEN_HI 9 +`define EIPU_R_LEN_LO 3 +`define EIPU_R_COS 1 +`define EIPU_R_READ 0 + + +// ENET Ingress Packet Unit Ack +`define EIPU_ACK_BUS 10 +`define EIPU_ACK_SZ 10 +`define EIPU_A_NACK 9 +`define EIPU_A_CTAG_HI 8 +`define EIPU_A_CTAG_LO 0 + + +// In-Order / Ordered Queue: PCI +// Tag is: CTAG +`define PCI_TAG_ARY 12 +`define PCI_ENTRIES 16 +`define PCI_E_IDX 4 +`define PCI_PORTS 2 + +// PCI-X Request +`define PCI_REQ_BUS 64 +`define PCI_REQ_SZ 62 +`define PCI_R_CTAG_HI 61 +`define PCI_R_CTAG_LO 50 +`define PCI_R_ADD_HI 49 +`define PCI_R_ADD_LO 10 +`define PCI_R_LEN_HI 9 +`define PCI_R_LEN_LO 3 +`define PCI_R_COS 1 +`define PCI_R_READ 0 + +// PCI_X Acknowledge +`define PCI_ACK_BUS 64 +`define PCI_ACK_SZ 14 +`define PCI_A_NACK 13 +`define PCI_A_READ 12 +`define PCI_A_CTAG_HI 11 +`define PCI_A_CTAG_LO 0 + + +`define BSC_MAX_REQ_SZ 62 + + +// +// BSC array sizes +//================ +// +`define BSC_REQ_ARY_INDEX 6 +`define BSC_REQ_ARY_DEPTH 64 +`define BSC_REQ_ARY_WIDTH 62 +`define BSC_REQ_NXT_WIDTH 12 +`define BSC_ACK_ARY_INDEX 6 +`define BSC_ACK_ARY_DEPTH 64 +`define BSC_ACK_ARY_WIDTH 14 +`define BSC_ACK_NXT_WIDTH 12 +`define BSC_PAY_ARY_INDEX 6 +`define BSC_PAY_ARY_DEPTH 64 +`define BSC_PAY_ARY_WIDTH 256 + +// ECC syndrome bits per memory element +`define BSC_PAY_ECC 10 +`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH) + + +// +// BSC Port Definitions +// ==================== +// +// Bits 7 to 4 of curr_port_id +`define BSC_PORT_NULL 4'h0 +`define BSC_PORT_SC 4'h1 +`define BSC_PORT_EICU 4'h2 +`define BSC_PORT_EIPU 4'h3 +`define BSC_PORT_EECU 4'h4 +`define BSC_PORT_EEPU 4'h8 +`define BSC_PORT_PCI 4'h9 + +// Number of ports of each type +`define BSC_PORT_SC_CNT 8 + +// Bits needed to represent above +`define BSC_PORT_SC_IDX 3 + +// How wide the linked list pointers are +// 60b for no payload (2CoS) +// 80b for payload (2CoS) + +//`define BSC_OBJ_PTR 80 +//`define BSC_HD1_HI 69 +//`define BSC_HD1_LO 60 +//`define BSC_TL1_HI 59 +//`define BSC_TL1_LO 50 +//`define BSC_CT1_HI 49 +//`define BSC_CT1_LO 40 +//`define BSC_HD0_HI 29 +//`define BSC_HD0_LO 20 +//`define BSC_TL0_HI 19 +//`define BSC_TL0_LO 10 +//`define BSC_CT0_HI 9 +//`define BSC_CT0_LO 0 + +`define BSC_OBJP_PTR 48 +`define BSC_PYP1_HI 47 +`define BSC_PYP1_LO 42 +`define BSC_HDP1_HI 41 +`define BSC_HDP1_LO 36 +`define BSC_TLP1_HI 35 +`define BSC_TLP1_LO 30 +`define BSC_CTP1_HI 29 +`define BSC_CTP1_LO 24 +`define BSC_PYP0_HI 23 +`define BSC_PYP0_LO 18 +`define BSC_HDP0_HI 17 +`define BSC_HDP0_LO 12 +`define BSC_TLP0_HI 11 +`define BSC_TLP0_LO 6 +`define BSC_CTP0_HI 5 +`define BSC_CTP0_LO 0 + +`define BSC_PTR_WIDTH 192 +`define BSC_PTR_REQ_HI 191 +`define BSC_PTR_REQ_LO 144 +`define BSC_PTR_REQP_HI 143 +`define BSC_PTR_REQP_LO 96 +`define BSC_PTR_ACK_HI 95 +`define BSC_PTR_ACK_LO 48 +`define BSC_PTR_ACKP_HI 47 +`define BSC_PTR_ACKP_LO 0 + +`define BSC_PORT_SC_PTR 96 // R, R+P +`define BSC_PORT_EECU_PTR 48 // A+P +`define BSC_PORT_EICU_PTR 96 // A, A+P +`define BSC_PORT_EIPU_PTR 48 // A + +// I2C STATES in DRAMctl +`define I2C_CMD_NOP 4'b0000 +`define I2C_CMD_START 4'b0001 +`define I2C_CMD_STOP 4'b0010 +`define I2C_CMD_WRITE 4'b0100 +`define I2C_CMD_READ 4'b1000 + + +// +// IOB defines +// =========== +// +`define IOB_ADDR_WIDTH 40 +`define IOB_LOCAL_ADDR_WIDTH 32 + +`define IOB_CPU_INDEX 3 +`define IOB_CPU_WIDTH 8 +`define IOB_THR_INDEX 2 +`define IOB_THR_WIDTH 4 +`define IOB_CPUTHR_INDEX 5 +`define IOB_CPUTHR_WIDTH 32 + +`define IOB_MONDO_DATA_INDEX 5 +`define IOB_MONDO_DATA_DEPTH 32 +`define IOB_MONDO_DATA_WIDTH 64 +`define IOB_MONDO_SRC_WIDTH 5 +`define IOB_MONDO_BUSY 5 + +`define IOB_INT_TAB_INDEX 2 +`define IOB_INT_TAB_DEPTH 4 + +//`define IOB_INT_STAT_WIDTH 32 +//`define IOB_INT_STAT_HI 31 +//`define IOB_INT_STAT_LO 0 + +`define IOB_INT_VEC_WIDTH 6 +`define IOB_INT_VEC_HI 5 +`define IOB_INT_VEC_LO 0 + +`define IOB_INT_CPU_WIDTH 5 +`define IOB_INT_CPU_HI 12 +`define IOB_INT_CPU_LO 8 + +`define IOB_INT_MASK 2 +`define IOB_INT_CLEAR 1 +`define IOB_INT_PEND 0 + +`define IOB_DISP_TYPE_HI 17 +`define IOB_DISP_TYPE_LO 16 +`define IOB_DISP_THR_HI 12 +`define IOB_DISP_THR_LO 8 +`define IOB_DISP_VEC_HI 5 +`define IOB_DISP_VEC_LO 0 + +`define IOB_JBI_RESET 1 +`define IOB_ENET_RESET 0 + +`define IOB_RESET_STAT_WIDTH 3 +`define IOB_RESET_STAT_HI 3 +`define IOB_RESET_STAT_LO 1 + +`define IOB_SERNUM_WIDTH 64 + +`define IOB_FUSE_WIDTH 22 + +`define IOB_TMSTAT_THERM 63 + +`define IOB_POR_TT 6'b01 // power-on-reset trap type + +`define IOB_CPU_BUF_INDEX 4 + +`define IOB_INT_BUF_INDEX 4 +`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width + +`define IOB_IO_BUF_INDEX 4 +`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width + +`define IOB_L2_VIS_BUF_INDEX 5 +`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width + +`define IOB_INT_AVEC_WIDTH 9 // availibility vector width +`define IOB_ACK_AVEC_WIDTH 9 // availibility vector width + +// fixme - double check address mapping +// CREG in `IOB_INT_CSR space +`define IOB_DEV_ADDR_MASK 32'hffffffe7 +`define IOB_CREG_INTSTAT 32'h00000000 +`define IOB_CREG_MDATA0 32'h00000400 +`define IOB_CREG_MDATA1 32'h00000500 +`define IOB_CREG_MBUSY 32'h00000900 +`define IOB_THR_ADDR_MASK 32'hffffff07 +`define IOB_CREG_MDATA0_ALIAS 32'h00000600 +`define IOB_CREG_MDATA1_ALIAS 32'h00000700 +`define IOB_CREG_MBUSY_ALIAS 32'h00000b00 + +// CREG in `IOB_MAN_CSR space +`define IOB_CREG_INTMAN 32'h00000000 +`define IOB_CREG_INTCTL 32'h00000400 +`define IOB_CREG_INTVECDISP 32'h00000800 +`define IOB_CREG_RESETSTAT 32'h00000810 +`define IOB_CREG_SERNUM 32'h00000820 +`define IOB_CREG_TMSTATCTRL 32'h00000828 +`define IOB_CREG_COREAVAIL 32'h00000830 +`define IOB_CREG_SSYSRESET 32'h00000838 +`define IOB_CREG_FUSESTAT 32'h00000840 +`define IOB_CREG_MARGIN 32'h00000850 +`define IOB_CREG_JINTV 32'h00000a00 + +`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800 +`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820 +`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828 +`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830 +`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838 +`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840 +`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000 +`define IOB_CREG_DBG_ENET_CTRL 32'h00002000 +`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008 +`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100 +`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140 +`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160 +`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148 +`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168 +`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150 +`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170 +`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180 +`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0 +`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188 +`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8 +`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190 +`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0 + +`define IOB_CREG_TESTSTUB 32'h80000000 + +// Address map for TAP access of SPARC ASI +`define IOB_ASI_PC 4'b0000 +`define IOB_ASI_BIST 4'b0001 +`define IOB_ASI_MARGIN 4'b0010 +`define IOB_ASI_DEFEATURE 4'b0011 +`define IOB_ASI_L1DD 4'b0100 +`define IOB_ASI_L1ID 4'b0101 +`define IOB_ASI_L1DT 4'b0110 + +`define IOB_INT 2'b00 +`define IOB_RESET 2'b01 +`define IOB_IDLE 2'b10 +`define IOB_RESUME 2'b11 + +// +// CIOP UCB Bus Width +// ================== +// +//`define IOB_EECU_WIDTH 16 // ethernet egress command +//`define EECU_IOB_WIDTH 16 + +//`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously) +//`define NRAM_IOB_WIDTH 4 + +`define IOB_JBI_WIDTH 64 // JBI +`define JBI_IOB_WIDTH 16 + +//`define IOB_ENET_ING_WIDTH 32 // ethernet ingress +//`define ENET_ING_IOB_WIDTH 8 + +//`define IOB_ENET_EGR_WIDTH 4 // ethernet egress +//`define ENET_EGR_IOB_WIDTH 4 + +//`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC +//`define ENET_MAC_IOB_WIDTH 4 + +`define IOB_DRAM_WIDTH 4 // DRAM controller +`define DRAM_IOB_WIDTH 4 + +//`define IOB_BSC_WIDTH 4 // BSC +//`define BSC_IOB_WIDTH 4 + +`define IOB_SPI_WIDTH 4 // SPI (Boot ROM) +`define SPI_IOB_WIDTH 4 + +`define IOB_CLK_WIDTH 4 // clk unit +`define CLK_IOB_WIDTH 4 + +//`define IOB_CLSP_WIDTH 4 // clk spine unit +//`define CLSP_IOB_WIDTH 4 + +`define IOB_TAP_WIDTH 8 // TAP +`define TAP_IOB_WIDTH 8 + + +// +// CIOP UCB Buf ID Type +// ==================== +// +`define UCB_BID_CMP 2'b00 +`define UCB_BID_TAP 2'b01 + +// +// Interrupt Device ID +// =================== +// +// Caution: DUMMY_DEV_ID has to be 9 bit wide +// for fields to line up properly in the IOB. +`define DUMMY_DEV_ID 9'h00 // 0 +`define UNCOR_ECC_DEV_ID 7'd1 // 1 + +// +// Soft Error related definitions +// ============================== +// +`define COR_ECC_CNT_WIDTH 16 + + +// +// CMP clock +// ========= +// + +`define CMP_CLK_PERIOD 1333 + + +// +// NRAM/IO Interface +// ================= +// + +`define DRAM_CLK_PERIOD 6000 + +`define NRAM_IO_DQ_WIDTH 32 +`define IO_NRAM_DQ_WIDTH 32 + +`define NRAM_IO_ADDR_WIDTH 15 +`define NRAM_IO_BA_WIDTH 2 + + +// +// NRAM/ENET Interface +// =================== +// + +`define NRAM_ENET_DATA_WIDTH 64 +`define ENET_NRAM_ADDR_WIDTH 20 + +`define NRAM_DBG_DATA_WIDTH 40 + + +// +// IO/FCRAM Interface +// ================== +// + +`define FCRAM_DATA1_HI 63 +`define FCRAM_DATA1_LO 32 +`define FCRAM_DATA0_HI 31 +`define FCRAM_DATA0_LO 0 + +// +// PCI Interface +// ================== +// Load/store size encodings +// ------------------------- +// Size encoding +// 000 - byte +// 001 - half-word +// 010 - word +// 011 - double-word +// 100 - quad +`define LDST_SZ_BYTE 3'b000 +`define LDST_SZ_HALF_WORD 3'b001 +`define LDST_SZ_WORD 3'b010 +`define LDST_SZ_DOUBLE_WORD 3'b011 +`define LDST_SZ_QUAD 3'b100 + +// +// JBI<->SCTAG Interface +// ======================= +// Outbound Header Format +`define JBI_BTU_OUT_ADDR_LO 0 +`define JBI_BTU_OUT_ADDR_HI 42 +`define JBI_BTU_OUT_RSV0_LO 43 +`define JBI_BTU_OUT_RSV0_HI 43 +`define JBI_BTU_OUT_TYPE_LO 44 +`define JBI_BTU_OUT_TYPE_HI 48 +`define JBI_BTU_OUT_RSV1_LO 49 +`define JBI_BTU_OUT_RSV1_HI 51 +`define JBI_BTU_OUT_REPLACE_LO 52 +`define JBI_BTU_OUT_REPLACE_HI 56 +`define JBI_BTU_OUT_RSV2_LO 57 +`define JBI_BTU_OUT_RSV2_HI 59 +`define JBI_BTU_OUT_BTU_ID_LO 60 +`define JBI_BTU_OUT_BTU_ID_HI 71 +`define JBI_BTU_OUT_DATA_RTN 72 +`define JBI_BTU_OUT_RSV3_LO 73 +`define JBI_BTU_OUT_RSV3_HI 75 +`define JBI_BTU_OUT_CE 76 +`define JBI_BTU_OUT_RSV4_LO 77 +`define JBI_BTU_OUT_RSV4_HI 79 +`define JBI_BTU_OUT_UE 80 +`define JBI_BTU_OUT_RSV5_LO 81 +`define JBI_BTU_OUT_RSV5_HI 83 +`define JBI_BTU_OUT_DRAM 84 +`define JBI_BTU_OUT_RSV6_LO 85 +`define JBI_BTU_OUT_RSV6_HI 127 + +// Inbound Header Format +`define JBI_SCTAG_IN_ADDR_LO 0 +`define JBI_SCTAG_IN_ADDR_HI 39 +`define JBI_SCTAG_IN_SZ_LO 40 +`define JBI_SCTAG_IN_SZ_HI 42 +`define JBI_SCTAG_IN_RSV0 43 +`define JBI_SCTAG_IN_TAG_LO 44 +`define JBI_SCTAG_IN_TAG_HI 55 +`define JBI_SCTAG_IN_REQ_LO 56 +`define JBI_SCTAG_IN_REQ_HI 58 +`define JBI_SCTAG_IN_POISON 59 +`define JBI_SCTAG_IN_RSV1_LO 60 +`define JBI_SCTAG_IN_RSV1_HI 63 + +`define JBI_SCTAG_REQ_WRI 3'b100 +`define JBI_SCTAG_REQ_WR8 3'b010 +`define JBI_SCTAG_REQ_RDD 3'b001 +`define JBI_SCTAG_REQ_WRI_BIT 2 +`define JBI_SCTAG_REQ_WR8_BIT 1 +`define JBI_SCTAG_REQ_RDD_BIT 0 + +// +// JBI->IOB Mondo Header Format +// ============================ +// +`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1 +`define JBI_IOB_MONDO_RSV1_LO 13 +`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target +`define JBI_IOB_MONDO_TRG_LO 8 +`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0 +`define JBI_IOB_MONDO_RSV0_LO 5 +`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source +`define JBI_IOB_MONDO_SRC_LO 0 + +`define JBI_IOB_MONDO_RSV1_WIDTH 3 +`define JBI_IOB_MONDO_TRG_WIDTH 5 +`define JBI_IOB_MONDO_RSV0_WIDTH 3 +`define JBI_IOB_MONDO_SRC_WIDTH 5 + +// JBI->IOB Mondo Bus Width/Cycle +// ============================== +// Cycle 1 Header[15:8] +// Cycle 2 Header[ 7:0] +// Cycle 3 J_AD[127:120] +// Cycle 4 J_AD[119:112] +// ..... +// Cycle 18 J_AD[ 7: 0] +`define JBI_IOB_MONDO_BUS_WIDTH 8 +`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data 1.3 s1_core/hdl/rtl/sparc_core/include/lsu.h http://www.opencores.org/cvsweb.shtml/s1_core/hdl/rtl/sparc_core/include/lsu.h.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: lsu.h =================================================================== RCS file: lsu.h diff -N lsu.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ lsu.h 26 Mar 2007 23:02:19 -0000 1.3 @@ -0,0 +1,302 @@ +/* +* ========== Copyright Header Begin ========================================== +* +* OpenSPARC T1 Processor File: lsu.h +* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +* +* The above named program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public +* License version 2 as published by the Free Software Foundation. +* +* The above named program is distributed in the hope that it will be +* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +* +* You should have received a copy of the GNU General Public +* License along with this work; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +* +* ========== Copyright Header End ============================================ +*/ +`define STB_PCX_WIDTH 115 +`define STB_PCX_VLD 114 +`define STB_PCX_RQ_HI 113 +`define STB_PCX_RQ_LO 111 +`define STB_PCX_NC 110 +`define STB_PCX_TH_HI 109 +`define STB_PCX_TH_LO 108 +`define STB_PCX_FLSH 107 +//`define STB_PCX_WY_HI 107 +//`define STB_PCX_WY_LO 106 +`define STB_PCX_SZ_HI 105 +`define STB_PCX_SZ_LO 104 +`define STB_PCX_AD_HI 103 +`define STB_PCX_AD_LO 64 +`define STB_PCX_DA_HI 63 +`define STB_PCX_DA_LO 0 +`define LMQ_WIDTH 65 +`define LMQ_VLD 64 +`define LMQ_DFLUSH 63 +`define LMQ_PREF 62 +`define LMQ_FPLD 61 +`define LMQ_SIGNEXT 60 +`define LMQ_BIGEND 59 +`define LMQ_RD1_HI 58 +`define LMQ_RD1_LO 54 +`define LMQ_RD2_VLD 53 +`define LMQ_RD2_HI 52 +`define LMQ_RD2_LO 51 +`define LMQ_RQ_HI 47 +`define LMQ_RQ_LO 45 +`define LMQ_NC 44 +`define LMQ_WY_HI 43 +`define LMQ_WY_LO 42 +`define LMQ_SZ_HI 41 +`define LMQ_SZ_LO 40 +`define LMQ_AD_HI 39 +`define LMQ_AD_LO 0 +`define DATA_PA_HI 32 +`define DATA_PA_LO 6 +`define STB_DFQ_WIDTH 83 +`define STB_DFQ_VLD 82 +`define STB_DFQ_ATM 81 +`define STB_DFQ_WY_HI 80 +`define STB_DFQ_WY_LO 79 +`define STB_DFQ_BF_ID_HI 78 +`define STB_DFQ_BF_ID_LO 76 +`define STB_DFQ_SZ_HI 75 +`define STB_DFQ_SZ_LO 74 +`define STB_DFQ_AD_HI 73 +`define STB_DFQ_AD_LO 64 +`define STB_DFQ_DA_HI 63 +`define STB_DFQ_DA_LO 0 + +`define DFQ_WIDTH 151 +`define DFQ_TH_HI 150 +`define DFQ_TH_LO 149 +`define DFQ_ST_CMPLT 148 +`define DFQ_LD_TYPE 147 +`define DFQ_INV_TYPE 146 +`define DFQ_WY_HI 145 +`define DFQ_WY_LO 144 +`define DFQ_WY1_HI 143 +`define DFQ_WY1_LO 142 +`define DFQ_WY2_HI 141 +`define DFQ_WY2_LO 140 +`define DFQ_WY3_HI 139 +`define DFQ_WY3_LO 138 +`define DFQ_SI_HI 137 +`define DFQ_SI_LO 132 +`define DFQ_SI_DCD_HI 131 +`define DFQ_SI_DCD_LO 128 +`define DFQ_DA_HI 127 +`define DFQ_DA_LO 0 + +`define DCFILL_WIDTH 183 +`define DCFILL_TH_HI 182 +`define DCFILL_TH_LO 181 +`define DCFILL_ST 180 +`define DCFILL_ST 180 +`define DCFILL_LD 179 +`define DCFILL_INV 178 +`define DCFILL_DC_WR 177 +`define DCFILL_RD_HI 176 +`define DCFILL_RD_LO 172 +`define DCFILL_WY_HI 171 +`define DCFILL_WY_LO 170 +`define DCFILL_SZ_HI 169 +`define DCFILL_SZ_LO 168 +`define DCFILL_AD_HI 167 +`define DCFILL_AD_LO 128 +`define DCFILL_DA_HI 127 +`define DCFILL_DA_LO 0 + +// TLB Tag and Data Format + `define STLB_TAG_PID_HI 58 + `define STLB_TAG_PID_LO 56 + `define STLB_TAG_R 55 + `define STLB_TAG_PARITY 54 + `define STLB_TAG_VA_47_28_HI 53 + `define STLB_TAG_VA_47_28_LO 34 + `define STLB_TAG_VA_27_22_HI 33 + `define STLB_TAG_VA_27_22_LO 28 + `define STLB_TAG_VA_27_22_V 27 + `define STLB_TAG_V 26 + `define STLB_TAG_L 25 + `define STLB_TAG_U 24 + `define STLB_TAG_VA_21_16_HI 23 + `define STLB_TAG_VA_21_16_LO 18 + `define STLB_TAG_VA_21_16_V 17 + `define STLB_TAG_VA_15_13_HI 16 + `define STLB_TAG_VA_15_13_LO 14 + `define STLB_TAG_VA_15_13_V 13 + `define STLB_TAG_CTXT_12_0_HI 12 + `define STLB_TAG_CTXT_12_0_LO 0 + + `define STLB_DATA_PARITY 42 + `define STLB_DATA_PA_39_28_HI 41 + `define STLB_DATA_PA_39_28_LO 30 + `define STLB_DATA_PA_27_22_HI 29 + `define STLB_DATA_PA_27_22_LO 24 + `define STLB_DATA_27_22_SEL 23 + `define STLB_DATA_PA_21_16_HI 22 + `define STLB_DATA_PA_21_16_LO 17 + `define STLB_DATA_21_16_SEL 16 + `define STLB_DATA_PA_15_13_HI 15 + `define STLB_DATA_PA_15_13_LO 13 + `define STLB_DATA_15_13_SEL 12 + `define STLB_DATA_V 11 + `define STLB_DATA_NFO 10 + `define STLB_DATA_IE 9 + `define STLB_DATA_L 8 + `define STLB_DATA_CP 7 + `define STLB_DATA_CV 6 + `define STLB_DATA_E 5 + `define STLB_DATA_P 4 + `define STLB_DATA_W 3 + `define STLB_DATA_SPARE_HI 2 + `define STLB_DATA_SPARE_LO 0 + + `define CAM_VA_47_28_HI 40 + `define CAM_VA_47_28_LO 21 + `define CAM_VA_47_28_V 20 + `define CAM_VA_27_22_HI 19 + `define CAM_VA_27_22_LO 14 + `define CAM_VA_27_22_V 13 + `define CAM_VA_21_16_HI 12 + `define CAM_VA_21_16_LO 7 + `define CAM_VA_21_16_V 6 + `define CAM_VA_15_13_HI 5 + `define CAM_VA_15_13_LO 3 + `define CAM_VA_15_13_V 2 + `define CAM_CTXT_GK 1 + `define CAM_REAL_V 0 + + +// I-TLB version - lsu_tlb only. + +`define TLB_TAG_G 52 +`define TLB_TAG_CTXT_HI 51 +`define TLB_TAG_CTXT_LO 39 +`define TLB_TAG_VA_HI 38 +`define TLB_TAG_VA_LO 4 +`define TLB_TAG_L 3 +`define TLB_TAG_VA_21_19_V 2 +`define TLB_TAG_VA_18_16_V 1 +`define TLB_TAG_VA_15_13_V 0 +`define TLB_DATA_PARITY 37 +`define TLB_DATA_SZ_HI 36 +`define TLB_DATA_SZ_LO 35 +`define TLB_DATA_NFO 34 +`define TLB_DATA_IE 33 +`define TLB_DATA_PA_HI 32 +`define TLB_DATA_PA_LO 6 +`define TLB_DATA_CP 5 +`define TLB_DATA_CV 4 +`define TLB_DATA_E 3 +`define TLB_DATA_P 2 +`define TLB_DATA_W 1 +`define TLB_DATA_G 0 + +// Invalidate Format +//addr<5:4>=00 +`define CPX_A00_C0_LO 0 +`define CPX_A00_C0_HI 3 +`define CPX_A00_C1_LO 4 +`define CPX_A00_C1_HI 7 +`define CPX_A00_C2_LO 8 +`define CPX_A00_C2_HI 11 +`define CPX_A00_C3_LO 12 +`define CPX_A00_C3_HI 15 +`define CPX_A00_C4_LO 16 +`define CPX_A00_C4_HI 19 +`define CPX_A00_C5_LO 20 +`define CPX_A00_C5_HI 23 +`define CPX_A00_C6_LO 24 +`define CPX_A00_C6_HI 27 +`define CPX_A00_C7_LO 28 +`define CPX_A00_C7_HI 31 + +//addr<5:4>=01 +`define CPX_A01_C0_LO 32 +`define CPX_A01_C0_HI 34 +`define CPX_A01_C1_LO 35 +`define CPX_A01_C1_HI 37 +`define CPX_A01_C2_LO 38 +`define CPX_A01_C2_HI 40 +`define CPX_A01_C3_LO 41 +`define CPX_A01_C3_HI 43 +`define CPX_A01_C4_LO 44 +`define CPX_A01_C4_HI 46 +`define CPX_A01_C5_LO 47 +`define CPX_A01_C5_HI 49 +`define CPX_A01_C6_LO 50 +`define CPX_A01_C6_HI 52 +`define CPX_A01_C7_LO 53 +`define CPX_A01_C7_HI 55 + +//addr<5:4>=10 +`define CPX_A10_C0_LO 56 +`define CPX_A10_C0_HI 59 +`define CPX_A10_C1_LO 60 +`define CPX_A10_C1_HI 63 +`define CPX_A10_C2_LO 64 +`define CPX_A10_C2_HI 67 +`define CPX_A10_C3_LO 68 +`define CPX_A10_C3_HI 71 +`define CPX_A10_C4_LO 72 +`define CPX_A10_C4_HI 75 +`define CPX_A10_C5_LO 76 +`define CPX_A10_C5_HI 79 +`define CPX_A10_C6_LO 80 +`define CPX_A10_C6_HI 83 +`define CPX_A10_C7_LO 84 +`define CPX_A10_C7_HI 87 + +//addr<5:4>=11 +`define CPX_A11_C0_LO 88 +`define CPX_A11_C0_HI 90 +`define CPX_A11_C1_LO 91 +`define CPX_A11_C1_HI 93 +`define CPX_A11_C2_LO 94 +`define CPX_A11_C2_HI 96 +`define CPX_A11_C3_LO 97 +`define CPX_A11_C3_HI 99 +`define CPX_A11_C4_LO 100 +`define CPX_A11_C4_HI 102 +`define CPX_A11_C5_LO 103 +`define CPX_A11_C5_HI 105 +`define CPX_A11_C6_LO 106 +`define CPX_A11_C6_HI 108 +`define CPX_A11_C7_LO 109 +`define CPX_A11_C7_HI 111 + +// cpuid - 4b +`define CPX_INV_CID_LO 118 +`define CPX_INV_CID_HI 120 + +// CPUany, addr<5:4>=00,10 +`define CPX_AX0_INV_DVLD 0 +`define CPX_AX0_INV_IVLD 1 +`define CPX_AX0_INV_WY_LO 2 +`define CPX_AX0_INV_WY_HI 3 + +// CPUany, addr<5:4>=01,11 +`define CPX_AX1_INV_DVLD 0 +`define CPX_AX1_INV_WY_LO 1 +`define CPX_AX1_INV_WY_HI 2 + +// CPUany, addr<5:4>=01,11 +`define CPX_AX1_INV_DVLD 0 +`define CPX_AX1_INV_WY_LO 1 +`define CPX_AX1_INV_WY_HI 2 + +// DTAG parity error Invalidate +`define CPX_PERR_DINV 123 // dcache inv +`define CPX_PERR_DINV_AD5 122 // addr bit 5 +`define CPX_PERR_DINV_AD4 121 // addr bit 4 + +// CPX BINIT STORE +`define CPX_BINIT_STACK 125 // dcache inv 1.3 s1_core/hdl/rtl/sparc_core/include/sys.h http://www.opencores.org/cvsweb.shtml/s1_core/hdl/rtl/sparc_core/include/sys.h.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: sys.h =================================================================== RCS file: sys.h diff -N sys.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sys.h 26 Mar 2007 23:02:19 -0000 1.3 @@ -0,0 +1,278 @@ +/* +* ========== Copyright Header Begin ========================================== +* +* OpenSPARC T1 Processor File: sys.h +* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +* +* The above named program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public +* License version 2 as published by the Free Software Foundation. +* +* The above named program is distributed in the hope that it will be +* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +* +* You should have received a copy of the GNU General Public +* License along with this work; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +* +* ========== Copyright Header End ============================================ +*/ +// -*- verilog -*- +//////////////////////////////////////////////////////////////////////// +/* +// +// Description: Global header file that contain definitions that +// are common/shared at the systme level +*/ +//////////////////////////////////////////////////////////////////////// +// +// Setting the time scale +// If the timescale changes, JP_TIMESCALE may also have to change. +`timescale 1ps/1ps + +// +// JBUS clock +// ========= +// +`define SYSCLK_PERIOD 5000 + + +// Afara Link Defines +// ================== + +// Reliable Link +`define AL_RB_CNT 16 +`define AL_RB_IDX 4 +`define AL_RB_WINDOW `AL_RB_IDX'd8 + +// Afara Link Objects +`define AL_OBJ_SZ 112 + +// Afara Link Object Format - Reliable Link +`define AL_RL_HI 111 +`define AL_RL_LO 103 +`define AL_RL_SZ 9 + +`define AL_ESN_HI 111 +`define AL_ESN_LO 108 +`define AL_SSN_HI 107 +`define AL_SSN_LO 104 +`define AL_ED 103 + +// Afara Link Object Format - Congestion +`define AL_CNG_HI 102 +`define AL_CNG_LO 94 +`define AL_CNG_SZ 9 + +`define AL_REQ_CNG 102 +`define AL_BSCT_HI 101 +`define AL_BSCT_LO 96 +`define AL_EGR_P_CNG 95 +`define AL_MARK 94 + + +// Afara Link Object Format - Acknowledge +`define AL_ACK_SZ 21 +`define AL_A_COS 93 +`define AL_A_TYP_HI 92 +`define AL_A_TYP_LO 91 +`define AL_A_NACK 90 +`define AL_A_TAG_HI 89 +`define AL_A_TAG_LO 80 +`define AL_A_PORT_HI 79 +`define AL_A_PORT_LO 73 + + +// Afara Link Object Format - Request +`define AL_REQ_SZ 73 +`define AL_R_COS 72 +`define AL_R_TYP_HI 71 +`define AL_R_TYP_LO 70 +`define AL_R_SCR_HI 69 +`define AL_R_SCR_LO 67 +`define AL_R_TCR_HI 66 +`define AL_R_TCR_LO 64 +`define AL_R_TAG_HI 63 +`define AL_R_TAG_LO 54 +`define AL_R_PORT_HI 53 +`define AL_R_PORT_LO 47 +`define AL_R_LEN_HI 46 +`define AL_R_LEN_LO 40 +`define AL_R_ADD_HI 39 +`define AL_R_ADD_LO 0 + +// Afara Link Object Format - Message +`define AL_M_MQID_HI 2 +`define AL_M_MQID_LO 0 + +// Acknowledge Types +`define AL_ACK_NONE 2'b00 +`define AL_ACK_NPAY 2'b01 +`define AL_ACK_WPAY 2'b10 + +// Request Types +`define AL_REQ_NONE 2'b00 +`define AL_REQ_NPAY 2'b01 +`define AL_REQ_WPAY 2'b10 +`define AL_REQ_MSG 2'b11 + +// Afara Link Frame +`define AL_FRAME_SZ 144 + + +// +// UCB Packet Type +// =============== +// +`define UCB_READ_NACK 4'b0000 // ack/nack types +`define UCB_READ_ACK 4'b0001 +`define UCB_WRITE_ACK 4'b0010 +`define UCB_IFILL_ACK 4'b0011 +`define UCB_IFILL_NACK 4'b0111 + +`define UCB_READ_REQ 4'b0100 // req types +`define UCB_WRITE_REQ 4'b0101 +`define UCB_IFILL_REQ 4'b0110 + +`define UCB_INT 4'b1000 // plain interrupt +`define UCB_INT_VEC 4'b1100 // interrupt with vector +`define UCB_RESET_VEC 4'b1101 // reset with vector +`define UCB_IDLE_VEC 4'b1110 // idle with vector +`define UCB_RESUME_VEC 4'b1111 // resume with vector + + +// +// UCB Data Packet Format +// ====================== +// +`define UCB_NOPAY_PKT_WIDTH 64 // packet without payload +`define UCB_64PAY_PKT_WIDTH 128 // packet with 64 bit payload +`define UCB_128PAY_PKT_WIDTH 192 // packet with 128 bit payload + +`define UCB_DATA_EXT_HI 191 // (64) extended data +`define UCB_DATA_EXT_LO 128 +`define UCB_DATA_HI 127 // (64) data +`define UCB_DATA_LO 64 +`define UCB_RSV_HI 63 // (9) reserved bits +`define UCB_RSV_LO 55 +`define UCB_ADDR_HI 54 // (40) bit address +`define UCB_ADDR_LO 15 +`define UCB_SIZE_HI 14 // (3) request size +`define UCB_SIZE_LO 12 +`define UCB_BUF_HI 11 // (2) buffer ID +`define UCB_BUF_LO 10 +`define UCB_THR_HI 9 // (6) cpu/thread ID +`define UCB_THR_LO 4 +`define UCB_PKT_HI 3 // (4) packet type +`define UCB_PKT_LO 0 + +`define UCB_DATA_EXT_WIDTH 64 +`define UCB_DATA_WIDTH 64 +`define UCB_RSV_WIDTH 9 +`define UCB_ADDR_WIDTH 40 +`define UCB_SIZE_WIDTH 3 +`define UCB_BUFID_WIDTH 2 +`define UCB_THR_WIDTH 6 +`define UCB_PKT_WIDTH 4 + +// Size encoding for the UCB_SIZE_HI/LO field +// 000 - byte +// 001 - half-word +// 010 - word +// 011 - double-word +// 111 - quad-word +`define UCB_SIZE_1B 3'b000 +`define UCB_SIZE_2B 3'b001 +`define UCB_SIZE_4B 3'b010 +`define UCB_SIZE_8B 3'b011 +`define UCB_SIZE_16B 3'b111 + + +// +// UCB Interrupt Packet Format +// =========================== +// +`define UCB_INT_PKT_WIDTH 64 + +`define UCB_INT_RSV_HI 63 // (7) reserved bits +`define UCB_INT_RSV_LO 57 +`define UCB_INT_VEC_HI 56 // (6) interrupt vector +`define UCB_INT_VEC_LO 51 +`define UCB_INT_STAT_HI 50 // (32) interrupt status +`define UCB_INT_STAT_LO 19 +`define UCB_INT_DEV_HI 18 // (9) device ID +`define UCB_INT_DEV_LO 10 +//`define UCB_THR_HI 9 // (6) cpu/thread ID shared with +//`define UCB_THR_LO 4 data packet format +//`define UCB_PKT_HI 3 // (4) packet type shared with +//`define UCB_PKT_LO 0 // data packet format + +`define UCB_INT_RSV_WIDTH 7 +`define UCB_INT_VEC_WIDTH 6 +`define UCB_INT_STAT_WIDTH 32 +`define UCB_INT_DEV_WIDTH 9 + + +// +// FCRAM Bus Widths +// ================ +// +`define FCRAM_DQ_WIDTH 16 +`define FCRAM_DQS_WIDTH 2 +`define FCRAM_ADDR_WIDTH 15 +`define FCRAM_BA_WIDTH 2 + + +// +// ENET clock periods +// ================== +// +`define AXGRMII_CLK_PERIOD 6400 // 312.5MHz/2 +`define ENET_GMAC_CLK_PERIOD 8000 // 125MHz + + +// +// JBus Bridge defines +// ================= +// +`define SYS_UPA_CLK `SYS.upa_clk +`define SYS_J_CLK `SYS.j_clk +`define SYS_P_CLK `SYS.p_clk +`define SYS_G_CLK `SYS.g_clk +`define JP_TIMESCALE `timescale 1 ps / 1 ps +`define PCI_CLK_PERIOD 15152 // 66 MHz +`define UPA_RD_CLK_PERIOD 6666 // 150 MHz +`define UPA_REF_CLK_PERIOD 7576 // 132 MHz +`define ICHIP_CLK_PERIOD 30304 // 33 MHz + + +// +// PCI Device Address Configuration +// ================================ +// +`define PRIM_SLAVE1_MEM0_L 64'h0000000000000000 +`define PRIM_SLAVE1_MEM0_H 64'h000000003fff0000 +`define PRIM_SLAVE1_IO0_L 64'h0000000000000000 +`define PRIM_SLAVE1_IO0_H 64'h00000000002f0000 +`define PRIM_SLAVE1_JBUS_BASE 64'h000007ff00000000 + +`define PRIM_SLAVE2_MEM0_L 64'h0000000040000000 +`define PRIM_SLAVE2_MEM0_H 64'h00000000Dfffffff +`define PRIM_SLAVE2_IO0_L 64'h0000000000300000 +`define PRIM_SLAVE2_IO0_H 64'h00000000005fffff +`define PRIM_SLAVE2_JBUS_BASE 64'h000007ff40000000 + +`define PCIB_SLAVE1_MEM0_L 64'h0000000000000000 +`define PCIB_SLAVE1_MEM0_H 64'h000000003fff0000 +`define PCIB_SLAVE1_IO0_L 64'h0000000000000000 +`define PCIB_SLAVE1_IO0_H 64'h00000000002fffff +`define PCIB_SLAVE1_JBUS_BASE 64'h000007f780000000 + +`define PCIB_SLAVE2_MEM0_L 64'h0000000040000000 +`define PCIB_SLAVE2_MEM0_H 64'h000000007fffffff +`define PCIB_SLAVE2_IO0_L 64'h0000000000300000 +`define PCIB_SLAVE2_IO0_H 64'h00000000007fffff +`define PCIB_SLAVE2_JBUS_BASE 64'h000007f7c0000000 1.3 s1_core/hdl/rtl/sparc_core/include/sys_paths.h http://www.opencores.org/cvsweb.shtml/s1_core/hdl/rtl/sparc_core/include/sys_paths.h.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: sys_paths.h =================================================================== RCS file: sys_paths.h diff -N sys_paths.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sys_paths.h 26 Mar 2007 23:02:19 -0000 1.3 @@ -0,0 +1,50 @@ +/* +* ========== Copyright Header Begin ========================================== +* +* OpenSPARC T1 Processor File: sys_paths.h +* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +* +* The above named program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public +* License version 2 as published by the Free Software Foundation. +* +* The above named program is distributed in the hope that it will be +* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +* +* You should have received a copy of the GNU General Public +* License along with this work; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +* +* ========== Copyright Header End ============================================ +*/ +// -*- verilog -*- +//////////////////////////////////////////////////////////////////////// +/* +// +// Description: Global header file that contain definitions that +// are common/shared at the systme level +*/ +//////////////////////////////////////////////////////////////////////// + +// Here we add defines for all the blocks referenced in monitors. +// The absolute path would vary based on the verif model being built. + +// Global CIOP defines +`define RBC sys_top +`define RBC_CLK `RBC.jbus_gclk +`define CPU_CLK `RBC.cmp_gclk +`define CHIP_RST_L `RBC.jbus_grst_l +`define CHIP_RST ~`RBC.jbus_grst_l + +// BSC defines +`define BSC `RBC.iop.bsc +`define BSC_CTL `BSC.bsc_ctl +`define BSC_SFS `BSC_CTL.bsc_sfs +`define BSC_IOP `BSC.bsc_iop +`define BSC_EEPU `BSC_IOP.eepu_ioq + +// Environment defines +`define FAIL_FLAG sys_top.fail_flag 1.3 s1_core/hdl/rtl/sparc_core/include/tlu.h http://www.opencores.org/cvsweb.shtml/s1_core/hdl/rtl/sparc_core/include/tlu.h.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: tlu.h =================================================================== RCS file: tlu.h diff -N tlu.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ tlu.h 26 Mar 2007 23:02:19 -0000 1.3 @@ -0,0 +1,399 @@ +/* +* ========== Copyright Header Begin ========================================== +* +* OpenSPARC T1 Processor File: tlu.h +* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. +* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. +* +* The above named program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public +* License version 2 as published by the Free Software Foundation. +* +* The above named program is distributed in the hope that it will be +* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* General Public License for more details. +* +* You should have received a copy of the GNU General Public +* License along with this work; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. +* +* ========== Copyright Header End ============================================ +*/ +// ifu trap types +`define INST_ACC_EXC 9'h008 +`define INST_ACC_MMU_MS 9'h009 +`define INST_ACC_ERR 9'h00a +`define ILL_INST 9'h010 +`define PRIV_OPC 9'h011 +`define FP_DISABLED 9'h020 +`define DATA_ACC_EXC 9'h030 + +`define MRA_TSB_PS0_HI 155 +`define MRA_TSB_PS0_LO 108 +`define MRA_TSB_PS1_HI 107 +`define MRA_TSB_PS1_LO 60 +`define MRA_TACCESS_HI 59 +`define MRA_TACCESS_LO 12 +`define MRA_CTXTCFG_HI 11 +`define MRA_CTXTCFG_LO 6 +// +// modified for hypervisor support +// +`define TLU_THRD_NUM 4 +`define TLU_TT_LO 0 +`define TLU_TT_HI 8 +`define TLU_CWP_LO 9 +`define TLU_CWP_HI 11 +`define TLU_PSTATE_LO 12 +`define TLU_PSTATE_HI 19 +`define TLU_ASI_LO 20 +`define TLU_ASI_HI 27 +`define TLU_CCR_LO 28 +`define TLU_CCR_HI 35 +`define TLU_GL_LO 36 +`define TLU_GL_HI 37 +`define TLU_NPC_LO 38 +`define TLU_NPC_HI 84 +`define TLU_PC_LO 85 +`define TLU_PC_HI 131 +`define TLU_HTSTATE_LO 132 +`define TLU_HTSTATE_HI 135 +`define TLU_RD_NPC_HI 83 +`define TLU_RD_PC_LO 84 +`define TLU_RD_PC_HI 129 +`define TLU_RD_HTSTATE_LO 130 +`define TLU_RD_HTSTATE_HI 133 +// +`define TSA_PSTATE_VRANGE1_LO 12 +`define TSA_PSTATE_VRANGE1_HI 15 +// modified due to bug 2588 +// `define TSA_PSTATE_VRANGE2_LO 16 +`define TSA_PSTATE_VRANGE2_LO 18 +`define TSA_PSTATE_VRANGE2_HI 19 +// +`define TLU_TSA_WIDTH 136 +`define TLU_TDP_TSA_WIDTH 134 +`define TSA_HTSTATE_WIDTH 4 +`define TSA_GLOBAL_WIDTH 2 +`define TSA_CCR_WIDTH 8 +`define TSA_ASI_WIDTH 8 +`define TSA_PSTATE_WIDTH 8 +`define TSA_CWP_WIDTH 3 +`define TSA_TTYPE_WIDTH 9 +`define TLU_GLOBAL_WIDTH 4 +`define TLU_HPSTATE_WIDTH 5 +// +// added due to Niagara SRAMs methodology +// The following defines have been replaced due +// the memory macro replacement from: +// bw_r_rf32x144 -> 2x bw_r_rf32x80 +/* +`define TSA_MEM_WIDTH 144 +`define TSA_HTSTATE_HI 142 // 3 bits +`define TSA_HTSTATE_LO 140 +`define TSA_TPC_HI 138 // 47 bits +`define TSA_TPC_LO 92 +`define TSA_TNPC_HI 90 // 47 bits +`define TSA_TNPC_LO 44 +`define TSA_TSTATE_HI 40 // 29 bits +`define TSA_TSTATE_LO 12 +`define TSA_TTYPE_HI 8 // 9 bits +`define TSA_TTYPE_LO 0 +`define TSA_MEM_CWP_LO 12 +`define TSA_MEM_CWP_HI 14 +`define TSA_MEM_PSTATE_LO 15 +`define TSA_MEM_PSTATE_HI 22 +`define TSA_MEM_ASI_LO 23 +`define TSA_MEM_ASI_HI 30 +`define TSA_MEM_CCR_LO 31 +`define TSA_MEM_CCR_HI 38 +`define TSA_MEM_GL_LO 39 +`define TSA_MEM_GL_HI 40 +*/ +`define TSA_MEM_WIDTH 80 +`define TSA1_HTSTATE_HI 63 // 4 bits +`define TSA1_HTSTATE_LO 60 +`define TSA1_TNPC_HI 58 // 47 bits +`define TSA1_TNPC_LO 12 +`define TSA1_TTYPE_HI 8 // 9 bits +`define TSA1_TTYPE_LO 0 +`define TSA0_TPC_HI 78 // 47 bits +`define TSA0_TPC_LO 32 +`define TSA0_TSTATE_HI 28 // 29 bits +`define TSA0_TSTATE_LO 0 +// +`define TSA0_MEM_CWP_LO 0 +`define TSA0_MEM_CWP_HI 2 +`define TSA0_MEM_PSTATE_LO 3 +`define TSA0_MEM_PSTATE_HI 10 +`define TSA0_MEM_ASI_LO 11 +`define TSA0_MEM_ASI_HI 18 +`define TSA0_MEM_CCR_LO 19 +`define TSA0_MEM_CCR_HI 26 +`define TSA0_MEM_GL_LO 27 +`define TSA0_MEM_GL_HI 28 + +// HPSTATE position definitions within wsr +`define WSR_HPSTATE_ENB 11 +`define WSR_HPSTATE_IBE 10 +`define WSR_HPSTATE_RED 5 +`define WSR_HPSTATE_PRIV 2 +`define WSR_HPSTATE_TLZ 0 + +// TSTATE postition definitions within wsr +`define WSR_TSTATE_GL_HI 41 // 2b +`define WSR_TSTATE_GL_LO 40 +`define WSR_TSTATE_CCR_HI 39 // 8b +`define WSR_TSTATE_CCR_LO 32 +`define WSR_TSTATE_ASI_HI 31 // 8b +`define WSR_TSTATE_ASI_LO 24 +`define WSR_TSTATE_PS2_HI 17 // 4b +// modified due to bug 2588 +`define WSR_TSTATE_PS2_LO 16 +`define WSR_TSTATE_PS1_HI 12 // 4b +// added for bug 2584 +`define WSR_TSTATE_PS_PRIV 10 // 4b +`define WSR_TSTATE_PS1_LO 9 +`define WSR_TSTATE_CWP_HI 2 // 3b +`define WSR_TSTATE_CWP_LO 0 +// +`define WSR_TSTATE_WIDTH 29 +`define RDSR_TSTATE_WIDTH 48 +`define RDSR_HPSTATE_WIDTH 12 +`define TLU_ASR_DATA_WIDTH 64 +`define TLU_ASR_ADDR_WIDTH 7 + +`define SFTINT_WIDTH 17 +// +// tick_cmp and stick_cmp definitions +`define TICKCMP_RANGE_HI 60 +`define TICKCMP_RANGE_LO 0 +`define TICKCMP_INTDIS 63 +`define SFTINT_TICK_CMP 0 +`define SFTINT_STICK_CMP 16 +// +// PIB WRAP +`define SFTINT_PIB_WRAP 15 +`define PIB_OVERFLOW_TTYPE 7'h4f + +// HPSTATE postition definitions +`define HPSTATE_IBE 4 +`define HPSTATE_ENB 3 +`define HPSTATE_RED 2 +`define HPSTATE_PRIV 1 +`define HPSTATE_TLZ 0 + +// HTBA definitions +`define TLU_HTBA_WIDTH 34 // supported physical width +`define TLU_HTBA_HI 47 +`define TLU_HTBA_LO 14 + +// TBA definitions +`define TLU_TBA_WIDTH 33 // supported physical width +`define TLU_TBA_HI 47 +`define TLU_TBA_LO 15 + +`define TPC 5'h0 +`define TNPC 5'h1 +`define TSTATE 5'h2 +`define TT 5'h3 +`define TICK 5'h4 +`define TBA 5'h5 +`define PSTATE 5'h6 +`define TL 5'h7 +`define PIL 5'h8 +`define HPSTATE 5'h0 +`define HTSTATE 5'h1 +`define HINTP 5'h3 +`define HTBA 5'h5 +`define HTICKCMP 5'h1f +`define STICKCMP 5'h19 +`define TICKCMP 5'h17 +// +// added for the hypervisor support +`define PSTATE_VRANGE1_LO 1 +`define PSTATE_VRANGE1_HI 4 +// modified due to bug 2588 +`define PSTATE_VRANGE2_LO 8 +`define PSTATE_VRANGE2_HI 9 +`define PSTATE_TRUE_WIDTH 12 + +`define PSTATE_AG 0 +`define PSTATE_IE 1 +`define PSTATE_PRIV 2 +`define PSTATE_AM 3 +`define PSTATE_PEF 4 +`define PSTATE_RED 5 +`define PSTATE_MM_LO 6 +`define PSTATE_MM_HI 7 +`define PSTATE_TLE 8 +`define PSTATE_CLE 9 +`define PSTATE_MG 10 +`define PSTATE_IG 11 +// +// compressed PSTATE WSR definitions +`define WSR_PSTATE_VRANGE1_LO 0 +`define WSR_PSTATE_VR_PRIV 1 +`define WSR_PSTATE_VRANGE1_HI 3 +`define WSR_PSTATE_VRANGE2_LO 4 +`define WSR_PSTATE_VRANGE2_HI 5 +`define WSR_PSTATE_VR_WIDTH 6 + +`define MAXTL 3'b110 +`define MAXTL_LESSONE 3'b101 +`define MAXSTL 3'b010 +`define MAXSTL_TL 3'b010 // Saturation point for GL and TL (supervisor) +`define MAXSTL_GL 2'b10 // Saturation point for GL and TL (supervisor) +`define MAXGL 4'b0011 // Saturation point for GL (hypervisor) +`define MAXGL_GL 2'b11 // Saturation point for GL (hypervisor) +// +// ASI_QUEUE for hypervisor +// Queues are: CPU_MONODO +// DEV_MONODO +// RESUMABLE_ERROR +// NON_RESUMABLE_ERROR +// +`define ASI_VA_WIDTH 48 +`define TLU_ASI_QUE_HI 13 +`define TLU_ASI_QUE_LO 6 +`define TLU_ASI_QUE_WIDTH 8 +`define TLU_ASI_VA_WIDTH 10 +`define TLU_ASI_STATE_WIDTH 8 + +// for address range checking +`define TLU_ASI_QUE_VA_HI 9 +`define TLU_ASI_QUE_VA_LO 3 + +`define TLU_ASI_QUE_ASI 8'h25 +`define CPU_MONDO_HEAD 10'h3c0 +`define CPU_MONDO_TAIL 10'h3c8 +`define DEV_MONDO_HEAD 10'h3d0 +`define DEV_MONDO_TAIL 10'h3d8 +`define RESUM_ERR_HEAD 10'h3e0 +`define RESUM_ERR_TAIL 10'h3e8 +`define NRESUM_ERR_HEAD 10'h3f0 +`define NRESUM_ERR_TAIL 10'h3f8 +`define CPU_MONDO_TRAP 7'h7c // only 7 bits are defined; upper two are 2'b00 +`define DEV_MONDO_TRAP 7'h7d // only 7 bits are defined; upper two are 2'b00 +`define TLZ_TRAP 7'h5f // only 7 bits are defined; upper two are 2'b00 +`define HWINT_INT 7'h60 // only 7 bits are defined; upper two are 2'b00 +// +// Niagara scratch-pads +// VA address of 0x20 and 0x28 are exclusive to hypervisor +// +`define TLU_SCPD_DATA_WIDTH 64 +`define SCPD_RW_ADDR_WIDTH 5 +`define SCPD_ASI_VA_ADDR_WIDTH 3 + +`define PRI_SCPD_ASI_STATE 8'h20 +`define SCPD_ASI_VA_ADDR_LO 10'h000 +`define SCPD_ASI_VA_ADDR_HI 10'h038 +// +// range checking +`define TLU_ASI_SCPD_VA_HI 5 +`define TLU_ASI_SCPD_VA_LO 3 + +`define HPRI_SCPD_ASI_STATE 8'h4f +`define HSCPD_ASI_VA_ADDR_LO 3'h4 +`define HSCPD_ASI_VA_ADDR_HI 3'h5 + +// PIB related definitions +// Bit definition for events +`define PIB_INSTR_COUNT 3'bxxx +`define PIB_SB_FULL_CNT 3'b000 +`define PIB_FP_INST_CNT 3'b001 +`define PIB_IC_MISS_CNT 3'b010 +`define PIB_DC_MISS_CNT 3'b011 +`define PIB_ITLB_MISS_CNT 3'b100 +`define PIB_DTLB_MISS_CNT 3'b101 +`define PIB_L2_IMISS_CNT 3'b110 +`define PIB_L2_DMISS_CNT 3'b111 +// +// PIB related definitions +// PCR and PIC address definitions +`define PCR_ASR_ADDR 7'b0010000 +`define PIC_ASR_PRIV_ADDR 7'b0110001 +`define PIC_ASR_NPRIV_ADDR 7'b0010001 +// +// PCR bit definitions +`define WSR_PCR_PRIV 0 // PIC privilege +`define WSR_PCR_ST 1 // supervior trace +`define WSR_PCR_UT 2 // user trace +`define WSR_PCR_SL_LO 4 // PICL event mask +`define WSR_PCR_SL_HI 6 // +`define WSR_PCR_CL_OVF 8 // +`define WSR_PCR_CH_OVF 9 // +// +`define PIB_PCR_WIDTH 8 +`define PIB_PCR_PRIV 0 // PIC privilege +`define PIB_PCR_ST 1 // privilege event trace +`define PIB_PCR_UT 2 // user event trace +`define PIB_PCR_SL_LO 3 // PICL event encode +`define PIB_PCR_SL_HI 5 // +`define PIB_PCR_CL_OVF 6 // +`define PIB_PCR_CH_OVF 7 // + +// PIC definitions +`define PIB_PIC_FULL_WIDTH 64 +`define PIB_PIC_CNT_WIDTH 33 +`define PIB_PIC_CNT_WRAP 32 +`define PIB_PICH_CNT_HI 63 +`define PIB_PICH_CNT_LO 32 +`define PIB_PICL_CNT_HI 31 +`define PIB_PICL_CNT_LO 0 +`define PIB_EVQ_CNT_WIDTH 3 +// PIC mask bit position definitions +`define PICL_MASK_WIDTH 8 +`define PICL_MASK_SB_FULL 0 +`define PICL_MASK_FP_INST 1 +`define PICL_MASK_IC_MISS 2 +`define PICL_MASK_DC_MISS 3 +`define PICL_MASK_ITLB_MISS 4 +`define PICL_MASK_DTLB_MISS 5 +`define PICL_MASK_L2_IMISS 6 +`define PICL_MASK_L2_DMISS 7 + +// added define from sparc_tlu_int.v +`define INT_THR_HI 12 +`define INT_VEC_HI 5 +`define INT_VEC_LO 0 +`define INT_THR_HI 12 +`define INT_THR_LO 8 +`define INT_TYPE_HI 17 +`define INT_TYPE_LO 16 +`define TLU_INRR_ASI 8'h72 +`define TLU_INDR_ASI 8'h73 +`define TLU_INVR_ASI 8'h74 +// +// shadow scan related definitions +`define TLU_SSCAN_WIDTH 63 +// modified due to logic redistribution +// `define TCL_SSCAN_WIDTH 12 +`define TCL_SSCAN_WIDTH 3 +`define MISCTL_SSCAN_WIDTH 9 +`define TDP_SSCAN_WIDTH 51 +`define TDP_SSCAN_LO 0 +`define TDP_SSCAN_HI 50 +// `define TCL_SSCAN_LO 51 +`define MISCTL_SSCAN_LO 51 +`define MISCTL_SSCAN_HI 59 +`define TCL_SSCAN_LO 60 +`define TCL_SSCAN_HI 62 +// +// position definitions - TDP +`define TDP_SSCAN_PC_LO 0 +`define TDP_SSCAN_PC_HI 45 +`define TDP_SSCAN_PS_IE 46 +`define TDP_SSCAN_PS_PRIV 47 +`define TDP_SSCAN_HPS_LO 48 +`define TDP_SSCAN_HPS_HI 50 +// +// position definitions - TCL +`define TCL_SSCAN_TT_LO 0 +`define TCL_SSCAN_TT_HI 8 +`define TCL_SSCAN_TL_LO 9 +`define TCL_SSCAN_TL_HI 11 +// +// To speedup POR for verification purposes +`define RSTVADDR_BASE 34'h3_ffff_c000 1.1 s1_core/hdl/rtl/sparc_core/include/xst_defines.h http://www.opencores.org/cvsweb.shtml/s1_core/hdl/rtl/sparc_core/include/xst_defines.h?rev=1.1&content-type=text/x-cvsweb-markup Index: xst_defines.h =================================================================== `define FPGA_SYN `define FPGA_SYN_NO_SPU `define FPGA_SYN_1THREAD `define NO_SCAN `define FPGA_SYN_CLK `define FPGA_SYN_CLK_DFF `define FPGA_SYN_CLK_EN

     
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