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From: cvs at opencores.org<cvs@o...>
Date: Sun Mar 25 00:36:30 CET 2007
Subject: [cvs-checkins] MODIFIED: graphiti ...

Date: 00/07/03 25:00:36

Added: graphiti/xilinx clk.vhd csr.vhd dcm1.vhd dds.vhd dds_sinus.vhd delay.vhd license.txt miniga.ise miniga.ucf miniga.vhd myfir.vhd pal.vhd paltimer.vhd rgb2yuv.vhd spi.vhd Log: xilinx vhdl files added Revision Changes Path 1.1 graphiti/xilinx/clk.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/clk.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: clk.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clk is port ( clkin : in std_logic; reset : in std_logic; clk60M : out std_logic; clk45M : out std_logic; clk15M : out std_logic; pixclk : out std_logic; sync : out std_logic ); end clk; architecture behaviour of clk is COMPONENT dcm1 PORT( CLKIN_IN : IN std_logic; RST_IN : IN std_logic; CLKFX_OUT : OUT std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic; LOCKED_OUT : OUT std_logic ); END COMPONENT; signal locked: std_logic; signal pllreset : std_logic; signal pllclk180M : std_logic; begin Inst_dcm1: dcm1 PORT MAP( CLKIN_IN => clkin, RST_IN => pllreset, CLKFX_OUT => pllclk180M, CLKIN_IBUFG_OUT => open, CLK0_OUT => open, LOCKED_OUT => locked ); pllreset <= not reset; -- statemachine, weil counter zu langsam sind ... process (pllclk180M, reset, locked) variable state : integer := 0; begin if reset='0' or locked='0' then state := 0; clk60M <= '0'; clk15M <= '0'; clk45M <= '0'; sync <= '0'; pixclk <= '0'; elsif pllclk180M'event and pllclk180M='1' then case state is when 0 => clk15M <= '1'; clk45M <= '1'; clk60M <= '1'; state := 1; when 1 => clk60M <= '0'; state := 2; when 2 => clk45M <= '0'; pixclk <= '1'; state := 3; when 3 => clk60M <= '1'; pixclk <= '0'; state := 4; when 4 => clk60M <= '0'; clk45M <= '1'; state := 5; when 5 => state := 6; when 6 => pixclk <= '1'; clk60M <= '1'; clk45M <= '0'; clk15M <= '0'; state := 7; when 7 => pixclk <= '0'; clk60M <= '0'; state := 8; when 8 => sync <= '1'; clk45M <= '1'; state := 9; when 9 => clk60M <= '1'; state := 10; when 10 => pixclk <= '1'; clk60M <= '0'; clk45M <= '0'; state := 11; when 11 => pixclk <= '0'; sync <= '0'; state := 0; when others => state := 0; end case; end if; end process; end architecture; 1.1 graphiti/xilinx/csr.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/csr.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: csr.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author ------------------------------------------------------------------------------- -- Cycle-Shared-RAM -- clk4x = 60MHz -- Effektiv ergeben sich 30MB/sec pro Bus library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity csr is generic ( ADR_WIDTH : integer := 19; -- A0 bis A18 DATA_WIDTH : integer := 16 -- D0 bis D15 ); port ( clk4x : in std_logic; reset : in std_logic; clk : in std_logic; sync : in std_logic; -- ram ram_adr : out std_logic_vector ((ADR_WIDTH-1) downto 0); ram_data: inout std_logic_vector ((DATA_WIDTH-1) downto 0); ram_rd : out std_logic; ram_wr : out std_logic; ram_cs : out std_logic; adr1 : in std_logic_vector ((ADR_WIDTH-1) downto 0); data1_in : in std_logic_vector ((DATA_WIDTH-1) downto 0); data1_out : out std_logic_vector ((DATA_WIDTH-1) downto 0); rd1 : in std_logic; wr1 : in std_logic; adr2 : in std_logic_vector ((ADR_WIDTH-1) downto 0); data2_in : in std_logic_vector ((DATA_WIDTH-1) downto 0); data2_out : out std_logic_vector ((DATA_WIDTH-1) downto 0); rd2 : in std_logic; wr2 : in std_logic ); end csr; architecture behaviour of csr is begin -- immer 16bit zugriffe! process (clk4x, reset) variable state : integer := -1; begin if reset='0' then ram_data <= (others => 'Z'); ram_rd <= '1'; ram_wr <= '1'; ram_adr <= (others => '0'); data1_out <= (others => '0'); data2_out <= (others => '0'); ram_cs <= '1'; state := 4; elsif clk4x'event and clk4x='0' then case state is when 0 => if rd2='0' and wr2='1' then data2_out <= ram_data; end if; ram_rd <= '1'; ram_wr <= '1'; ram_adr <= adr1; ram_cs <= '0'; -- auf Datenbussen rausschreiben if wr1='0' and rd1='1' then ram_data <= data1_in; else ram_data <= (others => 'Z'); end if; state := 1; when 1 => -- beim lesen nur vom selektierten SRAM lesen ram_rd <= rd1; ram_wr <= wr1; state := 2; when 2 => if rd2='0' and wr2='1' then data1_out <= ram_data; end if; ram_rd <= '1'; ram_wr <= '1'; ram_adr <= adr2; ram_cs <= '0'; -- auf Datenbussen rausschreiben if wr2='0' and rd2='1' then ram_data <= data2_in; else ram_data <= (others => 'Z'); end if; state := 3; when 3 => ram_rd <= rd2; ram_wr <= wr2; state := 0; -- statemachine mit dem 15MHz clock synchronisieren when 4 => if sync='1' then state := 5; end if; when 5 => state := 6; when 6 => state := 0; when 7 => state := 0; when others => state:=0; end case; end if; end process; end architecture; 1.1 graphiti/xilinx/dcm1.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/dcm1.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: dcm1.vhd =================================================================== -------------------------------------------------------------------------------- -- Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 8.1i -- \ \ Application : xaw2vhdl -- / / Filename : dcm1.vhd -- /___/ /\ Timestamp : 09/05/2006 19:50:18 -- \ \ / \ -- \___\/\___\ -- --Command: xaw2vhdl-intstyle C:/Xilinx/graphiti/dcm1.xaw -st dcm1.vhd --Design Name: dcm1 --Device: xc3s250e-5tq144 -- -- Module dcm1 -- Generated by Xilinx Architecture Wizard -- Written for synthesis tool: XST library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL; -- synopsys translate_on entity dcm1 is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKFX_OUT : out std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic); end dcm1; architecture BEHAVIORAL of dcm1 is signal CLKFB_IN : std_logic; signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal CLK0_BUF : std_logic; signal GND1 : std_logic; component BUFG port ( I : in std_logic; O : out std_logic); end component; component IBUFG port ( I : in std_logic; O : out std_logic); end component; -- Period Jitter (unit interval) for block DCM_INST = 0.00 UI -- Period Jitter (Peak-to-Peak) for block DCM_INST = 0.03 ns component DCM generic( CLK_FEEDBACK : string := "1X"; CLKDV_DIVIDE : real := 2.000000; CLKFX_DIVIDE : integer := 1; CLKFX_MULTIPLY : integer := 4; CLKIN_DIVIDE_BY_2 : boolean := FALSE; CLKIN_PERIOD : real := 10.000000; CLKOUT_PHASE_SHIFT : string := "NONE"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DUTY_CYCLE_CORRECTION : boolean := TRUE; FACTORY_JF : bit_vector := x"C080"; PHASE_SHIFT : integer := 0; STARTUP_WAIT : boolean := FALSE; DSS_MODE : string := "NONE"); port ( CLKIN : in std_logic; CLKFB : in std_logic; RST : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSCLK : in std_logic; DSSEN : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLKDV : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; STATUS : out std_logic_vector (7 downto 0); LOCKED : out std_logic; PSDONE : out std_logic); end component; begin GND1 <= '0'; CLKIN_IBUFG_OUT <= CLKIN_IBUFG; CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); CLKIN_IBUFG_INST : IBUFG port map (I=>CLKIN_IN, O=>CLKIN_IBUFG); CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_INST : DCM generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.000000, CLKFX_DIVIDE => 1, CLKFX_MULTIPLY => 4, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 22.222200, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IBUFG, DSSEN=>GND1, PSCLK=>GND1, PSEN=>GND1, PSINCDEC=>GND1, RST=>RST_IN, CLKDV=>open, CLKFX=>CLKFX_BUF, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>LOCKED_OUT, PSDONE=>open, STATUS=>open); end BEHAVIORAL; 1.1 graphiti/xilinx/dds.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/dds.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: dds.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dds is Port ( clk : in std_logic; reset : in std_logic; phase : in std_logic_vector (1 downto 0); addi : out std_logic_vector (8 downto 0); data : out std_logic_vector (15 downto 0)); end dds; architecture Behavioral of dds is component dds_sinus Port ( clk : in std_logic; reset : in std_logic; adr : in std_logic_vector (6 downto 0); output1 : out std_logic_vector (15 downto 0)); end component; signal adr : std_logic_vector (6 downto 0); signal output : std_logic_vector (15 downto 0); begin I_O: dds_sinus port map ( clk => clk, reset => reset, adr => adr, output1 => output); process (clk, reset) variable step48 : unsigned (63 downto 0) := X"1938ECE0531174F2"; variable ctr_48 : unsigned (63 downto 0) := X"FFC0000000000000"; variable ctr90_48 : unsigned (63 downto 0):= X"3FC0000000000000"; variable ctr135_48 : unsigned (63 downto 0):= X"5FC0000000000000"; variable ctr225_48 : unsigned (63 downto 0):= X"9FC0000000000000"; variable curctr : unsigned (8 downto 0); variable abschnittu : unsigned (1 downto 0); variable indexu : unsigned (6 downto 0); begin if reset='0' then ctr_48 := X"FFC0000000000000"; ctr90_48 := X"3FC0000000000000"; ctr135_48 := X"5FC0000000000000"; ctr225_48 := X"9FC0000000000000"; data <= (others => '0'); elsif clk'event and clk='1' then ctr_48 := ctr_48 + step48; ctr90_48 := ctr90_48 + step48; ctr135_48 := ctr135_48 + step48; ctr225_48 := ctr225_48 + step48; case phase is when "00" => curctr := ctr_48 (63 downto 55); when "01" => curctr := ctr90_48 (63 downto 55); when "10" => curctr := ctr135_48 (63 downto 55); when "11" => curctr := ctr225_48 (63 downto 55); when others => curctr := (others=>'0'); end case; addi <= std_logic_vector(curctr);--(others => '0');--conv_std_logic_vector(curctr,9); indexu := curctr (6 downto 0); -- index für die tabelle case abschnittu(1) is when '1' => data <= conv_std_logic_vector(-signed(output),16); when '0' => data <= conv_std_logic_vector(signed(output),16); when others => data <= (others=>'0'); end case; abschnittu := curctr (8 downto 7); case abschnittu(0) is when '0' => adr <= conv_std_logic_vector(indexu,7); when '1' => adr <= conv_std_logic_vector(127-indexu,7); when others => adr <= (others=>'0'); end case; end if; end process; end Behavioral; 1.1 graphiti/xilinx/dds_sinus.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/dds_sinus.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: dds_sinus.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dds_sinus is Port ( clk : in std_logic; reset : in std_logic; adr : in std_logic_vector (6 downto 0); output1 : out std_logic_vector (15 downto 0)); end dds_sinus; architecture Behavioral of dds_sinus is begin process (adr) begin case adr is when "0000000" => output1 <= "0000000011001001"; -- 0.0061 when "0000001" => output1 <= "0000001001011011"; -- 0.0184 when "0000010" => output1 <= "0000001111101101"; -- 0.0307 when "0000011" => output1 <= "0000010101111110"; -- 0.0430 when "0000100" => output1 <= "0000011100010000"; -- 0.0552 when "0000101" => output1 <= "0000100010100001"; -- 0.0675 when "0000110" => output1 <= "0000101000110010"; -- 0.0798 when "0000111" => output1 <= "0000101111000011"; -- 0.0920 when "0001000" => output1 <= "0000110101010011"; -- 0.1043 when "0001001" => output1 <= "0000111011100011"; -- 0.1166 when "0001010" => output1 <= "0001000001110010"; -- 0.1289 when "0001011" => output1 <= "0001001000000000"; -- 0.1411 when "0001100" => output1 <= "0001001110001110"; -- 0.1534 when "0001101" => output1 <= "0001010100011011"; -- 0.1657 when "0001110" => output1 <= "0001011010100111"; -- 0.1779 when "0001111" => output1 <= "0001100000110011"; -- 0.1902 when "0010000" => output1 <= "0001100110111101"; -- 0.2025 when "0010001" => output1 <= "0001101101000110"; -- 0.2148 when "0010010" => output1 <= "0001110011001111"; -- 0.2270 when "0010011" => output1 <= "0001111001010110"; -- 0.2393 when "0010100" => output1 <= "0001111111011100"; -- 0.2516 when "0010101" => output1 <= "0010000101100001"; -- 0.2638 when "0010110" => output1 <= "0010001011100100"; -- 0.2761 when "0010111" => output1 <= "0010010001100111"; -- 0.2884 when "0011000" => output1 <= "0010010111100111"; -- 0.3007 when "0011001" => output1 <= "0010011101100111"; -- 0.3129 when "0011010" => output1 <= "0010100011100101"; -- 0.3252 when "0011011" => output1 <= "0010101001100001"; -- 0.3375 when "0011100" => output1 <= "0010101111011011"; -- 0.3497 when "0011101" => output1 <= "0010110101010100"; -- 0.3620 when "0011110" => output1 <= "0010111011001100"; -- 0.3743 when "0011111" => output1 <= "0011000001000001"; -- 0.3866 when "0100000" => output1 <= "0011000110110100"; -- 0.3988 when "0100001" => output1 <= "0011001100100110"; -- 0.4111 when "0100010" => output1 <= "0011010010010110"; -- 0.4234 when "0100011" => output1 <= "0011011000000011"; -- 0.4357 when "0100100" => output1 <= "0011011101101111"; -- 0.4479 when "0100101" => output1 <= "0011100011011000"; -- 0.4602 when "0100110" => output1 <= "0011101000111111"; -- 0.4725 when "0100111" => output1 <= "0011101110100100"; -- 0.4847 when "0101000" => output1 <= "0011110100000111"; -- 0.4970 when "0101001" => output1 <= "0011111001100111"; -- 0.5093 when "0101010" => output1 <= "0011111111000101"; -- 0.5216 when "0101011" => output1 <= "0100000100100000"; -- 0.5338 when "0101100" => output1 <= "0100001001111001"; -- 0.5461 when "0101101" => output1 <= "0100001111010000"; -- 0.5584 when "0101110" => output1 <= "0100010100100011"; -- 0.5706 when "0101111" => output1 <= "0100011001110100"; -- 0.5829 when "0110000" => output1 <= "0100011111000011"; -- 0.5952 when "0110001" => output1 <= "0100100100001110"; -- 0.6075 when "0110010" => output1 <= "0100101001010111"; -- 0.6197 when "0110011" => output1 <= "0100101110011101"; -- 0.6320 when "0110100" => output1 <= "0100110011100000"; -- 0.6443 when "0110101" => output1 <= "0100111000100000"; -- 0.6565 when "0110110" => output1 <= "0100111101011101"; -- 0.6688 when "0110111" => output1 <= "0101000010010111"; -- 0.6811 when "0111000" => output1 <= "0101000111001110"; -- 0.6934 when "0111001" => output1 <= "0101001100000001"; -- 0.7056 when "0111010" => output1 <= "0101010000110010"; -- 0.7179 when "0111011" => output1 <= "0101010101011111"; -- 0.7302 when "0111100" => output1 <= "0101011010001001"; -- 0.7424 when "0111101" => output1 <= "0101011110110000"; -- 0.7547 when "0111110" => output1 <= "0101100011010011"; -- 0.7670 when "0111111" => output1 <= "0101100111110011"; -- 0.7793 when "1000000" => output1 <= "0101101100001111"; -- 0.7915 when "1000001" => output1 <= "0101110000101000"; -- 0.8038 when "1000010" => output1 <= "0101110100111101"; -- 0.8161 when "1000011" => output1 <= "0101111001001111"; -- 0.8283 when "1000100" => output1 <= "0101111101011101"; -- 0.8406 when "1000101" => output1 <= "0110000001100111"; -- 0.8529 when "1000110" => output1 <= "0110000101101110"; -- 0.8652 when "1000111" => output1 <= "0110001001110001"; -- 0.8774 when "1001000" => output1 <= "0110001101110000"; -- 0.8897 when "1001001" => output1 <= "0110010001101011"; -- 0.9020 when "1001010" => output1 <= "0110010101100010"; -- 0.9143 when "1001011" => output1 <= "0110011001010110"; -- 0.9265 when "1001100" => output1 <= "0110011101000101"; -- 0.9388 when "1001101" => output1 <= "0110100000110001"; -- 0.9511 when "1001110" => output1 <= "0110100100011001"; -- 0.9633 when "1001111" => output1 <= "0110100111111100"; -- 0.9756 when "1010000" => output1 <= "0110101011011011"; -- 0.9879 when "1010001" => output1 <= "0110101110110111"; -- 1.0002 when "1010010" => output1 <= "0110110010001110"; -- 1.0124 when "1010011" => output1 <= "0110110101100001"; -- 1.0247 when "1010100" => output1 <= "0110111000110000"; -- 1.0370 when "1010101" => output1 <= "0110111011111010"; -- 1.0492 when "1010110" => output1 <= "0110111111000000"; -- 1.0615 when "1010111" => output1 <= "0111000010000010"; -- 1.0738 when "1011000" => output1 <= "0111000101000000"; -- 1.0861 when "1011001" => output1 <= "0111000111111001"; -- 1.0983 when "1011010" => output1 <= "0111001010101110"; -- 1.1106 when "1011011" => output1 <= "0111001101011110"; -- 1.1229 when "1011100" => output1 <= "0111010000001010"; -- 1.1351 when "1011101" => output1 <= "0111010010110001"; -- 1.1474 when "1011110" => output1 <= "0111010101010100"; -- 1.1597 when "1011111" => output1 <= "0111010111110011"; -- 1.1720 when "1100000" => output1 <= "0111011010001101"; -- 1.1842 when "1100001" => output1 <= "0111011100100010"; -- 1.1965 when "1100010" => output1 <= "0111011110110011"; -- 1.2088 when "1100011" => output1 <= "0111100000111111"; -- 1.2210 when "1100100" => output1 <= "0111100011000110"; -- 1.2333 when "1100101" => output1 <= "0111100101001001"; -- 1.2456 when "1100110" => output1 <= "0111100111000111"; -- 1.2579 when "1100111" => output1 <= "0111101001000001"; -- 1.2701 when "1101000" => output1 <= "0111101010110101"; -- 1.2824 when "1101001" => output1 <= "0111101100100101"; -- 1.2947 when "1101010" => output1 <= "0111101110010001"; -- 1.3070 when "1101011" => output1 <= "0111101111110111"; -- 1.3192 when "1101100" => output1 <= "0111110001011001"; -- 1.3315 when "1101101" => output1 <= "0111110010110110"; -- 1.3438 when "1101110" => output1 <= "0111110100001110"; -- 1.3560 when "1101111" => output1 <= "0111110101100001"; -- 1.3683 when "1110000" => output1 <= "0111110110110000"; -- 1.3806 when "1110001" => output1 <= "0111110111111001"; -- 1.3929 when "1110010" => output1 <= "0111111000111110"; -- 1.4051 when "1110011" => output1 <= "0111111001111110"; -- 1.4174 when "1110100" => output1 <= "0111111010111001"; -- 1.4297 when "1110101" => output1 <= "0111111011101111"; -- 1.4419 when "1110110" => output1 <= "0111111100100000"; -- 1.4542 when "1110111" => output1 <= "0111111101001100"; -- 1.4665 when "1111000" => output1 <= "0111111101110100"; -- 1.4788 when "1111001" => output1 <= "0111111110010110"; -- 1.4910 when "1111010" => output1 <= "0111111110110100"; -- 1.5033 when "1111011" => output1 <= "0111111111001101"; -- 1.5156 when "1111100" => output1 <= "0111111111100000"; -- 1.5278 when "1111101" => output1 <= "0111111111101111"; -- 1.5401 when "1111110" => output1 <= "0111111111111001"; -- 1.5524 when "1111111" => output1 <= "0111111111111110"; -- 1.5647 when others => output1 <= (others => '0'); end case; end process; end Behavioral; 1.1 graphiti/xilinx/delay.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/delay.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: delay.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author ------------------------------------------------------------------------------- -- delay -- for synchronizing u,v,y after FIR filter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity delay is generic ( TAPS : integer := 8 -- group-delay der FIR-Filter ist 500ns ); port ( clk : in std_logic; reset : in std_logic; input : in std_logic_vector(11 downto 0); output : out std_logic_vector(11 downto 0) ); end delay; architecture behaviour of delay is begin process (clk, reset) type tsr is array(0 to TAPS-1) of signed(11 downto 0); variable sr : tsr; begin if reset='0' then for I in 0 to TAPS-1 loop sr(I) := (others => '0'); end loop; output <= (others => '0'); elsif clk'event and clk='1' then -- Schieberegister for I in (TAPS-1) downto 1 loop sr(I):=sr(I-1); end loop; sr(0) := signed(input); output <= conv_std_logic_vector(sr(TAPS-1),12); end if; end process; end architecture; 1.1 graphiti/xilinx/license.txt http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/license.txt?rev=1.1&content-type=text/x-cvsweb-markup Index: license.txt =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- VHDL project files -- -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ ------------------------------------------------------------------------------- 1.1 graphiti/xilinx/miniga.ise http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/miniga.ise?rev=1.1&content-type=text/x-cvsweb-markup <<Binary file>> 1.1 graphiti/xilinx/miniga.ucf http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/miniga.ucf?rev=1.1&content-type=text/x-cvsweb-markup Index: miniga.ucf =================================================================== NET "I0/clk15M1" TNM_NET = "I0/clk15M1"; TIMESPEC "TS_I0_clk15M1" = PERIOD "I0/clk15M1" 66.666666 ns HIGH 50 %; NET "clkin" TNM_NET = "clkin"; TIMESPEC "TS_clkin" = PERIOD "clkin" 22.222222 ns HIGH 50 %; NET "I0/clk60M1" TNM_NET = "I0/clk60M1"; TIMESPEC "TS_I0_clk60M1" = PERIOD "I0/clk60M1" 16.666666 ns HIGH 50 %; NET "I0/clk45M1" TNM_NET = "I0/clk45M1"; TIMESPEC "TS_I0_clk45M1" = PERIOD "I0/clk45M1" 22.222222 ns HIGH 50 %; NET "spi_clk" TNM_NET = "spi_clk"; TIMESPEC "TS_spi_clk" = PERIOD "spi_clk" 50 ns HIGH 50 %; NET "clkin" LOC = "P127"; NET "pixelclock" LOC = "P128"; NET "digitalvideo<0>" LOC = "P108"; NET "digitalvideo<1>" LOC = "P107"; NET "digitalvideo<2>" LOC = "P112"; NET "digitalvideo<3>" LOC = "P113"; NET "digitalvideo<4>" LOC = "P116"; NET "digitalvideo<5>" LOC = "P118"; NET "digitalvideo<6>" LOC = "P119"; NET "digitalvideo<7>" LOC = "P122"; NET "digitalvideo<8>" LOC = "P123"; NET "digitalvideo<9>" LOC = "P129"; NET "reset" LOC = "P105"; NET "spi_ss" LOC = "P102"; NET "spi_clk" LOC = "P125"; NET "spi_data" LOC = "P104"; NET "spi_cd" LOC = "P103"; NET "ram_adr<0>" LOC = "P77"; NET "ram_adr<1>" LOC = "P74"; NET "ram_adr<2>" LOC = "P70"; NET "ram_adr<3>" LOC = "P68"; NET "ram_adr<4>" LOC = "P60"; NET "ram_adr<5>" LOC = "P52"; NET "ram_adr<6>" LOC = "P50"; NET "ram_adr<7>" LOC = "P46"; NET "ram_adr<8>" LOC = "P41"; NET "ram_adr<9>" LOC = "P40"; NET "ram_adr<10>" LOC = "P44"; NET "ram_adr<11>" LOC = "P47"; NET "ram_adr<12>" LOC = "P51"; NET "ram_adr<13>" LOC = "P53"; NET "ram_adr<14>" LOC = "P57"; NET "ram_adr<15>" LOC = "P63"; NET "ram_adr<16>" LOC = "P69"; NET "ram_adr<17>" LOC = "P73"; NET "ram_adr<18>" LOC = "P76"; NET "ram_data<0>" LOC = "P23"; NET "ram_data<1>" LOC = "P24"; NET "ram_data<2>" LOC = "P25"; NET "ram_data<3>" LOC = "P26"; NET "ram_data<4>" LOC = "P17"; NET "ram_data<5>" LOC = "P18"; NET "ram_data<6>" LOC = "P20"; NET "ram_data<7>" LOC = "P21"; NET "ram_data<8>" LOC = "P32"; NET "ram_data<9>" LOC = "P33"; NET "ram_data<10>" LOC = "P35"; NET "ram_data<11>" LOC = "P36"; NET "ram_data<12>" LOC = "P27"; NET "ram_data<13>" LOC = "P28"; NET "ram_data<14>" LOC = "P30"; NET "ram_data<15>" LOC = "P31"; NET "ram_wr" LOC = "P55"; NET "ram_rd" LOC = "P59"; NET "ram_cs" LOC = "P56"; 1.1 graphiti/xilinx/miniga.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/miniga.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: miniga.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author -- -- clkin = 45MHz ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity miniga is generic ( ADR_WIDTH : integer := 19; -- A0 bis A18 DATA_WIDTH : integer := 16 -- D0 bis A15 ); port ( clkin : in std_logic; reset : in std_logic; -- das digitale video pixelclock : out std_logic; digitalvideo : out std_logic_vector (9 downto 0); ram_adr : out std_logic_vector ((ADR_WIDTH-1) downto 0); ram_data: inout std_logic_vector ((DATA_WIDTH-1) downto 0); ram_rd : out std_logic; ram_wr : out std_logic; ram_cs : out std_logic; -- spi-interface spi_ss : in std_logic; spi_clk : in std_logic; spi_data : in std_logic; spi_cd : in std_logic ); end miniga; architecture behaviour of miniga is signal clk60M : std_logic; signal clk15M : std_logic; signal clk45M : std_logic; signal sync : std_logic; signal adr1 : std_logic_vector ((ADR_WIDTH-1) downto 0); signal data1_in : std_logic_vector ((DATA_WIDTH-1) downto 0); signal data1_out : std_logic_vector ((DATA_WIDTH-1) downto 0); signal wr1 : std_logic; signal adr2 : std_logic_vector ((ADR_WIDTH-1) downto 0); signal data2_in : std_logic_vector ((DATA_WIDTH-1) downto 0); signal data2_out : std_logic_vector ((DATA_WIDTH-1) downto 0); signal rd2 : std_logic; signal picdata : std_logic_vector (15 downto 0); signal framereset : std_logic; signal readmem : std_logic; signal en_bild : std_logic; signal dummy : std_logic_vector (5 downto 0); signal testbild_r : std_logic_vector (4 downto 0); signal testbild_g : std_logic_vector (4 downto 0); signal testbild_b : std_logic_vector (4 downto 0); signal testbild_data : std_logic_vector (15 downto 0); signal memory_data : std_logic_vector (15 downto 0); signal testbild_en : std_logic; component clk is port ( clkin : in std_logic; reset : in std_logic; clk60M : out std_logic; clk45M : out std_logic; clk15M : out std_logic; pixclk : out std_logic; sync : out std_logic ); end component; component csr is generic ( ADR_WIDTH : integer := 19; -- A0 bis A18 DATA_WIDTH : integer := 16 -- D0 bis D15 ); port ( clk4x : in std_logic; reset : in std_logic; clk : in std_logic; sync : in std_logic; ram_adr : out std_logic_vector ((ADR_WIDTH-1) downto 0); ram_data: inout std_logic_vector ((DATA_WIDTH-1) downto 0); ram_rd : out std_logic; ram_wr : out std_logic; ram_cs : out std_logic; -- insg. 2 SRAMs mit verschiedene CS! adr1 : in std_logic_vector ((ADR_WIDTH-1) downto 0); data1_in : in std_logic_vector ((DATA_WIDTH-1) downto 0); data1_out : out std_logic_vector ((DATA_WIDTH-1) downto 0); rd1 : in std_logic; wr1 : in std_logic; adr2 : in std_logic_vector ((ADR_WIDTH-1) downto 0); data2_in : in std_logic_vector ((DATA_WIDTH-1) downto 0); data2_out : out std_logic_vector ((DATA_WIDTH-1) downto 0); rd2 : in std_logic; wr2 : in std_logic ); end component; component spi is port ( clk : in std_logic; reset : in std_logic; spi_ss : in std_logic; spi_clk : in std_logic; spi_data : in std_logic; spi_cd : in std_logic; out_adr : out std_logic_vector (18 downto 0); out_data : out std_logic_vector (15 downto 0); out_wr : out std_logic; testbild_en : out std_logic ); end component; component pal is Port ( clk : in std_logic; clk15M : in std_logic; reset : in std_logic; output : out std_logic_vector (15 downto 0); in_r : in std_logic_vector (4 downto 0); in_g : in std_logic_vector (4 downto 0); in_b : in std_logic_vector (4 downto 0); framereset : out std_logic; en_bild : out std_logic; readmem: out std_logic ); end component; begin I3: pal port map ( clk => clk45M, clk15M => clk15M, reset => reset, output (15 downto 6) => digitalvideo, output (5 downto 0) => dummy, in_r => picdata (15 downto 11), in_g => picdata (10 downto 6), in_b => picdata (4 downto 0), framereset => framereset, en_bild => en_bild, readmem => readmem ); I0: clk port map ( clkin => clkin, reset => reset, clk60M => clk60M, clk15M => clk15M, clk45M => clk45M, pixclk => pixelclock, sync => sync ); I1: csr port map ( clk4x => clk60M, clk => clk15M, reset => reset, sync => sync, -- direkt mappen ram_data => ram_data, ram_cs => ram_cs, -- die hier gehen erstmal über signale ram_adr => ram_adr, ram_rd => ram_rd, ram_wr => ram_wr, -- spi adr1 => adr1, data1_in => data1_in, data1_out => data1_out, rd1 => '1', -- wird nicht gelesen wr1 => wr1, -- pixel lesen adr2 => adr2, data2_in => data2_in, data2_out => data2_out, rd2 => rd2, wr2 => '1' -- wird nicht geschrieben ); I2: spi port map ( clk => clk15M, reset => reset, spi_ss => spi_ss, spi_clk => spi_clk, spi_data => spi_data, spi_cd => spi_cd, out_adr => adr1, out_data => data1_in, out_wr => wr1, testbild_en => testbild_en ); testbild_data (15 downto 11) <= testbild_r; testbild_data (10 downto 6) <= testbild_g; testbild_data (4 downto 0) <= testbild_b; testbild_data (5) <= '0'; with testbild_en select picdata <= testbild_data when '1', memory_data when others; process (clk15M, en_bild, reset) variable r2yctr : integer := 0; variable ctr2 : integer := 0; begin if en_bild='0' or reset='0' then r2yctr :=0 ; ctr2 := 0; testbild_r <= "00000"; testbild_g <= "00000"; testbild_b <= "00000"; elsif clk15m'event and clk15m='1' then case r2yctr is when 0 => testbild_r <= "11111"; testbild_g <= "11111"; testbild_b <= "11111"; when 1 => testbild_r <= "11111"; testbild_g <= "11111"; testbild_b <= "00000"; when 2 => testbild_r <= "00000"; testbild_g <= "11111"; testbild_b <= "11111"; when 3 => testbild_r <= "00000"; testbild_g <= "11111"; testbild_b <= "00000"; when 4 => testbild_r <= "11111"; testbild_g <= "00000"; testbild_b <= "11111"; when 5 => testbild_r <= "11111"; testbild_g <= "00000"; testbild_b <= "00000"; when 6 => testbild_r <= "00000"; testbild_g <= "00000"; testbild_b <= "11111"; when 7 => testbild_r <= "00000"; testbild_g <= "00000"; testbild_b <= "00000"; when others => testbild_r <= "00000"; testbild_g <= "00000"; testbild_b <= "00000"; end case; ctr2 := ctr2 + 1; if ctr2 = 90 then ctr2 := 0; r2yctr := r2yctr + 1; if (r2yctr = 8) then r2yctr := 0; end if; end if; end if; end process; -- fpga adresse inkrementieren process (clk15M, framereset, reset) variable colctr, rowctr : integer; variable adrctr : integer := 0; begin if reset='0' or framereset='1' then adrctr := 0; rowctr := 0; colctr := 0; rd2 <='1'; elsif clk15M'event and clk15M='1' then rd2 <='0'; memory_data <= data2_out; if en_bild = '1' AND readmem = '1' then if colctr = 779 then adrctr := adrctr + 781; colctr := 0; rowctr := rowctr + 1; else adrctr := adrctr + 1; colctr := colctr + 1; end if; if rowctr = 288 then adrctr := 780; colctr := 0; rowctr := 289; elsif rowctr = 577 then adrctr := 0; colctr := 0; rowctr := 0; end if; adr2 <= conv_std_logic_vector(adrctr,19); else rd2 <= '1'; adrctr := adrctr; memory_data <= (others => '0'); adr2 <= (others => '0'); end if; end if; end process; data2_in <= "0000000000000000"; end architecture; 1.1 graphiti/xilinx/myfir.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/myfir.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: myfir.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author ------------------------------------------------------------------------------- -- fir filter -- uses even and symmetric number of coefficients -- input format: s0,xxxxxxxxxx -- input must be <1024! library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity myfir is generic ( TAPS : integer := 16 ); port ( clk : in std_logic; reset : in std_logic; input : in std_logic_vector(11 downto 0); output : out std_logic_vector(11 downto 0) ); end myfir; architecture behaviour of myfir is begin process (clk, reset) type tsr is array(0 to TAPS-1) of signed(11 downto 0); type tcoff is array(0 to (TAPS/2)-1) of signed(11 downto 0); -- format: s0,xxxxxxxxxx; -- koeffizienten für 16tap 1,3MHz hamming-tiefpass bei 15MHz sampling frequenz variable coff : tcoff := ( x"FFA", x"FFB", x"004", x"027", x"06E", x"0D0", x"132", x"170" ); variable sr : tsr; variable y : signed (63 downto 0); begin if reset='0' then for I in 0 to TAPS-1 loop sr(I) := (others => '0'); end loop; output <= (others => '0'); elsif clk'event and clk='1' then -- Schieberegister for I in (TAPS-1) downto 1 loop sr(I):=sr(I-1); end loop; sr(0) := signed(input); -- jetzt berechnen y:= (others => '0'); for I in 0 to (TAPS/2)-1 loop y:=y+ (sr(I) + sr((TAPS-1)-I)) * coff(I); end loop; output <= conv_std_logic_vector(y(22 downto 11),12); end if; end process; end architecture; 1.1 graphiti/xilinx/pal.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/pal.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: pal.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pal is Port ( clk : in std_logic; clk15M : in std_logic; reset : in std_logic; output : out std_logic_vector (15 downto 0); in_r : in std_logic_vector (4 downto 0); in_g : in std_logic_vector (4 downto 0); in_b : in std_logic_vector (4 downto 0); framereset : out std_logic; en_bild : out std_logic; readmem: out std_logic ); end pal; architecture behaviour of pal is component paltimer is Port ( clk : in std_logic; clk15m : in std_logic; reset : in std_logic; en_sync : out std_logic; en_schwarz : out std_logic; en_bild : out std_logic; en_vertbr : out std_logic; en_verteq : out std_logic; en_burst : out std_logic; phase : out std_logic; framereset : out std_logic; sync : out std_logic; readmem : out std_logic; austastung : out std_logic ); end component; component dds is Port ( clk : in std_logic; reset : in std_logic; phase : in std_logic_vector (1 downto 0); addi : out std_logic_vector (8 downto 0); data : out std_logic_vector (15 downto 0) ); end component; component rgb2yuv is Port ( clk : in std_logic; reset : in std_logic; in_r, in_g, in_b : in std_logic_vector (4 downto 0); out_y, out_u, out_v : out std_logic_vector (11 downto 0) ); end component; component myfir is generic ( TAPS : integer := 16 ); port ( clk : in std_logic; reset : in std_logic; input : in std_logic_vector(11 downto 0); output : out std_logic_vector(11 downto 0) ); end component; component delay is generic ( TAPS : integer := 8 -- group-delay der FIR-Filter ist 500ns ); port ( clk : in std_logic; reset : in std_logic; input : in std_logic_vector(11 downto 0); output : out std_logic_vector(11 downto 0) ); end component; signal cos_data : signed (15 downto 0); signal sin_data : signed (15 downto 0); signal pre_yuv_y : signed (11 downto 0); signal pre_yuv_u : signed (11 downto 0); signal pre_yuv_v : signed (11 downto 0); signal pre_yuv_u2 : signed (11 downto 0); signal pre_yuv_v2 : signed (11 downto 0); signal yuv_y : signed (11 downto 0); signal yuv_u : signed (11 downto 0); signal yuv_v : signed (11 downto 0); signal tmr_phase : std_logic; signal tmr_sync : std_logic; signal tmr_austastung : std_logic; signal tmr_en_bild : std_logic; signal tmr_en_burst : std_logic; --signal prevideo : signed (16 downto 0); --signal preout_u : signed (16 downto 0); --signal preout_v : signed (16 downto 0); --signal preout_y : signed (16 downto 0); --pipelining wegen geschwindigkeit signal modu : signed(27 downto 0); signal modv : signed(27 downto 0); signal mody : signed (11 downto 0); signal modus : signed(28 downto 0); signal modvs : signed(28 downto 0); signal modys : signed(28 downto 0); -- workaround für xilinx signal input_fir1 : std_logic_vector (11 downto 0); signal input_fir2 : std_logic_vector (11 downto 0); signal input_delay : std_logic_vector (11 downto 0); signal output_fir1 : std_logic_vector (11 downto 0); signal output_fir2 : std_logic_vector (11 downto 0); signal output_delay : std_logic_vector (11 downto 0); signal dds1_data : std_logic_vector (15 downto 0); signal dds2_data : std_logic_vector (15 downto 0); signal rgb_out_v : std_logic_vector (11 downto 0); signal rgb_out_u : std_logic_vector (11 downto 0); signal rgb_out_y : std_logic_vector (11 downto 0); begin input_fir1 <= std_logic_vector(pre_yuv_u); input_fir2 <= std_logic_vector(pre_yuv_v); input_delay <= std_logic_vector(pre_yuv_y); yuv_u <= signed(output_fir1); yuv_v <= signed(output_fir2); yuv_y <= signed(output_delay); I_4: myfir port map ( clk => clk15M, reset => reset, input => input_fir1, output => output_fir1 ); I_5: myfir port map ( clk => clk15M, reset => reset, input => input_fir2, output => output_fir2 ); I_6: delay port map ( clk => clk15M, reset => reset, input => input_delay, output => output_delay ); I_0: paltimer port map ( clk => clk, clk15m => clk15m, reset => reset, en_sync => open, en_schwarz => open, en_bild => tmr_en_bild, en_vertbr => open, en_verteq => open, en_burst => tmr_en_burst, phase => tmr_phase, sync => tmr_sync, austastung => tmr_austastung, framereset => framereset, readmem => readmem ); I_1: dds port map ( clk => clk, reset => reset, phase => "01", -- cosinus addi => open, data => dds1_data ); cos_data <= signed(dds1_data); sin_data <= signed(dds2_data); I_2: dds port map ( clk => clk, reset => reset, phase => "00", -- sinus addi => open, data => dds2_data ); I_3: rgb2yuv port map ( clk => clk15m, reset => reset, in_r => in_r, in_g => in_g, in_b => in_b, out_y => rgb_out_y, out_u => rgb_out_u, out_v => rgb_out_v ); pre_yuv_y <= signed(rgb_out_y); pre_yuv_u2 <= signed(rgb_out_u); pre_yuv_v2 <= signed(rgb_out_v); en_bild <= tmr_en_bild; process (tmr_en_burst, tmr_austastung, tmr_en_bild, pre_yuv_u2, pre_yuv_v2) begin if tmr_austastung = '1' then if tmr_en_bild='1' then pre_yuv_u <= pre_yuv_u2; pre_yuv_v <= pre_yuv_v2; elsif tmr_en_burst = '1' then pre_yuv_u <= conv_signed(-171,12); pre_yuv_v <= conv_signed(171,12); else pre_yuv_u <= conv_signed(0,12); pre_yuv_v <= conv_signed(0,12); end if; else pre_yuv_u <= conv_signed(0,12); pre_yuv_v <= conv_signed(0,12); end if; end process; process (clk, reset) variable skaleuv : signed(16 downto 0) := conv_signed(30000,17);--40000 variable skaley : signed(16 downto 0) := conv_signed(36408,17); variable skaleburst : signed (11 downto 0) := conv_signed(240,12); variable psin : signed (15 downto 0); variable preout_u : signed (16 downto 0); variable preout_v : signed (16 downto 0); variable preout_y : signed (16 downto 0); variable prevideo : signed (16 downto 0); variable bursts : signed (27 downto 0); variable burstsin : signed (17 downto 0); variable burstcos : signed (17 downto 0); variable burst17 : signed (16 downto 0); variable i_output : signed (16 downto 0); begin if reset='0' then output <= (others => '0'); elsif clk'event and clk='1' then if tmr_phase='1' then psin := -sin_data; else psin := sin_data; end if; -- u und v modulieren modu <= cos_data * yuv_u; modv <= psin * yuv_v; mody <= yuv_y; -- jetzt skalieren modus <= modu (26 downto 15) * skaleuv; modvs <= modv (26 downto 15) * skaleuv; modys <= mody * skaley; -- yuv_y preout_u := modus (26 downto 10); preout_v := modvs (26 downto 10); preout_y := modys (26 downto 10); -- Y, U und V jetzt zum Signal zusammenbauen prevideo := preout_u + preout_v; if tmr_austastung = '1' and tmr_en_bild='1' then prevideo := prevideo + preout_y; end if; if tmr_sync ='0' then i_output := (others => '0'); else i_output := conv_signed(14563,17) + prevideo; end if; output <= conv_std_logic_vector (i_output (15 downto 0),16); end if; end process; end behaviour; 1.1 graphiti/xilinx/paltimer.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/paltimer.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: paltimer.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity paltimer is Port ( clk : in std_logic; clk15m : in std_logic; reset : in std_logic; en_sync : out std_logic; en_schwarz : out std_logic; en_bild : out std_logic; en_vertbr : out std_logic; en_verteq : out std_logic; en_burst : out std_logic; phase : out std_logic; sync : out std_logic; framereset : out std_logic; readmem : out std_logic; austastung : out std_logic); end paltimer; architecture Behavioral of paltimer is attribute clock_signal : string; begin process (clk15m, reset) variable pixctr : integer := 0; variable hlctr : integer :=0; variable i_en_sync : std_logic := '0'; variable i_en_sync_last : std_logic := '0'; variable i_en_schwarz : std_logic := '0'; variable i_en_bild : std_logic := '0'; variable i_en_burst : std_logic := '0'; variable i_en_vertbr : std_logic := '0'; variable i_en_vertbr_last : std_logic := '0'; variable i_en_verteq : std_logic := '0'; variable i_austastung : std_logic := '0'; variable i_framereset : std_logic := '0'; variable i_sync : std_logic := '0'; variable i_readmem : std_logic := '0'; variable i_phase : std_logic := '0'; variable i_sync_c : integer := 0; begin if reset='0' then pixctr := 0; hlctr :=0; i_en_sync := '0'; i_en_schwarz := '0'; i_en_bild := '0'; i_en_burst := '0'; i_en_vertbr := '0'; i_en_verteq := '0'; i_austastung := '0'; i_framereset := '0'; i_sync := '0'; i_readmem := '0'; i_phase := '0'; en_sync <= '0'; en_schwarz <= '0'; en_bild <= '0'; en_vertbr <= '0'; en_verteq <= '0'; en_burst <= '0'; phase <= '0'; sync <= '0'; framereset <= '1'; readmem <= '0'; austastung <= '0'; elsif clk15m'event and clk15m='1' then pixctr:=pixctr+1; if pixctr = 960 then pixctr:=0; end if; if pixctr >= 0 AND pixctr <= 70 then i_en_sync := '1'; else i_en_sync := '0'; end if; -- flanke nochmal checken ... if i_en_sync ='0' and i_en_sync_last='1' then i_phase := NOT i_phase; end if; i_en_sync_last := i_en_sync; if (pixctr >= 0 AND pixctr <= 157 ) then i_en_schwarz := '1'; elsif (pixctr >= 938 AND pixctr <= 959 ) then i_en_schwarz := '1'; else i_en_schwarz := '0'; end if; if pixctr >= 158 AND pixctr <= 937 then i_en_bild := '1'; else i_en_bild := '0'; end if; if pixctr >= 81 AND pixctr <= 118 then i_en_burst := '1'; else i_en_burst := '0'; end if; if pixctr >= 0 AND pixctr <= 408 then i_en_vertbr := '1'; elsif pixctr >= 480 AND pixctr <= 888 then i_en_vertbr := '1'; else i_en_vertbr := '0'; end if; if pixctr >= 0 AND pixctr <= 34 then i_en_verteq := '1'; elsif pixctr >= 480 AND pixctr <= 514 then i_en_verteq := '1'; else i_en_verteq := '0'; end if; if i_en_vertbr='1' and i_en_vertbr_last='0' then hlctr:=hlctr+1; if hlctr = 1250 then hlctr:=0; i_framereset := '1'; else i_framereset := '0'; end if; if hlctr >= 0 and hlctr <= 4 then i_sync_c := 1; elsif hlctr >= 5 and hlctr <= 9 then i_sync_c := 2; elsif hlctr >= 10 and hlctr <= 619 then i_sync_c := 3; elsif hlctr >= 620 and hlctr <= 624 then i_sync_c := 2; elsif hlctr >= 625 and hlctr <= 629 then i_sync_c := 1; elsif hlctr >= 630 and hlctr <= 634 then i_sync_c := 2; elsif hlctr >= 635 and hlctr <= 1244 then i_sync_c := 3; elsif hlctr >= 1245 and hlctr <= 1249 then i_sync_c := 2; else i_sync_c := 0; end if; if hlctr >= 1245 and hlctr <= 1249 then i_austastung := '1'; elsif hlctr >= 0 and hlctr <= 44 then i_austastung := '1'; elsif hlctr >= 620 and hlctr <= 668 then i_austastung := '1'; else i_austastung := '0'; end if; if hlctr >= 42 and hlctr <= 617 then i_readmem := '1'; elsif hlctr >= 668 and hlctr <= 1241 then i_readmem := '1'; else i_readmem := '0'; end if; end if; i_en_vertbr_last := i_en_vertbr; case i_sync_c is when 0 => i_sync := '0'; when 1 => i_sync := i_en_vertbr; when 2 => i_sync := i_en_verteq; when 3 => i_sync := i_en_sync; when others => i_sync := '0'; end case; phase <= i_phase; en_sync <= i_en_sync; en_schwarz <= i_en_schwarz; en_bild <= i_en_bild; en_vertbr <= i_en_vertbr; en_verteq <= i_en_verteq; en_burst <= i_en_burst; readmem <= i_readmem; sync <= NOT i_sync; austastung <= NOT i_austastung; framereset <= i_framereset; end if; end process; end Behavioral; 1.1 graphiti/xilinx/rgb2yuv.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/rgb2yuv.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: rgb2yuv.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rgb2yuv is Port ( clk : in std_logic; reset : in std_logic; in_r, in_g, in_b : in std_logic_vector (4 downto 0); -- signed out_y, out_u, out_v : out std_logic_vector (11 downto 0)); -- unsigned end rgb2yuv; architecture Behavioral of rgb2yuv is begin process (clk, reset) variable multu : signed (11 downto 0) := conv_signed (517,12); variable multv : signed (11 downto 0) := conv_signed (929,12); variable var_y : signed (11 downto 0); variable in_rs : signed (11 downto 0); variable in_gs : signed (11 downto 0); variable in_bs : signed (11 downto 0); variable worku24 : signed (23 downto 0); variable workv24 : signed (23 downto 0); variable rsigned : signed (11 downto 0) := conv_signed(0,12); variable bsigned : signed (11 downto 0) := conv_signed(0,12); begin if reset='0' then out_u <= (others => '0'); out_v <= (others => '0'); out_y <= (others => '0'); elsif clk='1' and clk'event then case in_r is when "00000" => in_rs := "000000000000"; -- 0.0000 when "00001" => in_rs := "000000001001"; -- 0.0094 when "00010" => in_rs := "000000010011"; -- 0.0187 when "00011" => in_rs := "000000011100"; -- 0.0281 when "00100" => in_rs := "000000100110"; -- 0.0375 when "00101" => in_rs := "000000110000"; -- 0.0469 when "00110" => in_rs := "000000111001"; -- 0.0562 when "00111" => in_rs := "000001000011"; -- 0.0656 when "01000" => in_rs := "000001001100"; -- 0.0750 when "01001" => in_rs := "000001010110"; -- 0.0844 when "01010" => in_rs := "000001100000"; -- 0.0938 when "01011" => in_rs := "000001101001"; -- 0.1031 when "01100" => in_rs := "000001110011"; -- 0.1125 when "01101" => in_rs := "000001111100"; -- 0.1219 when "01110" => in_rs := "000010000110"; -- 0.1313 when "01111" => in_rs := "000010010000"; -- 0.1406 when "10000" => in_rs := "000010011001"; -- 0.1500 when "10001" => in_rs := "000010100011"; -- 0.1594 when "10010" => in_rs := "000010101100"; -- 0.1687 when "10011" => in_rs := "000010110110"; -- 0.1781 when "10100" => in_rs := "000011000000"; -- 0.1875 when "10101" => in_rs := "000011001001"; -- 0.1969 when "10110" => in_rs := "000011010011"; -- 0.2062 when "10111" => in_rs := "000011011100"; -- 0.2156 when "11000" => in_rs := "000011100110"; -- 0.2250 when "11001" => in_rs := "000011110000"; -- 0.2344 when "11010" => in_rs := "000011111001"; -- 0.2437 when "11011" => in_rs := "000100000011"; -- 0.2531 when "11100" => in_rs := "000100001100"; -- 0.2625 when "11101" => in_rs := "000100010110"; -- 0.2719 when "11110" => in_rs := "000100100000"; -- 0.2813 when "11111" => in_rs := "000100101001"; -- 0.2906 when others => in_rs := (others => '0'); end case; case in_g is when "00000" => in_gs := "000000000000"; -- 0.0000 when "00001" => in_gs := "000000010010"; -- 0.0184 when "00010" => in_gs := "000000100101"; -- 0.0369 when "00011" => in_gs := "000000111000"; -- 0.0553 when "00100" => in_gs := "000001001011"; -- 0.0737 when "00101" => in_gs := "000001011110"; -- 0.0922 when "00110" => in_gs := "000001110001"; -- 0.1106 when "00111" => in_gs := "000010000100"; -- 0.1291 when "01000" => in_gs := "000010010111"; -- 0.1475 when "01001" => in_gs := "000010101001"; -- 0.1659 when "01010" => in_gs := "000010111100"; -- 0.1844 when "01011" => in_gs := "000011001111"; -- 0.2028 when "01100" => in_gs := "000011100010"; -- 0.2213 when "01101" => in_gs := "000011110101"; -- 0.2397 when "01110" => in_gs := "000100001000"; -- 0.2581 when "01111" => in_gs := "000100011011"; -- 0.2766 when "10000" => in_gs := "000100101110"; -- 0.2950 when "10001" => in_gs := "000101000000"; -- 0.3134 when "10010" => in_gs := "000101010011"; -- 0.3319 when "10011" => in_gs := "000101100110"; -- 0.3503 when "10100" => in_gs := "000101111001"; -- 0.3687 when "10101" => in_gs := "000110001100"; -- 0.3872 when "10110" => in_gs := "000110011111"; -- 0.4056 when "10111" => in_gs := "000110110010"; -- 0.4241 when "11000" => in_gs := "000111000101"; -- 0.4425 when "11001" => in_gs := "000111011000"; -- 0.4609 when "11010" => in_gs := "000111101010"; -- 0.4794 when "11011" => in_gs := "000111111101"; -- 0.4978 when "11100" => in_gs := "001000010000"; -- 0.5162 when "11101" => in_gs := "001000100011"; -- 0.5347 when "11110" => in_gs := "001000110110"; -- 0.5531 when "11111" => in_gs := "001001001001"; -- 0.5716 when others => in_gs := (others => '0'); end case; case in_b is when "00000" => in_bs := "000000000000"; -- 0.0000 when "00001" => in_bs := "000000000011"; -- 0.0034 when "00010" => in_bs := "000000000111"; -- 0.0069 when "00011" => in_bs := "000000001010"; -- 0.0103 when "00100" => in_bs := "000000001110"; -- 0.0138 when "00101" => in_bs := "000000010001"; -- 0.0172 when "00110" => in_bs := "000000010101"; -- 0.0206 when "00111" => in_bs := "000000011000"; -- 0.0241 when "01000" => in_bs := "000000011100"; -- 0.0275 when "01001" => in_bs := "000000011111"; -- 0.0309 when "01010" => in_bs := "000000100011"; -- 0.0344 when "01011" => in_bs := "000000100110"; -- 0.0378 when "01100" => in_bs := "000000101010"; -- 0.0413 when "01101" => in_bs := "000000101101"; -- 0.0447 when "01110" => in_bs := "000000110001"; -- 0.0481 when "01111" => in_bs := "000000110100"; -- 0.0516 when "10000" => in_bs := "000000111000"; -- 0.0550 when "10001" => in_bs := "000000111011"; -- 0.0584 when "10010" => in_bs := "000000111111"; -- 0.0619 when "10011" => in_bs := "000001000010"; -- 0.0653 when "10100" => in_bs := "000001000110"; -- 0.0688 when "10101" => in_bs := "000001001001"; -- 0.0722 when "10110" => in_bs := "000001001101"; -- 0.0756 when "10111" => in_bs := "000001010000"; -- 0.0791 when "11000" => in_bs := "000001010100"; -- 0.0825 when "11001" => in_bs := "000001011000"; -- 0.0859 when "11010" => in_bs := "000001011011"; -- 0.0894 when "11011" => in_bs := "000001011111"; -- 0.0928 when "11100" => in_bs := "000001100010"; -- 0.0963 when "11101" => in_bs := "000001100110"; -- 0.0997 when "11110" => in_bs := "000001101001"; -- 0.1031 when "11111" => in_bs := "000001101101"; -- 0.1066 when others => in_bs := (others => '0'); end case; rsigned := (others => '0'); bsigned := (others => '0'); rsigned (9 downto 5) := signed(in_r); bsigned (9 downto 5) := signed(in_b); var_y := signed(in_rs) + signed(in_gs) + signed(in_bs); worku24 := (bsigned-signed(var_y))* multu; workv24 := (rsigned-signed(var_y))* multv; out_u <= conv_std_logic_vector(worku24 (21 downto 10),12); out_v <= conv_std_logic_vector(workv24 (21 downto 10),12); out_y <= conv_std_logic_vector (var_y, var_y'length); end if; end process; end Behavioral; 1.1 graphiti/xilinx/spi.vhd http://www.opencores.org/cvsweb.shtml/graphiti/xilinx/spi.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: spi.vhd =================================================================== ------------------------------------------------------------------------------- -- MiniGA -- Author: Thomas Pototschnig (thomas.pototschnig@g...) -- -- License: Creative Commons Attribution-NonCommercial-ShareAlike 2.0 License -- http://creativecommons.org/licenses/by-nc-sa/2.0/de/ -- -- If you want to use MiniGA for commercial purposes please contact the author ------------------------------------------------------------------------------- -- spi interface -- very slow because this component is crap! -- reason: tried to implement a shift register which gets the clock from SCK -- but this makes a lot harder. Next version will sample the SPI pins library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity spi is port ( clk : in std_logic; reset : in std_logic; spi_ss : in std_logic; spi_clk : in std_logic; spi_data : in std_logic; spi_cd : in std_logic; out_adr : out std_logic_vector (18 downto 0); out_data : out std_logic_vector (15 downto 0); out_wr : out std_logic; testbild_en : out std_logic ); end spi; architecture behaviour of spi is signal rcvd_flag : std_logic; signal rcvd_data : std_logic_vector (15 downto 0); signal rcvd_cd : std_logic; signal ack : std_logic; begin process (spi_ss, spi_clk, ack, reset) variable ctr : integer := 0; variable data : std_logic_vector (15 downto 0); begin if spi_ss='1' or ack='0' or reset='0' then ctr := 0; rcvd_flag <= '0'; elsif spi_clk'event and spi_clk='1' then if ctr /= 16 then -- braucht man nicht - aber erstmal testen wie simuliert data(15-ctr):=spi_data; ctr:=ctr+1; if ctr = 16 then rcvd_data <= data; rcvd_flag <= '1'; rcvd_cd <= spi_cd; ctr := 0; end if; end if; end if; end process; process (clk, reset) variable state : integer := 0; variable adr : unsigned (18 downto 0); variable cmd : integer := 0; begin if reset='0' then state := 0; adr := conv_unsigned(0,19); out_adr <= (others => '0'); out_data <= (others => '0'); out_wr <= '1'; ack <= '1'; testbild_en <= '1'; elsif clk'event and clk='1' then case state is when 0 => -- etwas per spi empfangen? if rcvd_flag = '1' then state:=1; end if; when 1 => -- ja - dann adr und data ausgeben und schreiben aktivieren ack <= '0'; -- spi resetten out_adr <= conv_std_logic_vector(adr,19); adr := adr + 1; if rcvd_cd='0' then -- datum empfangen out_data <= rcvd_data; out_wr <= '0'; else -- commando empfangen cmd := conv_integer(rcvd_data (15 downto 10)); case cmd is when 1 => -- low-byte der adresse adr (9 downto 0) := unsigned(rcvd_data(9 downto 0)); when 2 => -- high-byte der adresse adr (18 downto 10) := unsigned(rcvd_data (8 downto 0)); when 3 => -- testbild an / aus testbild_en <= rcvd_data(0); when others => end case; end if; state := 2; when 2 => -- jetzt wurde das zeugs geschrieben ack <= '1'; out_wr <= '1'; state := 0; when others => state:=0; end case; end if; end process; end architecture;