OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Sun Feb 25 19:24:12 CET 2007
Subject: [cvs-checkins] MODIFIED: spi_boot ...

Date: 00/07/02 25:19:24

Modified: spi_boot/rtl/vhdl spi_boot.vhd spi_counter.vhd Log: fix type handling of resets Revision Changes Path 1.9 spi_boot/rtl/vhdl/spi_boot.vhd http://www.opencores.org/cvsweb.shtml/spi_boot/rtl/vhdl/spi_boot.vhd.diff?r1=1.8&r2=1.9 (In the diff below, changes in quantity of whitespace are not shown.) Index: spi_boot.vhd =================================================================== RCS file: /cvsroot/arniml/spi_boot/rtl/vhdl/spi_boot.vhd,v retrieving revision 1.8 retrieving revision 1.9 diff -u -b -r1.8 -r1.9 --- spi_boot.vhd 11 Sep 2006 23:03:36 -0000 1.8 +++ spi_boot.vhd 25 Feb 2007 18:24:12 -0000 1.9 @@ -2,7 +2,7 @@ -- -- SD/MMC Bootloader -- --- $Id: spi_boot.vhd,v 1.8 2006/09/11 23:03:36 arniml Exp $ +-- $Id: spi_boot.vhd,v 1.9 2007/02/25 18:24:12 arniml Exp $ -- -- Copyright (c) 2005, Arnim Laeuger (arniml@o...) -- @@ -102,12 +102,11 @@ component spi_counter generic ( cnt_width_g : integer := 4; - cnt_max_g : integer := 15; - reset_level_g : integer := 0 + cnt_max_g : integer := 15 ); port ( clk_i : in std_logic; - reset_i : in std_logic; + reset_i : in boolean; cnt_en_i : in boolean; cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); cnt_ovfl_o : out boolean @@ -178,24 +177,31 @@ signal en_outs_s, en_outs_q : boolean; + signal reset_s : boolean; + signal true_s : boolean; begin true_s <= true; + reset_s <= true + when (reset_level_g = 1 and reset_i = '1') or + (reset_level_g = 0 and reset_i = '0') else + false; + ----------------------------------------------------------------------------- -- Process seq -- -- Purpose: -- Implements several sequential elements. -- - seq: process (clk_i, reset_i) + seq: process (clk_i, reset_s) variable bit_cnt_v : unsigned(1 downto 0); begin - if reset_i = reset_level_g then + if reset_s then -- reset bit counter to 63 for power up bit_cnt_q <= (others => '0'); bit_cnt_q(op_r) <= "111111"; @@ -358,9 +364,9 @@ -- The clock for FPGA config has an enable and is stopped on high level. -- There is a phase shift of half a period between spi_clk and cfg_clk. -- - clk_gen: process (clk_i, reset_i) + clk_gen: process (clk_i, reset_s) begin - if reset_i = reset_level_g then + if reset_s then spi_clk_q <= '0'; cfg_clk_q <= '1'; @@ -409,9 +415,9 @@ -- Essential for MMC clock compatibility mode. ----------------------------------------------------------------------------- mmc_comap: if mmc_compat_clk_div_g > 0 generate - mmc_compat_sig: process (clk_i, reset_i) + mmc_compat_sig: process (clk_i, reset_s) begin - if reset_i = reset_level_g then + if reset_s then spi_clk_rising_q <= false; spi_clk_falling_q <= false; @@ -880,12 +886,11 @@ img_cnt_b : spi_counter generic map ( cnt_width_g => width_img_cnt_g, - cnt_max_g => 2**width_img_cnt_g - 1, - reset_level_g => reset_level_g + cnt_max_g => 2**width_img_cnt_g - 1 ) port map ( clk_i => clk_i, - reset_i => reset_i, + reset_i => reset_s, cnt_en_i => cnt_en_img_s, cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0), cnt_ovfl_o => open @@ -905,12 +910,11 @@ mmc_cnt_b : spi_counter generic map ( cnt_width_g => width_mmc_clk_div_g, - cnt_max_g => mmc_compat_clk_div_g, - reset_level_g => reset_level_g + cnt_max_g => mmc_compat_clk_div_g ) port map ( clk_i => clk_i, - reset_i => reset_i, + reset_i => reset_s, cnt_en_i => true_s, cnt_o => open, cnt_ovfl_o => mmc_cnt_ovfl_s @@ -944,6 +948,9 @@ -- File History: -- -- $Log: spi_boot.vhd,v $ +-- Revision 1.9 2007/02/25 18:24:12 arniml +-- fix type handling of resets +-- -- Revision 1.8 2006/09/11 23:03:36 arniml -- disable outputs with reset -- 1.2 spi_boot/rtl/vhdl/spi_counter.vhd http://www.opencores.org/cvsweb.shtml/spi_boot/rtl/vhdl/spi_counter.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: spi_counter.vhd =================================================================== RCS file: /cvsroot/arniml/spi_boot/rtl/vhdl/spi_counter.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- spi_counter.vhd 8 Feb 2005 20:41:33 -0000 1.1 +++ spi_counter.vhd 25 Feb 2007 18:24:12 -0000 1.2 @@ -3,7 +3,7 @@ -- SD/MMC Bootloader -- Generic counter module -- --- $Id: spi_counter.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ +-- $Id: spi_counter.vhd,v 1.2 2007/02/25 18:24:12 arniml Exp $ -- -- Copyright (c) 2005, Arnim Laeuger (arniml@o...) -- @@ -52,13 +52,12 @@ generic ( cnt_width_g : integer := 4; - cnt_max_g : integer := 15; - reset_level_g : integer := 0 + cnt_max_g : integer := 15 ); port ( clk_i : in std_logic; - reset_i : in std_logic; + reset_i : in boolean; cnt_en_i : in boolean; cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); cnt_ovfl_o : out boolean @@ -80,7 +79,7 @@ cnt: process (clk_i, reset_i) begin - if reset_i = reset_level_g then + if reset_i then cnt_q <= (others => '0'); elsif clk_i'event and clk_i = '1' then @@ -110,6 +109,9 @@ -- File History: -- -- $Log: spi_counter.vhd,v $ +-- Revision 1.2 2007/02/25 18:24:12 arniml +-- fix type handling of resets +-- -- Revision 1.1 2005/02/08 20:41:33 arniml -- initial check-in --