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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Wed Feb 14 20:02:15 CET 2007
    Subject: [cvs-checkins] MODIFIED: mlite ...
    Top
    Date: 00/07/02 14:20:02

    Modified: mlite/tools opcodes.asm
    Log:
    Implemented BREAK and SYSCALL opcodes


    Revision Changes Path
    1.11 mlite/tools/opcodes.asm

    http://www.opencores.org/cvsweb.shtml/mlite/tools/opcodes.asm.diff?r1=1.10&r2=1.11

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: opcodes.asm
    ===================================================================
    RCS file: /cvsroot/rhoads/mlite/tools/opcodes.asm,v
    retrieving revision 1.10
    retrieving revision 1.11
    diff -u -b -r1.10 -r1.11
    --- opcodes.asm 17 Mar 2006 03:10:21 -0000 1.10
    +++ opcodes.asm 14 Feb 2007 19:02:14 -0000 1.11
    @@ -32,6 +32,23 @@
    lui $sp,0
    ori $sp,$sp,0xfff0

    + b StartTest
    + nop #nops required to place ISR at 0x3c
    + nop
    +
    +OS_AsmPatchValue:
    + #Code to place at address 0x3c
    + lui $26, 0x1000
    + ori $26, $26, 0x3c
    + jr $26
    + nop
    +
    +InterruptVector: #Address=0x3c
    + mfc0 $26,$14 #C0_EPC=14 (Exception PC)
    + jr $26
    + add $4,$4,5
    +
    +StartTest:
    mtc0 $0,$12 #disable interrupts
    lui $20,0x2000 #serial port write address
    ori $21,$0,'\n' #<CR> letter
    @@ -39,9 +56,34 @@
    ori $23,$0,'\r'
    ori $24,$0,0x0f80 #temp memory

    + sb $23,0($20)
    + sb $21,0($20)
    + sb $23,0($20)
    + sb $21,0($20)
    + sb $23,0($20)
    + sb $21,0($20)
    + sb $23,0($20)
    + sb $21,0($20)
    +
    + #Patch interrupt vector to 0x1000003c
    + la $5, OS_AsmPatchValue
    + sub $6,$5,0x1000
    + blez $6,NoPatch
    +
    + lw $6, 0($5)
    + sw $6, 0x3c($0)
    + lw $6, 4($5)
    + sw $6, 0x40($0)
    + lw $6, 8($5)
    + sw $6, 0x44($0)
    + lw $6, 12($5)
    + sw $6, 0x48($0)
    +NoPatch:
    +
    ######################################
    #Arithmetic Instructions
    ######################################
    +ArthmeticTest:
    ori $2,$0,'A'
    sb $2,0($20)
    ori $2,$0,'r'
    @@ -288,6 +330,7 @@
    ######################################
    #Branch and Jump Instructions
    ######################################
    +BranchTest:
    ori $2,$0,'B'
    sb $2,0($20)
    ori $2,$0,'r'
    @@ -621,10 +664,35 @@
    sb $23,0($20)
    sb $21,0($20)

    +# b LoadTest
    +
    +BreakTest:
    + #p: BREAK
    + ori $2,$0,'p'
    + sb $2,0($20)
    + ori $2,$0,'z'
    + ori $4,$0,59
    + break 0
    + addi $4,$4,1 + sb $4,0($20) + sb $23,0($20) + sb $21,0($20) + + #q: SYSCALL + ori $2,$0,'q' + sb $2,0($20) + ori $4,$0,61 + syscall 0 + addi $4,$4,-1 + sb $4,0($20) + sb $23,0($20) + sb $21,0($20) + ###################################### #Load, Store, and Memory Control Instructions ###################################### +LoadTest: ori $2,$0,'L' sb $2,0($20) ori $2,$0,'o' @@ -785,6 +853,7 @@ ###################################### #Logical Instructions ###################################### +LogicalTest: ori $2,$0,'L' sb $2,0($20) ori $2,$0,'o' @@ -878,6 +947,7 @@ ###################################### #Move Instructions ###################################### +MoveTest: ori $2,$0,'M' sb $2,0($20) ori $2,$0,'o' @@ -933,6 +1003,7 @@ ###################################### #Shift Instructions ###################################### +ShiftTest: ori $2,$0,'S' sb $2,0($20) ori $2,$0,'h'

     
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