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Message
From: cvs at opencores.org<cvs@o...>
Date: Wed Feb 14 19:57:28 CET 2007
Subject: [cvs-checkins] MODIFIED: mlite ...
Date: 00/07/02 14:19:57 Modified: mlite/vhdl mlite_cpu.vhd
Log:
Implemented BREAK and SYSCALL opcodes
Revision Changes Path
1.14 mlite/vhdl/mlite_cpu.vhd
http://www.opencores.org/cvsweb.shtml/mlite/vhdl/mlite_cpu.vhd.diff?r1=1.13&r2=1.14
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mlite_cpu.vhd
===================================================================
RCS file: /cvsroot/rhoads/mlite/vhdl/mlite_cpu.vhd,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -b -r1.13 -r1.14
--- mlite_cpu.vhd 6 Mar 2006 02:07:03 -0000 1.13
+++ mlite_cpu.vhd 14 Feb 2007 18:57:27 -0000 1.14
@@ -137,6 +137,7 @@
signal nullify_op : std_logic;
signal intr_enable : std_logic;
signal intr_signal : std_logic;
+ signal exception_sig : std_logic;
signal reset_reg : std_logic_vector(3 downto 0);
signal reset : std_logic;
begin --architecture
@@ -145,7 +146,7 @@
pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
- or intr_signal = '1'
+ or intr_signal = '1' or exception_sig = '1'
else '0';
c_bus <= c_alu or c_shift or c_mult;
reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
@@ -224,7 +225,8 @@
b_source_out => b_source,
c_source_out => c_source,
pc_source_out=> pc_source,
- mem_source_out=> mem_source);
+ mem_source_out=> mem_source,
+ exception_out=> exception_sig);
u4_reg_bank: reg_bank
generic map(memory_type => memory_type)
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