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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Thu Jan 25 04:06:23 CET 2007
    Subject: [cvs-checkins] MODIFIED: s1_core ...
    Top
    Date: 00/07/01 25:04:06

    Modified: s1_core/tools/opt/tracan tracan.c sim.log
    Log:
    Updated the PCX/CPX fields description with all the info required for debugging.




    Revision Changes Path
    1.3 s1_core/tools/opt/tracan/tracan.c

    http://www.opencores.org/cvsweb.shtml/s1_core/tools/opt/tracan/tracan.c.diff?r1=1.2&r2=1.3

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: tracan.c
    ===================================================================
    RCS file: /cvsroot/fafa1971/s1_core/tools/opt/tracan/tracan.c,v
    retrieving revision 1.2
    retrieving revision 1.3
    diff -u -b -r1.2 -r1.3
    --- tracan.c 24 Jan 2007 23:47:02 -0000 1.2
    +++ tracan.c 25 Jan 2007 03:06:23 -0000 1.3
    @@ -24,8 +24,7 @@
    len = strlen(buf);
    if(len==LEN_REQ && dir==CHAR_REQ) {

    - if(bitsToInt(PCX_VLD,PCX_VLD)==0) printf("INFO: SPC2WBM: *** DIRTY REQUEST FROM SPARC CORE ***\n");
    - else {
    + if(bitsToInt(PCX_VLD,PCX_VLD)==1) {

    // Write details of request packet
    printf("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***\n");
    @@ -47,10 +46,10 @@
    default: printf("INFO: SPC2WBM: Request of Type Unknown\n");
    }
    printf("INFO: SPC2WBM: Non-Cacheable bit is %d\n", bitsToInt(PCX_R,PCX_R));
    - printf("INFO: SPC2WBM: CPU ID is %0X\n", bitsToInt(PCX_CP_HI,PCX_CP_LO));
    - printf("INFO: SPC2WBM: Thread is %0X\n", bitsToInt(PCX_TH_HI,PCX_TH_LO));
    - printf("INFO: SPC2WBM: Invalidate All is %0X\n", bitsToInt(PCX_INVALL,PCX_INVALL));
    - printf("INFO: SPC2WBM: Replaced L1 Way is %0X\n", bitsToInt(PCX_WY_HI,PCX_WY_LO));
    + printf("INFO: SPC2WBM: CPU-ID is %0x\n", bitsToInt(PCX_CP_HI,PCX_CP_LO));
    + printf("INFO: SPC2WBM: Thread is %0x\n", bitsToInt(PCX_TH_HI,PCX_TH_LO));
    + printf("INFO: SPC2WBM: Invalidate All is %0x\n", bitsToInt(PCX_INVALL,PCX_INVALL));
    + printf("INFO: SPC2WBM: Replaced L1 Way is %0x\n", bitsToInt(PCX_WY_HI,PCX_WY_LO));
    switch(bitsToInt(PCX_SZ_HI,PCX_SZ_LO)) {
    case PCX_SZ_1B: printf("INFO: SPC2WBM: Request size is 1 Byte\n"); break;
    case PCX_SZ_2B: printf("INFO: SPC2WBM: Request size is 2 Bytes\n"); break;
    @@ -59,15 +58,13 @@
    case PCX_SZ_16B: printf("INFO: SPC2WBM: Request size is 16 Bytes\n"); break;
    default: printf("INFO: SPC2WBM: Request size is Unknown\n");
    }
    - printf("INFO: SPC2WBM: Address is %05X%05X\n", bitsToInt(PCX_AD_HI,PCX_AD_HI-19), bitsToInt(PCX_AD_HI-20,PCX_AD_LO));
    - printf("INFO: SPC2WBM: Data is %08X%08X\n", bitsToInt(PCX_DA_HI,PCX_DA_HI-31), bitsToInt(PCX_DA_HI-32,PCX_DA_LO));
    - printf("INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master\n");
    + printf("INFO: SPC2WBM: Address is %05x%05x\n", bitsToInt(PCX_AD_HI,PCX_AD_HI-19), bitsToInt(PCX_AD_HI-20,PCX_AD_LO));
    + printf("INFO: SPC2WBM: Data is %08x%08x\n", bitsToInt(PCX_DA_HI,PCX_DA_HI-31), bitsToInt(PCX_DA_HI-32,PCX_DA_LO));
    }

    } else if(len==LEN_RET && dir==CHAR_RET) {

    - if(bitsToInt(CPX_VLD,CPX_VLD)==0) printf("INFO: WBM2SPC: *** DIRTY PACKET TO SPARC CORE ***\n");
    - else {
    + if(bitsToInt(CPX_VLD,CPX_VLD)==1) {

    // Write details of return packet
    printf("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***\n");
    @@ -78,13 +75,16 @@
    case ST_ACK: printf("INFO: WBM2SPC: Return Packet of Type ST_ACK\n"); break;
    default: printf("INFO: WBM2SPC: Return Packet of Type Unknown\n");
    }
    - printf("INFO: WBM2SPC: Error is %0X\n", bitsToInt(CPX_ERR_HI,CPX_ERR_LO));
    + printf("INFO: WBM2SPC: L2 Miss is %0x\n", bitsToInt(CPX_ERR_HI,CPX_ERR_HI));
    + printf("INFO: WBM2SPC: Error is %0x\n", bitsToInt(CPX_ERR_HI-1,CPX_ERR_LO));
    printf("INFO: WBM2SPC: Non-Cacheable bit is %d\n", bitsToInt(CPX_R,CPX_R));
    - printf("INFO: WBM2SPC: Thread is %0X\n", bitsToInt(CPX_TH_HI,CPX_TH_LO));
    - printf("INFO: WBM2SPC: Way Valid is %0X\n", bitsToInt(CPX_WYVLD,CPX_WYVLD));
    - printf("INFO: WBM2SPC: Replaced L2 Way is %0X\n", bitsToInt(CPX_WY_HI,CPX_WY_LO));
    - printf("INFO: WBM2SPC: Data is %08X%08X%08X%08X\n", bitsToInt(CPX_DA_HI,CPX_DA_HI-31), bitsToInt(CPX_DA_HI-32,CPX_DA_HI-63), bitsToInt(CPX_DA_HI-64,CPX_DA_HI-95), bitsToInt(CPX_DA_HI-96,CPX_DA_LO));
    - printf("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core\n");
    + printf("INFO: WBM2SPC: Thread is %0x\n", bitsToInt(CPX_TH_HI,CPX_TH_LO));
    + printf("INFO: WBM2SPC: Way Valid is %0x\n", bitsToInt(CPX_WYVLD,CPX_WYVLD));
    + printf("INFO: WBM2SPC: Replaced L2 Way is %0x\n", bitsToInt(CPX_WY_HI,CPX_WY_LO));
    + printf("INFO: WBM2SPC: Fetch for Boot is %0x\n", bitsToInt(CPX_IF4B,CPX_IF4B));
    + printf("INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is %0x\n", bitsToInt(CPX_IF4B-1,CPX_IF4B-1));
    + printf("INFO: WBM2SPC: PFL is %0x\n", bitsToInt(CPX_IF4B-2,CPX_IF4B-2));
    + printf("INFO: WBM2SPC: Data is %08x%08x%08x%08x\n", bitsToInt(CPX_DA_HI,CPX_DA_HI-31), bitsToInt(CPX_DA_HI-32,CPX_DA_HI-63), bitsToInt(CPX_DA_HI-64,CPX_DA_HI-95), bitsToInt(CPX_DA_HI-96,CPX_DA_LO));
    }

    } else {



    1.2 s1_core/tools/opt/tracan/sim.log

    http://www.opencores.org/cvsweb.shtml/s1_core/tools/opt/tracan/sim.log.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: sim.log
    ===================================================================
    RCS file: /cvsroot/fafa1971/s1_core/tools/opt/tracan/sim.log,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- sim.log 4 Jan 2007 02:23:45 -0000 1.1 +++ sim.log 25 Jan 2007 03:06:23 -0000 1.2 @@ -1,3926 +1,3030 @@ INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type Unknown -INFO: WBM2SPC: Return Packet is a Write Access -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000010001 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 00000000000000000000000000010001 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 3 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 3 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is FFF0000020 +INFO: SPC2WBM: Address is fff0000020 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 1 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 0300000005000100821060008410A0C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 1 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 0300000005000100821060008410a0c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 1 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 1 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is FFF0000024 +INFO: SPC2WBM: Address is fff0000024 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 1 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 0300000005000100821060008410A0C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 1 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 0300000005000100821060008410a0c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 1 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 1 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is FFF0000028 +INFO: SPC2WBM: Address is fff0000028 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 1 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 0300000005000100821060008410A0C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 1 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 0300000005000100821060008410a0c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 2 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 2 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is FFF000002C +INFO: SPC2WBM: Address is fff000002c INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 1 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 0300000005000100821060008410A0C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 1 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 0300000005000100821060008410a0c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 2 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 2 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is FFF0000030 +INFO: SPC2WBM: Address is fff0000030 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 1 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 832870208410800181C0800001000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 1 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 832870208410800181c0800001000000 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 1 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 1 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is FFF0000034 +INFO: SPC2WBM: Address is fff0000034 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 1 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 832870208410800181C0800001000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 1 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 832870208410800181c0800001000000 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 3 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 3 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is FFF0000038 +INFO: SPC2WBM: Address is fff0000038 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 1 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 832870208410800181C0800001000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 1 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 832870208410800181c0800001000000 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is FFF000003C +INFO: SPC2WBM: Address is fff000003c INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 1 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 832870208410800181C0800001000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 1 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 832870208410800181c0800001000000 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 1 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 1 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400C0 +INFO: SPC2WBM: Address is 00000400c0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 1 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is B5802005A2102000821020A983287020 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b5802005a2102000821020a983287020 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2706000E2706040E2706080E27060C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2706000e2706040e2706080e27060c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 2 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 2 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400C0 +INFO: SPC2WBM: Address is 00000400c0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 1 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is B5802005A2102000821020A983287020 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b5802005a2102000821020a983287020 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2706000E2706040E2706080E27060C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2706000e2706040e2706080e27060c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400C0 +INFO: SPC2WBM: Address is 00000400c0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 1 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is B5802005A2102000821020A983287020 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b5802005a2102000821020a983287020 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2706000E2706040E2706080E27060C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2706000e2706040e2706080e27060c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 1 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 1 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400C0 +INFO: SPC2WBM: Address is 00000400c0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 1 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is B5802005A2102000821020A983287020 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b5802005a2102000821020a983287020 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2706000E2706040E2706080E27060C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2706000e2706040e2706080e27060c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400C0 +INFO: SPC2WBM: Address is 00000400c0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 1 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is B5802005A2102000821020A983287020 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b5802005a2102000821020a983287020 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2706000E2706040E2706080E27060C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2706000e2706040e2706080e27060c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400C0 +INFO: SPC2WBM: Address is 00000400c0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 1 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is B5802005A2102000821020A983287020 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b5802005a2102000821020a983287020 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2706000E2706040E2706080E27060C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2706000e2706040e2706080e27060c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 2 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 2 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400C0 +INFO: SPC2WBM: Address is 00000400c0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 +INFO: SPC2WBM: Address is a900000000 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type ST_ACK -INFO: WBM2SPC: Return Packet is a Write Access -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 1 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is B5802005A2102000821020A983287020 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b5802005a2102000821020a983287020 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2706000E2706040E2706080E27060C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2706000e2706040e2706080e27060c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400C0 +INFO: SPC2WBM: Address is 00000400c0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000040 +INFO: SPC2WBM: Address is a900000040 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type ST_ACK -INFO: WBM2SPC: Return Packet is a Write Access -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00010000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 00010000000000000000000000000000 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 1 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is B5802005A2102000821020A983287020 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b5802005a2102000821020a983287020 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2706000E2706040E2706080E27060C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2706000e2706040e2706080e27060c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 3 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 3 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400C0 +INFO: SPC2WBM: Address is 00000400c0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000080 +INFO: SPC2WBM: Address is a900000080 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type ST_ACK -INFO: WBM2SPC: Return Packet is a Write Access -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00020000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 00020000000000000000000000000000 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 1 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is B5802005A2102000821020A983287020 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b5802005a2102000821020a983287020 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2706000E2706040E2706080E27060C0 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2706000e2706040e2706080e27060c0 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 00000400e0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A9000000C0 +INFO: SPC2WBM: Address is a9000000c0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 1 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type ST_ACK -INFO: WBM2SPC: Return Packet is a Write Access -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 0 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 INFO: WBM2SPC: Data is 00030000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 3 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 3 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 00000400e0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: Valid bit is 1 +INFO: WBM2SPC: Return Packet of Type IFILL_RET +INFO: WBM2SPC: L2 Miss is 1 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable +INFO: WBM2SPC: L2 Miss is 0 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 +INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** +INFO: SPC2WBM: Valid bit is 1 +INFO: SPC2WBM: Request of Type IMISS_RQ +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 +INFO: SPC2WBM: Thread is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 2 +INFO: SPC2WBM: Request size is 1 Byte +INFO: SPC2WBM: Address is 00000400e0 +INFO: SPC2WBM: Data is 0000000000000000 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 +INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** +INFO: WBM2SPC: Valid bit is 1 +INFO: WBM2SPC: Return Packet of Type IFILL_RET +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 2 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 3 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 00000400e0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 3 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 1 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 00000400e0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master +INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** +INFO: WBM2SPC: Valid bit is 1 +INFO: WBM2SPC: Return Packet of Type IFILL_RET +INFO: WBM2SPC: L2 Miss is 0 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 +INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** +INFO: WBM2SPC: Valid bit is 1 +INFO: WBM2SPC: Return Packet of Type IFILL_RET +INFO: WBM2SPC: L2 Miss is 0 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Valid bit is 1 +INFO: SPC2WBM: Request of Type IMISS_RQ +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 -INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 3 +INFO: SPC2WBM: Request size is 1 Byte +INFO: SPC2WBM: Address is 00000400e0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 1 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 2 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 00000400e0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 3 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 1 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 00000400e0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 2 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 1 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 00000400e0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master +INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** +INFO: WBM2SPC: Valid bit is 1 +INFO: WBM2SPC: Return Packet of Type IFILL_RET +INFO: WBM2SPC: L2 Miss is 0 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 +INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** +INFO: WBM2SPC: Valid bit is 1 +INFO: WBM2SPC: Return Packet of Type IFILL_RET +INFO: WBM2SPC: L2 Miss is 0 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Valid bit is 1 +INFO: SPC2WBM: Request of Type IMISS_RQ +INFO: SPC2WBM: Non-Cacheable bit is 1 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 -INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 +INFO: SPC2WBM: Request size is 1 Byte +INFO: SPC2WBM: Address is 00000400e0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 1 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 1 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 1 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 2 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 00000400e0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 0 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is a210200082102010e2f04840a2102003 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is e2f008a0a3480000819c682087802025 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 1 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 2 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 0000040100 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 1 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 0 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is c0f023c0c0f023c8c0f023d0c0f023d8 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is c0f023e0c0f023e8c0f023f0c0f023f8 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Non-Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 3 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 0000040120 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 0 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 8f902000a19020008d80200085802000 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Non-Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 87802000841020008990800084102000 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 2 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 3 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 00000400E0 +INFO: SPC2WBM: Address is 0000040140 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 1 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is A210200082102010E2F04840A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Non-Cacheable bit is 0 +INFO: WBM2SPC: Thread is 0 +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b1808000841020018528b03faf808000 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is E2F008A0A3480000819C682087802025 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is b3808000bf988000818000009190200f INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 2 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 3 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 0000040100 +INFO: SPC2WBM: Address is 0000040160 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable +INFO: WBM2SPC: L2 Miss is 0 +INFO: WBM2SPC: Error is 0 +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is C0F023C0C0F023C8C0F023D0C0F023D8 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 9390200095902006979020009b902000 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is C0F023E0C0F023E8C0F023F0C0F023F8 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 999020079d90200782102018c0f00a01 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Valid bit is 1 +INFO: SPC2WBM: Request of Type IMISS_RQ +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 -INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 1 +INFO: SPC2WBM: Request size is 1 Byte +INFO: SPC2WBM: Address is 0000040180 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 -INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 -INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 -INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 -INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 -INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 -INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 -INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 -INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 -INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 -INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 -INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 -INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit -INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Cacheable -INFO: SPC2WBM: CPU ID is 0 -INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 3 -INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 0000040120 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 -INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 -INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit -INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 8F902000A19020008D80200085802000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit -INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 87802000841020008990800084102000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit -INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Cacheable -INFO: SPC2WBM: CPU ID is 0 -INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 3 -INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 0000040140 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit -INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is B1808000841020018528B03FAF808000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 1 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is B3808000BF988000818000009190200F -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit -INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Cacheable -INFO: SPC2WBM: CPU ID is 0 -INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 3 -INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 0000040160 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit -INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 9390200095902006979020009B902000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 0 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is c0f00b01a2102003e2f00960a2102003 INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit +INFO: WBM2SPC: Valid bit is 1 INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 +INFO: WBM2SPC: L2 Miss is 0 INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 999020079D90200782102018C0F00A01 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access +INFO: WBM2SPC: Non-Cacheable bit is 0 INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core +INFO: WBM2SPC: Way Valid is 0 +INFO: WBM2SPC: Replaced L2 Way is 0 +INFO: WBM2SPC: Fetch for Boot is 0 +INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is 1 +INFO: WBM2SPC: PFL is 0 +INFO: WBM2SPC: Data is 821020aa83287020e2706000e2706040 INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type IMISS_RQ -INFO: SPC2WBM: Request is Cacheable -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 1 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 1 INFO: SPC2WBM: Request size is 1 Byte -INFO: SPC2WBM: Error is 0 -INFO: SPC2WBM: Address is 0000040180 +INFO: SPC2WBM: Address is 00000401a0 INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit +INFO: SPC2WBM: Valid bit is 1 INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Access -INFO: SPC2WBM: CPU ID is 0 +INFO: SPC2WBM: Non-Cacheable bit is 0 +INFO: SPC2WBM: CPU-ID is 0 INFO: SPC2WBM: Thread is 0 -INFO: SPC2WBM: Buffer is 0 -INFO: SPC2WBM: Packet ID is 0 +INFO: SPC2WBM: Invalidate All is 0 +INFO: SPC2WBM: Replaced L1 Way is 0 INFO: SPC2WBM: Request size is 8 Bytes -INFO: SPC2WBM: Error is 3 -INFO: SPC2WBM: Address is A900000000 -INFO: SPC2WBM: Data is 0000000000000000 -INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit -INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 4 -INFO: WBM2SPC: Data is C0F00B01A2102003E2F00960A2102003 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has valid bit -INFO: WBM2SPC: Return Packet of Type IFILL_RET -INFO: WBM2SPC: Return Packet is Cacheable -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 821020AA83287020E2706000E2706040 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE *** -INFO: WBM2SPC: Return packet has not valid bit -INFO: WBM2SPC: Return Packet of Type LOAD_RET -INFO: WBM2SPC: Return Packet is a Write Access -INFO: WBM2SPC: Thread is 0 -INFO: WBM2SPC: Packet ID is 0 -INFO: WBM2SPC: Error is 0 -INFO: WBM2SPC: Data is 00000000000000000000000000000000 -INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core -INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE *** -INFO: SPC2WBM: Request has not valid bit -INFO: SPC2WBM: Request of Type STORE_RQ -INFO: SPC2WBM: Request is a Write Acces