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From: cvs at opencores.org<cvs@o...>
Date: Thu Jan 25 00:47:03 CET 2007
Subject: [cvs-checkins] MODIFIED: s1_core ...
Date: 00/07/01 25:00:47

Modified: s1_core/tools/opt/tracan tracan.c
Log:
Corrected the bug about the packet format, now we are near to perfection...




Revision Changes Path
1.2 s1_core/tools/opt/tracan/tracan.c

http://www.opencores.org/cvsweb.shtml/s1_core/tools/opt/tracan/tracan.c.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: tracan.c
===================================================================
RCS file: /cvsroot/fafa1971/s1_core/tools/opt/tracan/tracan.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- tracan.c 4 Jan 2007 02:23:45 -0000 1.1
+++ tracan.c 24 Jan 2007 23:47:02 -0000 1.2
@@ -24,10 +24,12 @@
len = strlen(buf);
if(len==LEN_REQ && dir==CHAR_REQ) {

+ if(bitsToInt(PCX_VLD,PCX_VLD)==0) printf("INFO: SPC2WBM: *** DIRTY REQUEST FROM SPARC CORE ***\n");
+ else {
+
// Write details of request packet
printf("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***\n");
- if(bitsToInt(PCX_VLD,PCX_VLD)==1) printf("INFO: SPC2WBM: Request has valid bit\n");
- else printf("INFO: SPC2WBM: Request has not valid bit\n");
+ printf("INFO: SPC2WBM: Valid bit is %d\n",bitsToInt(PCX_VLD,PCX_VLD));
switch(bitsToInt(PCX_RQ_HI,PCX_RQ_LO)) {
case LOAD_RQ: printf("INFO: SPC2WBM: Request of Type LOAD_RQ\n"); break;
case IMISS_RQ: printf("INFO: SPC2WBM: Request of Type IMISS_RQ\n"); break;
@@ -44,17 +46,11 @@
case RSVD_RQ: printf("INFO: SPC2WBM: Request of Type RSVD_RQ\n"); break;
default: printf("INFO: SPC2WBM: Request of Type Unknown\n");
}
- if(bitsToInt(PCX_RQ_HI,PCX_RQ_LO)==IMISS_RQ) {
- if(bitsToInt(PCX_R,PCX_R)==1) printf("INFO: SPC2WBM: Request is Non-Cacheable\n");
- else printf("INFO: SPC2WBM: Request is Cacheable\n");
- } else {
- if(bitsToInt(PCX_R,PCX_R)==1) printf("INFO: SPC2WBM: Request is a Read Access\n");
- else printf("INFO: SPC2WBM: Request is a Write Access\n");
- }
+ printf("INFO: SPC2WBM: Non-Cacheable bit is %d\n", bitsToInt(PCX_R,PCX_R));
printf("INFO: SPC2WBM: CPU ID is %0X\n", bitsToInt(PCX_CP_HI,PCX_CP_LO));
printf("INFO: SPC2WBM: Thread is %0X\n", bitsToInt(PCX_TH_HI,PCX_TH_LO));
- printf("INFO: SPC2WBM: Buffer is %0X\n", bitsToInt(PCX_BF_HI,PCX_BF_LO));
- printf("INFO: SPC2WBM: Packet ID is %0X\n", bitsToInt(PCX_P_HI,PCX_P_LO));
+ printf("INFO: SPC2WBM: Invalidate All is %0X\n", bitsToInt(PCX_INVALL,PCX_INVALL));
+ printf("INFO: SPC2WBM: Replaced L1 Way is %0X\n", bitsToInt(PCX_WY_HI,PCX_WY_LO));
switch(bitsToInt(PCX_SZ_HI,PCX_SZ_LO)) {
case PCX_SZ_1B: printf("INFO: SPC2WBM: Request size is 1 Byte\n"); break;
case PCX_SZ_2B: printf("INFO: SPC2WBM: Request size is 2 Bytes\n"); break;
@@ -63,35 +59,34 @@
case PCX_SZ_16B: printf("INFO: SPC2WBM: Request size is 16 Bytes\n"); break;
default: printf("INFO: SPC2WBM: Request size is Unknown\n");
}
- printf("INFO: SPC2WBM: Error is %0X\n", bitsToInt(PCX_ERR_HI,PCX_ERR_LO));
printf("INFO: SPC2WBM: Address is %05X%05X\n", bitsToInt(PCX_AD_HI,PCX_AD_HI-19), bitsToInt(PCX_AD_HI-20,PCX_AD_LO));
printf("INFO: SPC2WBM: Data is %08X%08X\n", bitsToInt(PCX_DA_HI,PCX_DA_HI-31), bitsToInt(PCX_DA_HI-32,PCX_DA_LO));
printf("INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master\n");
+ }

} else if(len==LEN_RET && dir==CHAR_RET) {

+ if(bitsToInt(CPX_VLD,CPX_VLD)==0) printf("INFO: WBM2SPC: *** DIRTY PACKET TO SPARC CORE ***\n");
+ else {
+
// Write details of return packet
printf("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***\n");
- if(bitsToInt(CPX_VLD,CPX_VLD)==1) printf("INFO: WBM2SPC: Return packet has valid bit\n");
- else printf("INFO: WBM2SPC: Return packet has not valid bit\n");
+ printf("INFO: WBM2SPC: Valid bit is %d\n", bitsToInt(CPX_VLD,CPX_VLD));
switch(bitsToInt(CPX_RQ_HI,CPX_RQ_LO)) {
case IFILL_RET: printf("INFO: WBM2SPC: Return Packet of Type IFILL_RET\n"); break;
case LOAD_RET: printf("INFO: WBM2SPC: Return Packet of Type LOAD_RET\n"); break;
case ST_ACK: printf("INFO: WBM2SPC: Return Packet of Type ST_ACK\n"); break;
default: printf("INFO: WBM2SPC: Return Packet of Type Unknown\n");
}
- if(bitsToInt(CPX_RQ_HI,CPX_RQ_LO)==IFILL_RET) {
- if(bitsToInt(CPX_R,CPX_R)==1) printf("INFO: WBM2SPC: Return Packet is Non-Cacheable\n");
- else printf("INFO: WBM2SPC: Return Packet is Cacheable\n");
- } else {
- if(bitsToInt(CPX_R,CPX_R)==1) printf("INFO: WBM2SPC: Return Packet is a Read Access\n");
- else printf("INFO: WBM2SPC: Return Packet is a Write Access\n");
- }
- printf("INFO: WBM2SPC: Thread is %0X\n", bitsToInt(CPX_TH_HI,CPX_TH_LO));
- printf("INFO: WBM2SPC: Packet ID is %0X\n", bitsToInt(CPX_P_HI,CPX_P_LO));
printf("INFO: WBM2SPC: Error is %0X\n", bitsToInt(CPX_ERR_HI,CPX_ERR_LO));
+ printf("INFO: WBM2SPC: Non-Cacheable bit is %d\n", bitsToInt(CPX_R,CPX_R));
+ printf("INFO: WBM2SPC: Thread is %0X\n", bitsToInt(CPX_TH_HI,CPX_TH_LO));
+ printf("INFO: WBM2SPC: Way Valid is %0X\n", bitsToInt(CPX_WYVLD,CPX_WYVLD));
+ printf("INFO: WBM2SPC: Replaced L2 Way is %0X\n", bitsToInt(CPX_WY_HI,CPX_WY_LO));
printf("INFO: WBM2SPC: Data is %08X%08X%08X%08X\n", bitsToInt(CPX_DA_HI,CPX_DA_HI-31), bitsToInt(CPX_DA_HI-32,CPX_DA_HI-63), bitsToInt(CPX_DA_HI-64,CPX_DA_HI-95), bitsToInt(CPX_DA_HI-96,CPX_DA_LO));
printf("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core\n");
+ } + } else { printf("PACKET DIRECTION UNKNOWN!!!\n"); }