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Message
From: cvs at opencores.org<cvs@o...>
Date: Wed Jan 24 23:13:20 CET 2007
Subject: [cvs-checkins] MODIFIED: rise ...
Date: 00/07/01 24:23:13 Added: rise/examples uart_sample.s
Log:
Sample assembler program for accessing uart
Revision Changes Path
1.1 rise/examples/uart_sample.s
http://www.opencores.org/cvsweb.shtml/rise/examples/uart_sample.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: uart_sample.s
===================================================================
/*
* Description: UART sample
*/
.text
.org 0x0000
/* address for status register */
ld r8, #0x0
ldhb r8, #0x80
/* address for uart data register */
ld r9, #0x01
ldhb r9, #0x80
/* addresses for branch targets */
ld r11, addrlo(check_rdrf)
ldhb r11, addrhi(check_rdrf)
ld r12, addrlo(check_tdre)
ldhb r12, addrhi(check_tdre)
jmp r12
/* wait for uart receiver data */
check_rdrf:
ld r2, [r8]
ld R3, #0x2
and r2, r3
jmpz r11
/* data available, read data */
ld r4, [R9]
/* increment received data by one */
add r4, #0x1
/* wait for transmitter register empty */
check_tdre:
ld r2, [r8]
ld r3, #0x1
and r2, r3
jmpz r12
/* transmitter register empty: send data */
st r4, [r9]
/* back to start */
jmp r11
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