Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Wed Jan 24 22:54:11 CET 2007
Subject: [cvs-checkins] MODIFIED: rise ...
Date: 00/07/01 24:22:54

Modified: rise/vhdl sc_uart.vhd
Log:
Changed high active resets to low active ones.


Revision Changes Path
1.2 rise/vhdl/sc_uart.vhd

http://www.opencores.org/cvsweb.shtml/rise/vhdl/sc_uart.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: sc_uart.vhd
===================================================================
RCS file: /cvsroot/jlechner/rise/vhdl/sc_uart.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- sc_uart.vhd 21 Jan 2007 23:08:19 -0000 1.1
+++ sc_uart.vhd 24 Jan 2007 21:54:10 -0000 1.2
@@ -141,7 +141,7 @@
process(clk, reset)
begin

- if (reset='1') then
+ if (reset='0') then
rd_data(7 downto 0) <= (others => '0');
elsif rising_edge(clk) then

@@ -172,7 +172,7 @@
variable clkrx : unsigned(3 downto 0);

begin
- if (reset='1') then
+ if (reset='0') then
clk16 := 0;
clktx := "0000";
clkrx := "0000";
@@ -241,7 +241,7 @@

begin

- if (reset='1') then
+ if (reset='0') then
uart_tx_state <= s0;
tsr <= "1111111111";
tf_rd <= '0';
@@ -314,7 +314,7 @@

begin

- if (reset='1') then
+ if (reset='0') then
uart_rx_state <= s0;
rsr <= "0000000000";
rf_wr <= '0';