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From: cvs at opencores.org<cvs@o...>
Date: Fri Dec 29 19:04:23 CET 2006
Subject: [cvs-checkins] MODIFIED: ae18 ...
Date: 00/06/12 29:19:04

Modified: ae18/rtl/verilog ae18_aram.v
Log:
added $Log$




Revision Changes Path
1.3 ae18/rtl/verilog/ae18_aram.v

http://www.opencores.org/cvsweb.shtml/ae18/rtl/verilog/ae18_aram.v.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: ae18_aram.v
===================================================================
RCS file: /cvsroot/sybreon/ae18/rtl/verilog/ae18_aram.v,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- ae18_aram.v 29 Dec 2006 18:04:04 -0000 1.2
+++ ae18_aram.v 29 Dec 2006 18:04:22 -0000 1.3
@@ -10,7 +10,7 @@

/*
*
- * $Id: ae18_aram.v,v 1.2 2006/12/29 18:04:04 sybreon Exp $
+ * $Id: ae18_aram.v,v 1.3 2006/12/29 18:04:22 sybreon Exp $
*
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
@@ -32,7 +32,10 @@
* Basic asynchronous inferred RAM.
*
* HISTORY
- * $Log
+ * $Log: ae18_aram.v,v $
+ * Revision 1.3 2006/12/29 18:04:22 sybreon
+ * added $Log$
+ *
*
*/