Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Fri Dec 29 13:49:45 CET 2006
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/06/12 29:13:49

Modified: jop/java/tools/src/com/jopdesign/tools Jopa.java
Log:
removed generation of bcfetbl.vhd


Revision Changes Path
1.7 jop/java/tools/src/com/jopdesign/tools/Jopa.java

http://www.opencores.org/cvsweb.shtml/jop/java/tools/src/com/jopdesign/tools/Jopa.java.diff?r1=1.6&r2=1.7

(In the diff below, changes in quantity of whitespace are not shown.)

Index: Jopa.java
===================================================================
RCS file: /cvsroot/martin/jop/java/tools/src/com/jopdesign/tools/Jopa.java,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- Jopa.java 12 Jan 2006 11:02:10 -0000 1.6
+++ Jopa.java 29 Dec 2006 12:49:45 -0000 1.7
@@ -17,6 +17,7 @@
2005-01-17 interrupt mux in jtbl.vhd
2005-02-06 JOP version in stack RAM at address 64
2005-02-20 Generate memory data for the simulation
+ 2006-12-29 Remove bcfetbl.vhd generation (it's part of rom.vhd/mif)

*/

@@ -250,7 +251,6 @@
try {
FileWriter rom = new FileWriter(dstDir + "rom.mif");
FileWriter jtbl = new FileWriter(dstDir + "jtbl.vhd");
- FileWriter bcfetbl = new FileWriter(dstDir + "bcfetbl.vhd");

BufferedReader inraw = new BufferedReader(new FileReader(srcDir + fname));

@@ -315,40 +315,6 @@

jtbl.write( line );

-//
-// print bcfetbl.vhd head
-//
- line = "--\n";
- line += "--\tbcfetbl.vhd\n";
- line += "--\n";
- line += "--\tnext bc or bc operand read for bcfetch.\n";
- line += "--\n";
- line += "--\t\tDONT edit this file!\n";
- line += "--\t\tgenerated by Jopa.java\n";
- line += "--\n";
- line += "\n";
- line += "library ieee;\n";
- line += "use ieee.std_logic_1164.all;\n";
- line += "use ieee.std_logic_arith.all;\n";
- line += "use ieee.std_logic_unsigned.all;\n";
- line += "\n";
- line += "entity bcfetbl is\n";
- line += "port (\n";
- line += "\taddr\t\t: in std_logic_vector("+(ADDRBITS-1)+" downto 0);\n";
- line += "\tnxt, opd\t: out std_logic\n";
- line += ");\n";
- line += "end bcfetbl;\n";
- line += "\n";
- line += "architecture rtl of bcfetbl is\n";
- line += "\n";
- line += "begin\n";
- line += "\n";
- line += "process(addr) begin\n";
- line += "\n";
- line += "\tcase addr is\n";
- line += "\n";
-
- bcfetbl.write( line );

int noim_address = 0;
int int_address = 0;
@@ -384,12 +350,6 @@
//
int opcode = l.instr.opcode;

- if (l.nxt || l.opd) {
- bcfetbl.write("\t\twhen \""+bin(pc, ADDRBITS) + "\" => ");
- bcfetbl.write("nxt <= '"+(l.nxt ? 1 : 0)+"'; ");
- bcfetbl.write("opd <= '"+(l.opd ? 1 : 0)+"';\n");
- }
-
if (l.instr.hasOpd) {
int opVal = 0;
if (l.symVal!=null) {
@@ -483,16 +443,6 @@
jtbl.write(line);
jtbl.close();

- line = "\n";
- line += "\t\twhen others => nxt <= '0'; opd <= '0'; \n";
- line += "\tend case;\n";
- line += "end process;\n";
- line += "\n";
- line += "end rtl;\n";
- - bcfetbl.write(line); - bcfetbl.close(); - // // print ROM as generic VHDL file //