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From: cvs at opencores.org<cvs@o...>
Date: Wed Sep 20 15:59:06 CEST 2006
Subject: [cvs-checkins] MODIFIED: dirac ...
Date: 00/06/09 20:15:59

Added: dirac/docs/synthesis_reports/encoder limit_register.syr
Log:
Added Dirac Specification to docs directory


Revision Changes Path
1.1 dirac/docs/synthesis_reports/encoder/limit_register.syr

http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/encoder/limit_register.syr?rev=1.1&content-type=text/x-cvsweb-markup

Index: limit_register.syr
===================================================================
Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Reading design: limit_register.prj

TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT


=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "limit_register.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters
Output File Name : "limit_register"
Output Format : NGC
Target Device : xc2v2000-6-bg575

---- Source Options
Top Module Name : limit_register
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
ROM Style : Auto
Mux Extraction : YES
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
Resource Sharing : YES
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Equivalent register Removal : YES
Slice Packing : YES
Pack IO Registers into IOBs : auto

---- General Options
Optimization Goal : Speed
Optimization Effort : 2
Keep Hierarchy : NO
Global Optimization : AllClockNets
RTL Output : Yes
Write Timing Constraints : NO
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5

---- Other Options
lso : limit_register.lso
Read Cores : YES
cross_clock_analysis : NO
verilog2001 : YES
safe_implementation : No
Optimize Instantiated Primitives : NO
tristate2logic : Yes
use_clock_enable : Yes
use_sync_set : Yes
use_sync_reset : Yes enable_auto_floorplanning : No ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/REGISTER.vhd" in Library work. Architecture rtl of Entity limit_register is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity <limit_register> (Architecture <rtl>). Entity <limit_register> analyzed. Unit <limit_register> generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit <limit_register>. Related source file is "C:/Xilinx/bin/ArithmeticCoder/REGISTER.vhd". Found 16-bit register for signal <Q>. Summary: inferred 16 D-type flip-flop(s). Unit <limit_register> synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 16 1-bit register : 16 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit <limit_register> ... Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block limit_register, actual ratio is 0. FlipFlop Q_0 has been replicated 1 time(s) to handle iob=true attribute. ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : limit_register.ngr Top Level Output File Name : limit_register Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 37 Macro Statistics : # Registers : 16 # 1-bit register : 16 Cell Usage : # BELS : 19 # LUT2 : 1 # LUT3 : 1 # LUT4 : 2 # LUT4_L : 15 # FlipFlops/Latches : 17 # FDE : 17 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 36 # IBUF : 20 # OBUF : 16 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2v2000bg575-6 Number of Slices: 11 out of 10752 0% Number of Slice Flip Flops: 17 out of 21504 0% Number of 4 input LUTs: 19 out of 21504 0% Number of bonded IOBs: 37 out of 408 9% Number of GCLKs: 1 out of 16 6% ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ CLOCK | BUFGP | 17 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -6 Minimum period: 1.635ns (Maximum Frequency: 611.808MHz) Minimum input arrival time before clock: 3.322ns Maximum output required time after clock: 4.711ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'CLOCK' Clock period: 1.635ns (frequency: 611.808MHz) Total number of paths / destination ports: 15 / 15 ------------------------------------------------------------------------- Delay: 1.635ns (Levels of Logic = 1) Source: Q_2 (FF) Destination: Q_3 (FF) Source Clock: CLOCK rising Destination Clock: CLOCK rising Data Path: Q_2 to Q_3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDE:C->Q 2 0.449 0.546 Q_2 (Q_2) LUT4_L:I2->LO 1 0.347 0.000 _n00272 (_n0027) FDE:D 0.293 Q_3 ---------------------------------------- Total 1.635ns (1.089ns logic, 0.546ns route) (66.6% logic, 33.4% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' Total number of paths / destination ports: 134 / 34 ------------------------------------------------------------------------- Offset: 3.322ns (Levels of Logic = 3) Source: SHIFT_ALL (PAD) Destination: Q_3 (FF) Destination Clock: CLOCK rising Data Path: SHIFT_ALL to Q_3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 5 0.653 0.795 SHIFT_ALL_IBUF (SHIFT_ALL_IBUF) LUT2:I0->O 14 0.347 0.888 _n00161 (N28) LUT4_L:I1->LO 1 0.347 0.000 _n00162 (_n0016) FDE:D 0.293 Q_8 ---------------------------------------- Total 3.322ns (1.640ns logic, 1.682ns route) (49.4% logic, 50.6% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' Total number of paths / destination ports: 16 / 16 ------------------------------------------------------------------------- Offset: 4.711ns (Levels of Logic = 1) Source: Q_14 (FF) Destination: OUTPUT<14> (PAD) Source Clock: CLOCK rising Data Path: Q_14 to OUTPUT<14> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDE:C->Q 2 0.449 0.518 Q_14 (Q_14) OBUF:I->O 3.743 OUTPUT_14_OBUF (OUTPUT<14>) ---------------------------------------- Total 4.711ns (4.192ns logic, 0.518ns route) (89.0% logic, 11.0% route) ========================================================================= CPU : 4.63 / 5.00 s | Elapsed : 5.00 / 5.00 s --> Total memory usage is 121148 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)