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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Tue Sep 19 14:12:12 CEST 2006
    Subject: [cvs-checkins] MODIFIED: dirac ...
    Top
    Date: 00/06/09 19:14:12

    Modified: dirac/src/common ARITHMETIC_UNIT.vhd CONTEXT_MANAGER.vhd
    Divider.vhd FIFO.vhd HALVING_MANAGER.vhd
    UPDATER.vhd
    Log:
    Adjusted bitwidths and exp-golomb data format to be compatible with the Dirac Specification and software version 0.6.0. Updated test datasets and synthesis reports accordingly. Arithmetic coding and decoding are now COMPLETE.


    Revision Changes Path
    1.4 dirac/src/common/ARITHMETIC_UNIT.vhd

    http://www.opencores.org/cvsweb.shtml/dirac/src/common/ARITHMETIC_UNIT.vhd.diff?r1=1.3&r2=1.4

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: ARITHMETIC_UNIT.vhd
    ===================================================================
    RCS file: /cvsroot/petebleackley/dirac/src/common/ARITHMETIC_UNIT.vhd,v
    retrieving revision 1.3
    retrieving revision 1.4
    diff -u -b -r1.3 -r1.4
    --- ARITHMETIC_UNIT.vhd 27 May 2005 16:00:28 -0000 1.3
    +++ ARITHMETIC_UNIT.vhd 19 Sep 2006 12:12:11 -0000 1.4
    @@ -1,6 +1,6 @@
    -- ***** BEGIN LICENSE BLOCK *****
    --
    --- $Id: ARITHMETIC_UNIT.vhd,v 1.3 2005/05/27 16:00:28 petebleackley Exp $ $Name: $
    +-- $Id: ARITHMETIC_UNIT.vhd,v 1.4 2006/09/19 12:12:11 petebleackley Exp $ $Name: $
    -- *
    -- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
    -- *
    @@ -20,7 +20,7 @@
    -- * Portions created by the Initial Developer are Copyright (C) 2004.
    -- * All Rights Reserved.
    -- *
    --- * Contributor(s): Peter Bleackley (Original author), Stephan Reichör
    +-- * Contributor(s): Peter Bleackley (Original author)
    -- *
    -- * Alternatively, the contents of this file may be used under the terms of
    -- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
    @@ -35,7 +35,6 @@
    -- * or the LGPL.
    -- * ***** END LICENSE BLOCK ***** */

    -
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    @@ -47,9 +46,9 @@
    --library UNISIM;
    --use UNISIM.VComponents.all;

    - entity ARITHMETIC_UNIT is
    +entity ARITHMETIC_UNIT is
    Port ( DIFFERENCE : in std_logic_vector(15 downto 0);
    - PROB : in std_logic_vector(9 downto 0);
    + PROB : in std_logic_vector(7 downto 0);
    LOW : in std_logic_vector(15 downto 0);
    ENABLE : in std_logic;
    RESET : in std_logic;
    @@ -64,7 +63,7 @@
    architecture RTL of ARITHMETIC_UNIT is

    signal LOW2 : std_logic_vector(16 downto 0);
    - signal PRODUCT : std_logic_vector (26 downto 0);
    + signal PRODUCT : std_logic_vector (24 downto 0);
    signal PRODUCT2 : std_logic_vector (16 downto 0);
    signal RESULT : std_logic_vector (16 downto 0);
    signal RESULT0 : std_logic_vector (16 downto 0);
    @@ -73,19 +72,22 @@
    signal DIFFERENCE3 : std_logic_vector(16 downto 0);
    signal DIFFERENCE4 : std_logic_vector(16 downto 0);
    signal DELAY1 : std_logic;
    - signal DELAY2 : std_logic;
    +-- signal DELAY2 : std_logic;
    signal CALCULATE : std_logic;
    begin

    -- The arithmetic
    DIFFERENCE2 <= ('0' & DIFFERENCE) + "00000000000000001";
    -MULTIPLY : process (CLOCK, DIFFERENCE2, PROB)
    +MULTIPLY : process (CLOCK)
    begin
    if CLOCK'event and CLOCK = '1' then
    + if ENABLE = '1' then
    PRODUCT <= DIFFERENCE2 * PROB;
    end if;
    - end process MULTIPLY;
    - PRODUCT2 <= PRODUCT(26 downto 10);
    + end if;
    +end process MULTIPLY;
    +
    + PRODUCT2 <= PRODUCT(24 downto 8);
    RESULT <= LOW2 + PRODUCT2;
    RESULT_OUT1 <= RESULT(15 downto 0);
    RESULT0 <= (RESULT - "00000000000000001");
    @@ -93,13 +95,13 @@
    DIFFERENCE3 <= (PRODUCT2 - "00000000000000001");
    DIFFERENCE4 <= (DIFFERENCE1 - PRODUCT2);
    DIFFERENCE_OUT1 <= DIFFERENCE4(15 downto 0);
    -
    + DIFFERENCE_OUT0 <= DIFFERENCE3(15 downto 0); -- Control logic CALCULATE <= ENABLE and not RESET; - DATA_LOAD <= DELAY1 and DELAY2; + DATA_LOAD <= DELAY1;-- and DELAY2; -- Sequential control logic @@ -107,10 +109,12 @@ begin if CLOCK'event and CLOCK = '1' then DELAY1 <= CALCULATE; - DELAY2 <= DELAY1; +-- DELAY2 <= DELAY1; + if ENABLE = '1' then DIFFERENCE1 <= '0' & DIFFERENCE; LOW2 <= '0' & LOW; - DIFFERENCE_OUT0 <= DIFFERENCE3(15 downto 0); + end if; + end if; end process DELAYS; 1.3 dirac/src/common/CONTEXT_MANAGER.vhd http://www.opencores.org/cvsweb.shtml/dirac/src/common/CONTEXT_MANAGER.vhd.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: CONTEXT_MANAGER.vhd =================================================================== RCS file: /cvsroot/petebleackley/dirac/src/common/CONTEXT_MANAGER.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- CONTEXT_MANAGER.vhd 18 Aug 2006 14:29:32 -0000 1.2 +++ CONTEXT_MANAGER.vhd 19 Sep 2006 12:12:11 -0000 1.3 @@ -1,6 +1,6 @@ -- ***** BEGIN LICENSE BLOCK ***** -- --- $Id: CONTEXT_MANAGER.vhd,v 1.2 2006/08/18 14:29:32 petebleackley Exp $ $Name: $ +-- $Id: CONTEXT_MANAGER.vhd,v 1.3 2006/09/19 12:12:11 petebleackley Exp $ $Name: $ -- * -- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 -- * @@ -53,20 +53,20 @@ HALVECOUNTS : in std_logic; RESET : in std_logic; CLOCK : in std_logic; - PROB : out std_logic_vector(9 downto 0); + PROB : out std_logic_vector(7 downto 0); READY : out std_logic); end CONTEXT_MANAGER; architecture RTL of CONTEXT_MANAGER is - type MATRIX is array (45 downto 0) of std_logic_vector(19 downto 0); + type MATRIX is array (45 downto 0) of std_logic_vector(15 downto 0); signal PROBABILITY : MATRIX; - constant HALF : std_logic_vector(19 downto 0) := "00000000010000000010"; - signal FRACTION : std_logic_vector(19 downto 0); - signal FRACTION2 : std_logic_vector(19 downto 0); - signal RESET_FLAGS : std_logic_vector (63 downto 0); - signal NEWPROB : std_logic_vector(19 downto 0); - signal RATIO : std_logic_vector(19 downto 0); + constant HALF : std_logic_vector(15 downto 0) := "0000000100000010"; + signal FRACTION : std_logic_vector(15 downto 0); + signal FRACTION2 : std_logic_vector(15 downto 0); + signal RESET_FLAGS : std_logic_vector (45 downto 0); + signal NEWPROB : std_logic_vector(15 downto 0); + signal RATIO : std_logic_vector(15 downto 0); signal UPDATE_PROB : std_logic; signal PROB_CHANGED : std_logic; signal LOAD_DATA : std_logic; @@ -77,33 +77,33 @@ signal DATA_READY : std_logic_vector (1 downto 0); component DIVIDER - port ( NUMERATOR : in std_logic_vector(9 downto 0); - DENOMINATOR : in std_logic_vector(9 downto 0); + port ( NUMERATOR : in std_logic_vector(7 downto 0); + DENOMINATOR : in std_logic_vector(7 downto 0); RESET : in std_logic; CLOCK : in std_logic; - QUOTIENT : out std_logic_vector(9 downto 0)); + QUOTIENT : out std_logic_vector(7 downto 0)); end component DIVIDER; component UPDATER - port ( NUMERATOR : in std_logic_vector(9 downto 0); - DENOMINATOR : in std_logic_vector(9 downto 0); + port ( NUMERATOR : in std_logic_vector(7 downto 0); + DENOMINATOR : in std_logic_vector(7 downto 0); ENABLE : in std_logic; DATA_IN : in std_logic; RESET : in std_logic; CLOCK : in std_logic; - NUMERATOR_OUT : out std_logic_vector(9 downto 0); - DENOMINATOR_OUT : out std_logic_vector(9 downto 0); + NUMERATOR_OUT : out std_logic_vector(7 downto 0); + DENOMINATOR_OUT : out std_logic_vector(7 downto 0); UPDATE : out std_logic); end component UPDATER; component HALVING_MANAGER port ( TRIGGER_HALVING : in std_logic; INPUT_READY : in std_logic; - NUMERATOR_IN : in std_logic_vector(9 downto 0); - DENOMINATOR_IN : in std_logic_vector(9 downto 0); + NUMERATOR_IN : in std_logic_vector(7 downto 0); + DENOMINATOR_IN : in std_logic_vector(7 downto 0); CONTEXT : in std_logic_vector(5 downto 0); RESET : in std_logic; CLOCK : in std_logic; - NUMERATOR_OUT : out std_logic_vector(9 downto 0); - DENOMINATOR_OUT : out std_logic_vector(9 downto 0); + NUMERATOR_OUT : out std_logic_vector(7 downto 0); + DENOMINATOR_OUT : out std_logic_vector(7 downto 0); OUTPUT_READY : out std_logic); end component HALVING_MANAGER; @@ -147,33 +147,33 @@ DIVISION : DIVIDER - port map (NUMERATOR => FRACTION2(19 downto 10), - DENOMINATOR => FRACTION2(9 downto 0), + port map (NUMERATOR => FRACTION2(15 downto 8), + DENOMINATOR => FRACTION2(7 downto 0), RESET => RESET, CLOCK => CLOCK, QUOTIENT => PROB); PROBUPDATE : UPDATER - port map (NUMERATOR => FRACTION2(19 downto 10), - DENOMINATOR => FRACTION2(9 downto 0), + port map (NUMERATOR => FRACTION2(15 downto 8), + DENOMINATOR => FRACTION2(7 downto 0), ENABLE => PROB_CHANGED, DATA_IN => DATA_IN, RESET => RESET, CLOCK => CLOCK, - NUMERATOR_OUT => NEWPROB(19 downto 10), - DENOMINATOR_OUT => NEWPROB(9 downto 0), + NUMERATOR_OUT => NEWPROB(15 downto 8), + DENOMINATOR_OUT => NEWPROB(7 downto 0), UPDATE => UPDATE_PROB); REFRESH: HALVING_MANAGER port map (TRIGGER_HALVING => HALVECOUNTS, INPUT_READY => DATA_FETCHED, - NUMERATOR_IN => FRACTION(19 downto 10), - DENOMINATOR_IN => FRACTION(9 downto 0), + NUMERATOR_IN => FRACTION(15 downto 8), + DENOMINATOR_IN => FRACTION(7 downto 0), CONTEXT => CONTEXT_NUMBER, RESET => RESET, CLOCK => CLOCK, - NUMERATOR_OUT => FRACTION2(19 downto 10), - DENOMINATOR_OUT => FRACTION2(9 downto 0), + NUMERATOR_OUT => FRACTION2(15 downto 8), + DENOMINATOR_OUT => FRACTION2(7 downto 0), OUTPUT_READY => PROB_CHANGED); 1.2 dirac/src/common/Divider.vhd http://www.opencores.org/cvsweb.shtml/dirac/src/common/Divider.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: Divider.vhd =================================================================== RCS file: /cvsroot/petebleackley/dirac/src/common/Divider.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- Divider.vhd 18 Aug 2006 14:29:32 -0000 1.1 +++ Divider.vhd 19 Sep 2006 12:12:11 -0000 1.2 @@ -1,37 +1,38 @@ -- ***** BEGIN LICENSE BLOCK ***** -- --- --- Version: MPL 1.1/GPL 2.0/LGPL 2.1 --- --- The contents of this file are subject to the Mozilla Public License --- Version 1.1 (the "License"); you may not use this file except in compliance --- with the License. You may obtain a copy of the License at --- http://www.mozilla.org/MPL/ --- --- Software distributed under the License is distributed on an "AS IS" basis, --- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for --- the specific language governing rights and limitations under the License. --- --- The Original Code is BBC Research and Development code. --- --- The Initial Developer of the Original Code is the British Broadcasting --- Corporation. --- Portions created by the Initial Developer are Copyright (C) 2006. --- All Rights Reserved. --- --- Contributor(s): Peter Bleackley (Original author) --- --- Alternatively, the contents of this file may be used under the terms of --- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser --- Public License Version 2.1 (the "LGPL"), in which case the provisions of --- the GPL or the LGPL are applicable instead of those above. If you wish to --- allow use of your version of this file only under the terms of the either --- the GPL or LGPL and not to allow others to use your version of this file --- under the MPL, indicate your decision by deleting the provisions above --- and replace them with the notice and other provisions required by the GPL --- or LGPL. If you do not delete the provisions above, a recipient may use --- your version of this file under the terms of any one of the MPL, the GPL --- or the LGPL. +-- $Id: Divider.vhd,v 1.2 2006/09/19 12:12:11 petebleackley Exp $ $Name: $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. -- * ***** END LICENSE BLOCK ***** */ library IEEE; @@ -45,1051 +46,280 @@ --use UNISIM.VComponents.all; entity Divider is - Port ( NUMERATOR : in std_logic_vector(9 downto 0); - DENOMINATOR : in std_logic_vector(9 downto 0); + Port ( NUMERATOR : in std_logic_vector(7 downto 0); + DENOMINATOR : in std_logic_vector(7 downto 0); RESET : in std_logic; CLOCK : in std_logic; - QUOTIENT : out std_logic_vector(9 downto 0)); + QUOTIENT : out std_logic_vector(7 downto 0)); end Divider; architecture RTL of Divider is - signal NUMERATOR2 : std_logic_vector(9 downto 0); - signal DENOMINATOR2 : std_logic_vector( 9 downto 0); - signal RECIPROCAL : std_logic_vector(31 downto 0); - signal PRODUCT1 : std_logic_vector(25 downto 0); - signal PRODUCT2 : std_logic_vector(25 downto 0); - signal TOTAL : std_logic_vector(41 downto 0); - signal INDEX : std_logic_vector (9 downto 0); - type ROM is array (1021 downto 0) of std_logic_vector(31 downto 0); - constant LUT : ROM := ("00000000010000000001000000000100", -"00000000010000000010000000010000", -"00000000010000000011000000100100", -"00000000010000000100000001000000", -"00000000010000000101000001100100", -"00000000010000000110000010010000", -"00000000010000000111000011000101", -"00000000010000001000000100000010", -"00000000010000001001000101000110", -"00000000010000001010000110010011", -"00000000010000001011000111101001", -"00000000010000001100001001000110", -"00000000010000001101001010101100", -"00000000010000001110001100011010", -"00000000010000001111001110010001", -"00000000010000010000010000010000", -"00000000010000010001010010010111", -"00000000010000010010010100100111", -"00000000010000010011010110111111", -"00000000010000010100011001011111", -"00000000010000010101011100001000", -"00000000010000010110011110111010", -"00000000010000010111100001110100", -"00000000010000011000100100110111", -"00000000010000011001101000000010", -"00000000010000011010101011010110", -"00000000010000011011101110110010", -"00000000010000011100110010011000", -"00000000010000011101110110000110", -"00000000010000011110111001111100", -"00000000010000011111111101111100", -"00000000010000100001000010000100", -"00000000010000100010000110010101", -"00000000010000100011001010101110", -"00000000010000100100001111010001", -"00000000010000100101010011111100", -"00000000010000100110011000110001", -"00000000010000100111011101101110", -"00000000010000101000100010110100", -"00000000010000101001101000000100", -"00000000010000101010101101011100", -"00000000010000101011110010111101", -"00000000010000101100111000101000", -"00000000010000101101111110011011", -"00000000010000101111000100011000", -"00000000010000110000001010011110", -"00000000010000110001010000101101", -"00000000010000110010010111000101", -"00000000010000110011011101100110", -"00000000010000110100100100010001", -"00000000010000110101101011000101", -"00000000010000110110110010000010", -"00000000010000110111111001001001", -"00000000010000111001000000011001", -"00000000010000111010000111110010", -"00000000010000111011001111010101", -"00000000010000111100010111000010", -"00000000010000111101011110110111", -"00000000010000111110100110110111", -"00000000010000111111101111000000", -"00000000010001000000110111010010", -"00000000010001000001111111101110", -"00000000010001000011001000010100", -"00000000010001000100010001000100", -"00000000010001000101011001111101", -"00000000010001000110100011000000", -"00000000010001000111101100001101", -"00000000010001001000110101100011", -"00000000010001001001111111000011", -"00000000010001001011001000101110", -"00000000010001001100010010100010", -"00000000010001001101011100100000", -"00000000010001001110100110101000", -"00000000010001001111110000111010", -"00000000010001010000111011010110", -"00000000010001010010000101111100", -"00000000010001010011010000101100", -"00000000010001010100011011100110", -"00000000010001010101100110101010", -"00000000010001010110110001111001", -"00000000010001010111111101010010", -"00000000010001011001001000110101", -"00000000010001011010010100100010", -"00000000010001011011100000011010", -"00000000010001011100101100011100", -"00000000010001011101111000101000", -"00000000010001011111000100111111", -"00000000010001100000010001100000", -"00000000010001100001011110001011", -"00000000010001100010101011000010", -"00000000010001100011111000000010", -"00000000010001100101000101001110", -"00000000010001100110010010100011", -"00000000010001100111100000000100", -"00000000010001101000101101101111", -"00000000010001101001111011100101", -"00000000010001101011001001100110", -"00000000010001101100010111110001", -"00000000010001101101100110000111", -"00000000010001101110110100101001", -"00000000010001110000000011010101", -"00000000010001110001010010001011", -"00000000010001110010100001001101", -"00000000010001110011110000011010", -"00000000010001110100111111110010", -"00000000010001110110001111010101", -"00000000010001110111011111000011", -"00000000010001111000101110111100", -"00000000010001111001111111000001", -"00000000010001111011001111010000", -"00000000010001111100011111101011", -"00000000010001111101110000010001", -"00000000010001111111000001000011", -"00000000010010000000010010000000", -"00000000010010000001100011001000", -"00000000010010000010110100011100", -"00000000010010000100000101111011", -"00000000010010000101010111100110", -"00000000010010000110101001011100", -"00000000010010000111111011011110", -"00000000010010001001001101101011", -"00000000010010001010100000000100", -"00000000010010001011110010101001", -"00000000010010001101000101011001", -"00000000010010001110011000010110", -"00000000010010001111101011011110", -"00000000010010010000111110110010", -"00000000010010010010010010010010", -"00000000010010010011100101111110", -"00000000010010010100111001110101", -"00000000010010010110001101111001", -"00000000010010010111100010001001", -"00000000010010011000110110100101", -"00000000010010011010001011001101", -"00000000010010011011100000000010", -"00000000010010011100110101000010", -"00000000010010011110001010001111", -"00000000010010011111011111101000", -"00000000010010100000110101001110", -"00000000010010100010001011000000", -"00000000010010100011100000111110", -"00000000010010100100110111001001", -"00000000010010100110001101100000", -"00000000010010100111100100000100", -"00000000010010101000111010110101", -"00000000010010101010010001110010", -"00000000010010101011101000111100", -"00000000010010101101000000010010", -"00000000010010101110010111110110", -"00000000010010101111101111100110", -"00000000010010110001000111100011", -"00000000010010110010011111101101", -"00000000010010110011111000000100", -"00000000010010110101010000101000", -"00000000010010110110101001011000", -"00000000010010111000000010010111", -"00000000010010111001011011100010", -"00000000010010111010110100111010", -"00000000010010111100001110100000", -"00000000010010111101101000010010", -"00000000010010111111000010010011", -"00000000010011000000011100100000", -"00000000010011000001110110111011", -"00000000010011000011010001100100", -"00000000010011000100101100011001", -"00000000010011000110000111011101", -"00000000010011000111100010101110", -"00000000010011001000111110001101", -"00000000010011001010011001111001", -"00000000010011001011110101110011", -"00000000010011001101010001111011", -"00000000010011001110101110010001", -"00000000010011010000001010110101", -"00000000010011010001100111100110", -"00000000010011010011000100100110", -"00000000010011010100100001110011", -"00000000010011010101111111001111", -"00000000010011010111011100111001", -"00000000010011011000111010110001", -"00000000010011011010011000110111", -"00000000010011011011110111001100", -"00000000010011011101010101101111", -"00000000010011011110110100100000", -"00000000010011100000010011100000", -"00000000010011100001110010101110", -"00000000010011100011010010001011", -"00000000010011100100110001110110", -"00000000010011100110010001110000", -"00000000010011100111110001111001", -"00000000010011101001010010010000", -"00000000010011101010110010110111", -"00000000010011101100010011101100", -"00000000010011101101110100110000", -"00000000010011101111010110000011", -"00000000010011110000110111100101", -"00000000010011110010011001010110", -"00000000010011110011111011010110", -"00000000010011110101011101100110", -"00000000010011110111000000000100", -"00000000010011111000100010110010", -"00000000010011111010000101110000", -"00000000010011111011101000111101", -"00000000010011111101001100011001", -"00000000010011111110110000000100", -"00000000010100000000010100000000", -"00000000010100000001111000001011", -"00000000010100000011011100100101", -"00000000010100000101000001010000", -"00000000010100000110100110001010", -"00000000010100001000001011010100", -"00000000010100001001110000101110", -"00000000010100001011010110011000", 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-"00000010010110010011111101101001", -"00000010010111101101000010010111", -"00000010011001000111110001101001", -"00000010011010100100001110011111", -"00000010011100000010011100000010", -"00000010011101100010011101100010", -"00000010011111000100010110010111", -"00000010100000101000001010000010", -"00000010100010001101111100001100", -"00000010100011110101110000101000", -"00000010100101011111101011010100", -"00000010100111001011110000010100", -"00000010101000111010000011111101", -"00000010101010101010101010101010", -"00000010101100011101101001000110", -"00000010101110010011000100000101", -"00000010110000001011000000101100", -"00000010110010000101100100001011", -"00000010110100000010110100000010", -"00000010110110000010110110000010", -"00000010111000000101110000001011", -"00000010111010001011101000101110", -"00000010111100010100100110010000", -"00000010111110100000101111101000", -"00000011000000110000001100000011", -"00000011000011000011000011000011", -"00000011000101011001011100100001", -"00000011000111110011100000110001", -"00000011001010010001011000011111", -"00000011001100110011001100110011", -"00000011001111011001000111010010", -"00000011010010000011010010000011", -"00000011010100110001110111101100", -"00000011010111100101000011010111", -"00000011011010011101000000110110", -"00000011011101011001111100100010", -"00000011100000011100000011100000", -"00000011100011100011100011100011", -"00000011100110110000101011010001", -"00000011101010000011101010000011", -"00000011101101011100110000001110", -"00000011110000111100001111000011", -"00000011110100100010011000110101", -"00000011111000001111100000111110", -"00000011111100000011111100000011", -"00000100000000000000000000000000", -"00000100000100000100000100000100", -"00000100001000010000100001000010", -"00000100001100100101110001010011", -"00000100010001000100010001000100", -"00000100010101101100011110010111", -"00000100011010011110111001011000", -"00000100011111011100000100011111", -"00000100100100100100100100100100", -"00000100101001111001000001001010", -"00000100101111011010000100101111", -"00000100110101001000011100111110", -"00000100111011000100111011000100", -"00000101000001010000010100000101", -"00000101000111101011100001010001", -"00000101001110010111100000101001", -"00000101010101010101010101010101", -"00000101011100100110001000001010", -"00000101100100001011001000010110", -"00000101101100000101101100000101", -"00000101110100010111010001011101", -"00000101111101000001011111010000", -"00000110000110000110000110000110", -"00000110001111100111000001100011", -"00000110011001100110011001100110", -"00000110100100000110100100000110", -"00000110101111001010000110101111", -"00000110111010110011111001000101", -"00000111000111000111000111000111", -"00000111010100000111010100000111", -"00000111100001111000011110000111", -"00000111110000011111000001111100", -"00001000000000000000000000000000", -"00001000010000100001000010000100", -"00001000100010001000100010001000", -"00001000110100111101110010110000", -"00001001001001001001001001001001", -"00001001011110110100001001011110", -"00001001110110001001110110001001", -"00001010001111010111000010100011", -"00001010101010101010101010101010", -"00001011001000010110010000101100", -"00001011101000101110100010111010", -"00001100001100001100001100001100", -"00001100110011001100110011001100", -"00001101011110010100001101011110", -"00001110001110001110001110001110", -"00001111000011110000111100001111", -"00010000000000000000000000000000", -"00010001000100010001000100010001", -"00010010010010010010010010010010", -"00010011101100010011101100010011", -"00010101010101010101010101010101", -"00010111010001011101000101110100", -"00011001100110011001100110011001", -"00011100011100011100011100011100", -"00100000000000000000000000000000", -"00100100100100100100100100100100", -"00101010101010101010101010101010", -"00110011001100110011001100110011", -"01000000000000000000000000000000", -"01010101010101010101010101010101", -"10000000000000000000000000000000" - ); + signal NUMERATOR2 : std_logic_vector(7 downto 0); + signal DENOMINATOR2 : std_logic_vector(7 downto 0); + signal RECIPROCAL : std_logic_vector(15 downto 0); + signal PRODUCT : std_logic_vector(23 downto 0); + signal INDEX : std_logic_vector (7 downto 0); + type ROM is array (253 downto 0) of std_logic_vector(15 downto 0); + constant LUT : ROM := ( "0000000100000001", +"0000000100000010", +"0000000100000011", +"0000000100000100", +"0000000100000101", +"0000000100000110", +"0000000100000111", +"0000000100001000", +"0000000100001001", +"0000000100001010", +"0000000100001011", +"0000000100001101", +"0000000100001110", +"0000000100001111", +"0000000100010000", +"0000000100010001", +"0000000100010010", +"0000000100010011", +"0000000100010101", +"0000000100010110", +"0000000100010111", +"0000000100011000", +"0000000100011001", +"0000000100011010", +"0000000100011100", +"0000000100011101", +"0000000100011110", +"0000000100011111", +"0000000100100001", +"0000000100100010", +"0000000100100011", +"0000000100100101", +"0000000100100110", +"0000000100100111", +"0000000100101001", +"0000000100101010", +"0000000100101011", +"0000000100101101", +"0000000100101110", +"0000000100101111", +"0000000100110001", +"0000000100110010", +"0000000100110100", +"0000000100110101", +"0000000100110111", +"0000000100111000", +"0000000100111010", +"0000000100111011", +"0000000100111101", +"0000000100111110", +"0000000101000000", +"0000000101000001", +"0000000101000011", +"0000000101000100", +"0000000101000110", +"0000000101001000", +"0000000101001001", +"0000000101001011", +"0000000101001101", +"0000000101001110", +"0000000101010000", +"0000000101010010", +"0000000101010100", +"0000000101010101", +"0000000101010111", +"0000000101011001", +"0000000101011011", +"0000000101011101", +"0000000101011110", +"0000000101100000", +"0000000101100010", +"0000000101100100", +"0000000101100110", +"0000000101101000", +"0000000101101010", +"0000000101101100", +"0000000101101110", +"0000000101110000", +"0000000101110010", +"0000000101110100", +"0000000101110110", +"0000000101111001", +"0000000101111011", +"0000000101111101", +"0000000101111111", +"0000000110000010", +"0000000110000100", +"0000000110000110", +"0000000110001000", +"0000000110001011", +"0000000110001101", +"0000000110010000", +"0000000110010010", +"0000000110010101", +"0000000110010111", +"0000000110011010", +"0000000110011100", +"0000000110011111", +"0000000110100001", +"0000000110100100", +"0000000110100111", +"0000000110101010", +"0000000110101100", +"0000000110101111", +"0000000110110010", +"0000000110110101", +"0000000110111000", +"0000000110111011", +"0000000110111110", +"0000000111000001", +"0000000111000100", +"0000000111000111", +"0000000111001010", +"0000000111001110", +"0000000111010001", +"0000000111010100", +"0000000111010111", +"0000000111011011", +"0000000111011110", +"0000000111100010", +"0000000111100101", +"0000000111101001", +"0000000111101101", +"0000000111110000", +"0000000111110100", +"0000000111111000", +"0000000111111100", +"0000001000000000", +"0000001000000100", +"0000001000001000", +"0000001000001100", +"0000001000010001", +"0000001000010101", +"0000001000011001", +"0000001000011110", +"0000001000100010", +"0000001000100111", +"0000001000101011", +"0000001000110000", +"0000001000110101", +"0000001000111010", +"0000001000111111", +"0000001001000100", +"0000001001001001", +"0000001001001110", +"0000001001010100", +"0000001001011001", +"0000001001011111", +"0000001001100100", +"0000001001101010", +"0000001001110000", +"0000001001110110", +"0000001001111100", +"0000001010000011", +"0000001010001001", +"0000001010001111", +"0000001010010110", +"0000001010011101", +"0000001010100100", +"0000001010101011", +"0000001010110010", +"0000001010111001", +"0000001011000001", +"0000001011001000", +"0000001011010000", +"0000001011011000", +"0000001011100000", +"0000001011101001", +"0000001011110001", +"0000001011111010", +"0000001100000011", +"0000001100001100", +"0000001100010110", +"0000001100011111", +"0000001100101001", +"0000001100110011", +"0000001100111110", +"0000001101001000", +"0000001101010011", +"0000001101011110", +"0000001101101010", +"0000001101110110", +"0000001110000010", +"0000001110001110", +"0000001110011011", +"0000001110101000", +"0000001110110110", +"0000001111000100", +"0000001111010010", +"0000001111100001", +"0000001111110000", +"0000010000000000", +"0000010000010000", +"0000010000100001", +"0000010000110010", +"0000010001000100", +"0000010001010111", +"0000010001101010", +"0000010001111110", +"0000010010010010", +"0000010010101000", +"0000010010111110", +"0000010011010101", +"0000010011101100", +"0000010100000101", +"0000010100011111", +"0000010100111001", +"0000010101010101", +"0000010101110010", +"0000010110010001", +"0000010110110000", +"0000010111010001", +"0000010111110100", +"0000011000011000", +"0000011000111110", +"0000011001100110", +"0000011010010000", +"0000011010111101", +"0000011011101011", +"0000011100011100", +"0000011101010000", +"0000011110001000", +"0000011111000010", +"0000100000000000", +"0000100001000010", +"0000100010001001", +"0000100011010100", +"0000100100100101", +"0000100101111011", +"0000100111011001", +"0000101000111101", +"0000101010101011", +"0000101100100001", +"0000101110100011", +"0000110000110001", +"0000110011001101", +"0000110101111001", +"0000111000111001", +"0000111100001111", +"0001000000000000", +"0001000100010001", +"0001001001001001", +"0001001110110001", +"0001010101010101", +"0001011101000110", +"0001100110011010", +"0001110001110010", +"0010000000000000", +"0010010010010010", +"0010101010101011", +"0011001100110011", +"0100000000000000", +"0101010101010101", +"1000000000000000"); begin INIT : process(DENOMINATOR,RESET) begin if RESET = '1' then - DENOMINATOR2 <= "0000000010"; + DENOMINATOR2 <= "00000010"; else DENOMINATOR2 <= DENOMINATOR; end if; @@ -1099,7 +329,7 @@ begin if CLOCK'event and CLOCK = '1' then if RESET = '1' then - NUMERATOR2 <= "0000000001"; + NUMERATOR2 <= "00000001"; else NUMERATOR2 <= NUMERATOR; end if; @@ -1107,7 +337,7 @@ end process SETNUMERATOR; -INDEX <= DENOMINATOR2 - "0000000010"; +INDEX <= DENOMINATOR2 - "00000010"; LOOKUP: process(CLOCK) begin @@ -1116,22 +346,15 @@ end if; end process LOOKUP; -DIVIDE1: process(CLOCK) +DIVIDE: process(CLOCK) begin if CLOCK'event and CLOCK='1' then - PRODUCT1<=NUMERATOR2*RECIPROCAL(31 downto 16); + PRODUCT<=NUMERATOR2*RECIPROCAL; end if; -end process DIVIDE1; +end process DIVIDE; -DIVIDE2: process(CLOCK) -begin - if CLOCK'event and CLOCK='1' then - PRODUCT2<=NUMERATOR2*RECIPROCAL(15 downto 0); - end if; -end process DIVIDE2; -TOTAL<=((PRODUCT1 & "0000000000000000") + ("0000000000000000" & PRODUCT2)); -QUOTIENT <= TOTAL(31 downto 22); +QUOTIENT <= PRODUCT(15 downto 8); end RTL; 1.3 dirac/src/common/FIFO.vhd http://www.opencores.org/cvsweb.shtml/dirac/src/common/FIFO.vhd.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: FIFO.vhd =================================================================== RCS file: /cvsroot/petebleackley/dirac/src/common/FIFO.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- FIFO.vhd 27 May 2005 16:00:28 -0000 1.2 +++ FIFO.vhd 19 Sep 2006 12:12:11 -0000 1.3 @@ -1,6 +1,6 @@ -- ***** BEGIN LICENSE BLOCK ***** -- --- $Id: FIFO.vhd,v 1.2 2005/05/27 16:00:28 petebleackley Exp $ $Name: $ +-- $Id: FIFO.vhd,v 1.3 2006/09/19 12:12:11 petebleackley Exp $ $Name: $ -- * -- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 -- * @@ -35,7 +35,6 @@ -- * or the LGPL. -- * ***** END LICENSE BLOCK ***** */ - library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; @@ -46,9 +45,9 @@ --library UNISIM; --use UNISIM.VComponents.all; - entity FIFO is +entity FIFO is generic (RANK : integer range 0 to 16 :=8; - WIDTH : integer range 1 to 16); + WIDTH : integer range 1 to 16 := 1); Port ( WRITE_ENABLE : in std_logic; DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); READ_ENABLE : in std_logic; @@ -127,4 +126,3 @@ end RTL; - 1.2 dirac/src/common/HALVING_MANAGER.vhd http://www.opencores.org/cvsweb.shtml/dirac/src/common/HALVING_MANAGER.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: HALVING_MANAGER.vhd =================================================================== RCS file: /cvsroot/petebleackley/dirac/src/common/HALVING_MANAGER.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- HALVING_MANAGER.vhd 18 Aug 2006 14:29:32 -0000 1.1 +++ HALVING_MANAGER.vhd 19 Sep 2006 12:12:11 -0000 1.2 @@ -1,37 +1,38 @@ -- ***** BEGIN LICENSE BLOCK ***** -- --- --- Version: MPL 1.1/GPL 2.0/LGPL 2.1 --- --- The contents of this file are subject to the Mozilla Public License --- Version 1.1 (the "License"); you may not use this file except in compliance --- with the License. You may obtain a copy of the License at --- http://www.mozilla.org/MPL/ --- --- Software distributed under the License is distributed on an "AS IS" basis, --- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for --- the specific language governing rights and limitations under the License. --- --- The Original Code is BBC Research and Development code. --- --- The Initial Developer of the Original Code is the British Broadcasting --- Corporation. --- Portions created by the Initial Developer are Copyright (C) 2006. --- All Rights Reserved. --- --- Contributor(s): Peter Bleackley (Original author) --- --- Alternatively, the contents of this file may be used under the terms of --- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser --- Public License Version 2.1 (the "LGPL"), in which case the provisions of --- the GPL or the LGPL are applicable instead of those above. If you wish to --- allow use of your version of this file only under the terms of the either --- the GPL or LGPL and not to allow others to use your version of this file --- under the MPL, indicate your decision by deleting the provisions above --- and replace them with the notice and other provisions required by the GPL --- or LGPL. If you do not delete the provisions above, a recipient may use --- your version of this file under the terms of any one of the MPL, the GPL --- or the LGPL. +-- $Id: HALVING_MANAGER.vhd,v 1.2 2006/09/19 12:12:11 petebleackley Exp $ $Name: $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. -- * ***** END LICENSE BLOCK ***** */ library IEEE; @@ -47,24 +48,24 @@ entity HALVING_MANAGER is Port ( TRIGGER_HALVING : in std_logic; INPUT_READY : in std_logic; - NUMERATOR_IN : in std_logic_vector(9 downto 0); - DENOMINATOR_IN : in std_logic_vector(9 downto 0); + NUMERATOR_IN : in std_logic_vector(7 downto 0); + DENOMINATOR_IN : in std_logic_vector(7 downto 0); CONTEXT : in std_logic_vector(5 downto 0); RESET : in std_logic; CLOCK : in std_logic; - NUMERATOR_OUT : out std_logic_vector(9 downto 0); - DENOMINATOR_OUT : out std_logic_vector(9 downto 0); + NUMERATOR_OUT : out std_logic_vector(7 downto 0); + DENOMINATOR_OUT : out std_logic_vector(7 downto 0); OUTPUT_READY : out std_logic); end HALVING_MANAGER; architecture RTL of HALVING_MANAGER is type COUNTARRAY is array(45 downto 0) of std_logic_vector(2 downto 0); signal SHIFTS : COUNTARRAY; - signal NUMERATOR : std_logic_vector (9 downto 0); - signal DENOMINATOR : std_logic_vector (9 downto 0); - signal NUMERATOR2 : std_logic_vector (9 downto 0); - signal DENOMINATOR2 : std_logic_vector (9 downto 0); - signal DENOMINATOR_INCREMENT : std_logic_vector (9 downto 0); + signal NUMERATOR : std_logic_vector (7 downto 0); + signal DENOMINATOR : std_logic_vector (7 downto 0); + signal NUMERATOR2 : std_logic_vector (7 downto 0); + signal DENOMINATOR2 : std_logic_vector (7 downto 0); + signal DENOMINATOR_INCREMENT : std_logic_vector (7 downto 0); signal GREATER_THAN_16 : std_logic; signal PERFORM_HALVING : std_logic; signal AFTER_TRIGGER : std_logic; @@ -92,15 +93,15 @@ end if; end process COUNT_HALVING_EVENTS; -NUMERATOR2 <= ('0' & NUMERATOR (9 downto 1)) + "0000000001"; -DENOMINATOR2 <= ('0' & DENOMINATOR(9 downto 1)) + DENOMINATOR_INCREMENT; +NUMERATOR2 <= ('0' & NUMERATOR (7 downto 1)) + "0000000001"; +DENOMINATOR2 <= ('0' & DENOMINATOR(7 downto 1)) + DENOMINATOR_INCREMENT; HALVE_COUNTS : process (CLOCK) begin if CLOCK'event and CLOCK='1' then if RESET = '1' then - NUMERATOR <= "0000000001"; - DENOMINATOR <= "0000000010"; + NUMERATOR <= "00000001"; + DENOMINATOR <= "00000010"; elsif CALCULATE_VALUES = '1' then NUMERATOR <= NUMERATOR2; DENOMINATOR <= DENOMINATOR2; @@ -113,7 +114,7 @@ HALVING_PERMITTED : process (DENOMINATOR) begin - if DENOMINATOR > "0000010000" then + if DENOMINATOR > "00010000" then GREATER_THAN_16 <= '1'; else GREATER_THAN_16 <= '0'; @@ -154,9 +155,9 @@ CHOOSE_DENOMINATOR_INCREMENT : process (NUMERATOR, DENOMINATOR) begin if (NUMERATOR (0) = '1') and (DENOMINATOR (0) = '0') then - DENOMINATOR_INCREMENT <= "0000000001"; + DENOMINATOR_INCREMENT <= "00000001"; else - DENOMINATOR_INCREMENT <= "0000000010"; + DENOMINATOR_INCREMENT <= "00000010"; end if; end process CHOOSE_DENOMINATOR_INCREMENT; 1.2 dirac/src/common/UPDATER.vhd http://www.opencores.org/cvsweb.shtml/dirac/src/common/UPDATER.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: UPDATER.vhd =================================================================== RCS file: /cvsroot/petebleackley/dirac/src/common/UPDATER.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- UPDATER.vhd 18 Aug 2006 14:29:32 -0000 1.1 +++ UPDATER.vhd 19 Sep 2006 12:12:11 -0000 1.2 @@ -1,37 +1,38 @@ -- ***** BEGIN LICENSE BLOCK ***** -- --- --- Version: MPL 1.1/GPL 2.0/LGPL 2.1 --- --- The contents of this file are subject to the Mozilla Public License --- Version 1.1 (the "License"); you may not use this file except in compliance --- with the License. You may obtain a copy of the License at --- http://www.mozilla.org/MPL/ --- --- Software distributed under the License is distributed on an "AS IS" basis, --- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for --- the specific language governing rights and limitations under the License. --- --- The Original Code is BBC Research and Development code. --- --- The Initial Developer of the Original Code is the British Broadcasting --- Corporation. --- Portions created by the Initial Developer are Copyright (C) 2006. --- All Rights Reserved. --- --- Contributor(s): Peter Bleackley (Original author) --- --- Alternatively, the contents of this file may be used under the terms of --- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser --- Public License Version 2.1 (the "LGPL"), in which case the provisions of --- the GPL or the LGPL are applicable instead of those above. If you wish to --- allow use of your version of this file only under the terms of the either --- the GPL or LGPL and not to allow others to use your version of this file --- under the MPL, indicate your decision by deleting the provisions above --- and replace them with the notice and other provisions required by the GPL --- or LGPL. If you do not delete the provisions above, a recipient may use --- your version of this file under the terms of any one of the MPL, the GPL --- or the LGPL. +-- $Id: UPDATER.vhd,v 1.2 2006/09/19 12:12:11 petebleackley Exp $ $Name: $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. -- * ***** END LICENSE BLOCK ***** */ library IEEE; @@ -45,23 +46,23 @@ --use UNISIM.VComponents.all; entity UPDATER is - Port ( NUMERATOR : in std_logic_vector(9 downto 0); - DENOMINATOR : in std_logic_vector(9 downto 0); + Port ( NUMERATOR : in std_logic_vector(7 downto 0); + DENOMINATOR : in std_logic_vector(7 downto 0); ENABLE : in std_logic; DATA_IN : in std_logic; RESET : in std_logic; CLOCK : in std_logic; - NUMERATOR_OUT : out std_logic_vector(9 downto 0); - DENOMINATOR_OUT : out std_logic_vector(9 downto 0); + NUMERATOR_OUT : out std_logic_vector(7 downto 0); + DENOMINATOR_OUT : out std_logic_vector(7 downto 0); UPDATE : out std_logic); end UPDATER; architecture RTL of UPDATER is - signal NUMERATOR1 : std_logic_vector(9 downto 0); - signal NUMERATOR2 : std_logic_vector(9 downto 0); - signal NUMERATOR3 : std_logic_vector(9 downto 0); - signal NUMERATOR4 : std_logic_vector(9 downto 0); - signal DENOMINATOR2 : std_logic_vector(9 downto 0); + signal NUMERATOR1 : std_logic_vector(7 downto 0); + signal NUMERATOR2 : std_logic_vector(7 downto 0); + signal NUMERATOR3 : std_logic_vector(7 downto 0); + signal NUMERATOR4 : std_logic_vector(7 downto 0); + signal DENOMINATOR2 : std_logic_vector(7 downto 0); signal HALVE_VALUES : std_logic; signal HALVING_ALLOWED : std_logic; signal UPDATE_SWITCH : std_logic; @@ -71,7 +72,7 @@ begin if CLOCK'event and CLOCK='1' then if RESET='1' then - NUMERATOR1<="0000000001"; + NUMERATOR1<="00000001"; else NUMERATOR1<=NUMERATOR; end if; @@ -82,9 +83,9 @@ begin if CLOCK'event and CLOCK = '1' then if RESET = '1' then - NUMERATOR2 <= "0000000001"; + NUMERATOR2 <= "00000001"; else - NUMERATOR2 <= NUMERATOR + "0000000001"; + NUMERATOR2 <= NUMERATOR + "00000001"; end if; end if; end process INCREMENT_NUMERATOR; @@ -93,9 +94,9 @@ begin if CLOCK'event and CLOCK='1' then if RESET='1' then - NUMERATOR3 <= "0000000001"; + NUMERATOR3 <= "00000001"; else - NUMERATOR3 <= ('0' & NUMERATOR(9 downto 1)) + "0000000001"; + NUMERATOR3 <= ('0' & NUMERATOR(7 downto 1)) + "00000001"; end if; end if; end process HALVE_NUMERATOR; @@ -104,9 +105,9 @@ begin if CLOCK'event and CLOCK='1' then if RESET='1' then - NUMERATOR4 <= "0000000001"; + NUMERATOR4 <= "00000001"; else - NUMERATOR4 <= ('0' & NUMERATOR(9 downto 1)) + "0000000001" + ("000000000" & NUMERATOR(0)); + NUMERATOR4 <= ('0' & NUMERATOR(7 downto 1)) + "00000001" + ("0000000" & NUMERATOR(0)); end if; end if; end process INCREMENT_AND_HALVE_NUMERATOR; @@ -115,16 +116,16 @@ begin if CLOCK'event and CLOCK='1' then if RESET='1' then - DENOMINATOR2 <= "0000000010"; + DENOMINATOR2 <= "00000010"; else - DENOMINATOR2 <= DENOMINATOR + "0000000001"; + DENOMINATOR2 <= DENOMINATOR + "00000001"; end if; end if; end process INCREMENT_DENOMINATOR; HALVE_DENOMINATOR : process (DENOMINATOR) begin - if (DENOMINATOR = "1111111111") then + if (DENOMINATOR = "11111111") then HALVE_VALUES <= '1'; else HALVE_VALUES <= '0'; @@ -154,9 +155,9 @@ begin if HALVE_VALUES='1' then if UPDATE_SWITCH = '1' then - DENOMINATOR_OUT <= "1000000010"; + DENOMINATOR_OUT <= "10000010"; else - DENOMINATOR_OUT <= "1000000001"; + DENOMINATOR_OUT <= "10000001"; end if; else DENOMINATOR_OUT<=DENOMINATOR2;

     
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