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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Tue Sep 19 14:12:11 CEST 2006
    Subject: [cvs-checkins] MODIFIED: dirac ...
    Top
    Date: 00/06/09 19:14:12

    Modified: dirac/docs/synthesis_reports/expgolomb
    exp_golomb_counter.syr exp_golomb_decoder.syr
    Log:
    Adjusted bitwidths and exp-golomb data format to be compatible with the Dirac Specification and software version 0.6.0. Updated test datasets and synthesis reports accordingly. Arithmetic coding and decoding are now COMPLETE.


    Revision Changes Path
    1.2 dirac/docs/synthesis_reports/expgolomb/exp_golomb_counter.syr

    http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/expgolomb/exp_golomb_counter.syr.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: exp_golomb_counter.syr
    ===================================================================
    RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/expgolomb/exp_golomb_counter.syr,v
    retrieving revision 1.1
    retrieving revision 1.2
    diff -u -b -r1.1 -r1.2
    --- exp_golomb_counter.syr 6 Sep 2006 18:41:03 -0000 1.1
    +++ exp_golomb_counter.syr 19 Sep 2006 12:12:10 -0000 1.2
    @@ -1,10 +1,10 @@
    Release 7.1.04i - xst H.42
    Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
    --> Parameter TMPDIR set to __projnav
    -CPU : 0.00 / 2.44 s | Elapsed : 0.00 / 2.00 s
    +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s

    --> Parameter xsthdpdir set to ./xst
    -CPU : 0.00 / 2.44 s | Elapsed : 0.00 / 2.00 s
    +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s

    --> Reading design: exp_golomb_counter.prj

    @@ -96,13 +96,15 @@
    * HDL Compilation *
    =========================================================================
    Compiling vhdl file "C:/Xilinx/bin/exp_golomb_counter/EXP_GOLOMB_COUNTER.vhd" in Library work.
    -Architecture rtl of Entity exp_golomb_counter is up to date.
    +Entity <exp_golomb_counter> compiled.
    +Entity <exp_golomb_counter> (Architecture <rtl>) compiled.

    =========================================================================
    * HDL Analysis *
    =========================================================================
    Analyzing Entity <exp_golomb_counter> (Architecture <rtl>).
    -WARNING:Xst:790 - "C:/Xilinx/bin/exp_golomb_counter/EXP_GOLOMB_COUNTER.vhd" line 155: Index value(s) does not match array range, simulation mismatch.
    +WARNING:Xst:790 - "C:/Xilinx/bin/exp_golomb_counter/EXP_GOLOMB_COUNTER.vhd" line 131: Index value(s) does not match array range, simulation mismatch.
    +INFO:Xst:1607 - Contents of array <DATA2> may be accessed with an index that does not cover the full array size.
    Entity <exp_golomb_counter> analyzed. Unit <exp_golomb_counter> generated.


    @@ -113,21 +115,19 @@
    Synthesizing Unit <exp_golomb_counter>.
    Related source file is "C:/Xilinx/bin/exp_golomb_counter/EXP_GOLOMB_COUNTER.vhd".
    Found 1-bit register for signal <DATA_OUT>.
    - Found 1-bit 33-to-1 multiplexer for signal <$n0035> created at line 155.
    + Found 1-bit 33-to-1 multiplexer for signal <$n0034> created at line 131.
    Found 1-bit 4-to-1 multiplexer for signal <$n0036>.
    - Found 6-bit comparator equal for signal <$n0042> created at line 146.
    - Found 6-bit comparator not equal for signal <$n0043> created at line 146.
    + Found 1-bit 4-to-1 multiplexer for signal <$n0038>.
    + Found 5-bit subtractor for signal <$n0043> created at line 139.
    Found 33-bit adder for signal <DATA2>.
    - Found 6-bit register for signal <LOG>.
    - Found 6-bit updown counter for signal <OUT_ADDRESS>.
    + Found 5-bit register for signal <LOG>.
    + Found 1-bit register for signal <MODE>.
    + Found 5-bit register for signal <OUT_ADDRESS>.
    Found 1-bit register for signal <OUTPUT_ACTIVE>.
    - Found 1-bit register for signal <UPDOWN>.
    Summary:
    - inferred 1 Counter(s).
    - inferred 3 D-type flip-flop(s).
    - inferred 1 Adder/Subtractor(s).
    - inferred 2 Comparator(s).
    - inferred 2 Multiplexer(s).
    + inferred 8 D-type flip-flop(s).
    + inferred 2 Adder/Subtractor(s).
    + inferred 3 Multiplexer(s).
    Unit <exp_golomb_counter> synthesized.


    @@ -144,26 +144,21 @@
    HDL Synthesis Report

    Macro Statistics
    -# Adders/Subtractors : 1
    +# Adders/Subtractors : 2
    33-bit adder : 1
    -# Counters : 1
    - 6-bit updown counter : 1
    -# Registers : 4
    + 5-bit subtractor : 1
    +# Registers : 5
    1-bit register : 3
    - 6-bit register : 1
    -# Comparators : 2
    - 6-bit comparator equal : 1
    - 6-bit comparator not equal : 1
    -# Multiplexers : 2 + 5-bit register : 2 +# Multiplexers : 3 1-bit 33-to-1 multiplexer : 1 - 1-bit 4-to-1 multiplexer : 1 + 1-bit 4-to-1 multiplexer : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= -WARNING:Xst:1988 - Unit <exp_golomb_counter>: instances <Mcompar__n0043>, <Mcompar__n0042> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_1> are dual, second instance is removed Optimizing unit <exp_golomb_counter> ... Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. @@ -171,7 +166,7 @@ Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block exp_golomb_counter, actual ratio is 0. -FlipFlop OUTPUT_ACTIVE has been replicated 1 time(s) to handle iob=true attribute. +FlipFlop OUT_ADDRESS_0 has been replicated 1 time(s) ========================================================================= * Final Report * @@ -187,42 +182,36 @@ # IOs : 37 Macro Statistics : -# Registers : 10 -# 1-bit register : 9 -# 6-bit register : 1 -# Multiplexers : 2 +# Registers : 9 +# 1-bit register : 8 +# 5-bit register : 1 +# Multiplexers : 3 # 1-bit 33-to-1 multiplexer : 1 -# 1-bit 4-to-1 multiplexer : 1 -# Adders/Subtractors : 2 +# 1-bit 4-to-1 multiplexer : 2 +# Adders/Subtractors : 1 # 33-bit adder : 1 -# 6-bit addsub : 1 -# Comparators : 2 -# 6-bit comparator equal : 1 -# 6-bit comparator not equal : 1 Cell Usage : -# BELS : 196 +# BELS : 183 # GND : 1 -# INV : 1 +# INV : 2 # LUT1 : 31 -# LUT2 : 4 -# LUT2_L : 5 +# LUT2 : 5 # LUT3 : 7 -# LUT3_L : 16 -# LUT4 : 31 -# LUT4_L : 6 -# MUXCY : 40 -# MUXF5 : 9 +# LUT3_L : 19 +# LUT4 : 33 +# LUT4_D : 1 +# LUT4_L : 5 +# MUXCY : 32 +# MUXF5 : 8 # MUXF6 : 4 # MUXF7 : 2 # MUXF8 : 1 # VCC : 1 -# XORCY : 37 -# FlipFlops/Latches : 16 -# FDRE : 8 -# FDRS : 5 -# FDRSE : 2 -# FDS : 1 +# XORCY : 31 +# FlipFlops/Latches : 14 +# FDRE : 9 +# FDS : 5 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 36 @@ -236,8 +225,8 @@ Selected Device : 2v2000bg575-6 Number of Slices: 54 out of 10752 0% - Number of Slice Flip Flops: 16 out of 21504 0% - Number of 4 input LUTs: 100 out of 21504 0% + Number of Slice Flip Flops: 14 out of 21504 0% + Number of 4 input LUTs: 101 out of 21504 0% Number of bonded IOBs: 37 out of 408 9% Number of GCLKs: 1 out of 16 6% @@ -254,16 +243,16 @@ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ -CLOCK | BUFGP | 16 | +CLOCK | BUFGP | 14 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -6 - Minimum period: 4.224ns (Maximum Frequency: 236.770MHz) - Minimum input arrival time before clock: 11.608ns - Maximum output required time after clock: 4.575ns + Minimum period: 4.024ns (Maximum Frequency: 248.509MHz) + Minimum input arrival time before clock: 11.651ns + Maximum output required time after clock: 4.880ns Maximum combinational path delay: No path found Timing Detail: @@ -272,36 +261,36 @@ ========================================================================= Timing constraint: Default period analysis for Clock 'CLOCK' - Clock period: 4.224ns (frequency: 236.770MHz) - Total number of paths / destination ports: 233 / 17 + Clock period: 4.024ns (frequency: 248.509MHz) + Total number of paths / destination ports: 125 / 18 ------------------------------------------------------------------------- -Delay: 4.224ns (Levels of Logic = 6) - Source: OUT_ADDRESS_0 (FF) +Delay: 4.024ns (Levels of Logic = 6) + Source: OUT_ADDRESS_0_1 (FF) Destination: DATA_OUT (FF) Source Clock: CLOCK rising Destination Clock: CLOCK rising - Data Path: OUT_ADDRESS_0 to DATA_OUT + Data Path: OUT_ADDRESS_0_1 to DATA_OUT Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDRE:C->Q 19 0.449 0.792 OUT_ADDRESS_0 (OUT_ADDRESS_0) - LUT3_L:I2->LO 1 0.347 0.000 OUT_ADDRESS<0>13 (MUX_BLOCK_N13) - MUXF5:I0->O 1 0.345 0.000 OUT_ADDRESS<1>_rn_5 (MUX_BLOCK_OUT_ADDRESS<1>_MUXF56) - MUXF6:I1->O 1 0.354 0.000 OUT_ADDRESS<2>_rn_2 (MUX_BLOCK_OUT_ADDRESS<2>_MUXF63) - MUXF7:I0->O 1 0.354 0.000 OUT_ADDRESS<3>_rn_0 (MUX_BLOCK_OUT_ADDRESS<3>_MUXF71) - MUXF8:I0->O 1 0.354 0.382 OUT_ADDRESS<4> (MUX_BLOCK_OUT_ADDRESS<4>_MUXF8) - MUXF5:S->O 1 0.553 0.000 _n0058<2>1111 (_n0036) + FDRE:C->Q 16 0.449 0.766 OUT_ADDRESS_0_1 (OUT_ADDRESS_0_1) + LUT3_L:I2->LO 1 0.347 0.000 OUT_ADDRESS<0>7 (MUX_BLOCK_N7) + MUXF5:I0->O 1 0.345 0.000 OUT_ADDRESS<1>_rn_2 (MUX_BLOCK_OUT_ADDRESS<1>_MUXF53) + MUXF6:I0->O 1 0.354 0.000 OUT_ADDRESS<2>_rn_0 (MUX_BLOCK_OUT_ADDRESS<2>_MUXF61) + MUXF7:I0->O 1 0.354 0.000 OUT_ADDRESS<3> (MUX_BLOCK_OUT_ADDRESS<3>_MUXF7) + MUXF8:I1->O 1 0.354 0.414 OUT_ADDRESS<4> (MUX_BLOCK_OUT_ADDRESS<4>_MUXF8) + LUT4_L:I3->LO 1 0.347 0.000 MODE12 (_n0036) FDRE:D 0.293 DATA_OUT ---------------------------------------- - Total 4.224ns (3.049ns logic, 1.174ns route) - (72.2% logic, 27.8% route) + Total 4.024ns (2.843ns logic, 1.181ns route) + (70.7% logic, 29.3% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' - Total number of paths / destination ports: 3250 / 29 + Total number of paths / destination ports: 3123 / 28 ------------------------------------------------------------------------- -Offset: 11.608ns (Levels of Logic = 14) +Offset: 11.651ns (Levels of Logic = 14) Source: DATA_IN<1> (PAD) Destination: LOG_0 (FF) Destination Clock: CLOCK rising @@ -313,49 +302,49 @@ IBUF:I->O 1 0.653 0.608 DATA_IN_1_IBUF (DATA_IN_1_IBUF) LUT1:I0->O 1 0.347 0.000 DATA_IN_1_IBUF_rt (DATA_IN_1_IBUF_rt) MUXCY:S->O 1 0.235 0.000 exp_golomb_counter_DATA2<1>cy (exp_golomb_counter_DATA2<1>_cyo) - XORCY:CI->O 3 0.824 0.701 exp_golomb_counter_DATA2<2>_xor (DATA2<2>) - LUT4:I1->O 1 0.347 0.410 _n0037<0>24 (CHOICE501) - LUT4:I2->O 1 0.347 0.608 _n0037<0>42 (CHOICE504) - LUT4:I0->O 1 0.347 0.410 _n0037<0>75 (CHOICE507) - LUT4:I2->O 1 0.347 0.608 _n0037<0>120 (CHOICE510) - LUT4:I0->O 1 0.347 0.410 _n0037<0>170 (CHOICE513) - LUT4:I2->O 1 0.347 0.608 _n0037<0>219 (CHOICE516) - LUT4:I0->O 1 0.347 0.410 _n0037<0>269 (CHOICE519) - LUT4:I2->O 1 0.347 0.607 _n0037<0>318 (CHOICE522) - LUT4:I0->O 1 0.347 0.410 _n0037<0>368 (CHOICE525) - LUT3:I2->O 1 0.347 0.000 _n0037<0>4171 (N375) - FDRS:D 0.293 LOG_0 + XORCY:CI->O 2 0.824 0.743 exp_golomb_counter_DATA2<2>_xor (DATA2<2>) + LUT4:I0->O 1 0.347 0.410 LOG__n000024 (CHOICE472) + LUT4:I2->O 1 0.347 0.608 LOG__n000042 (CHOICE475) + LUT4:I0->O 1 0.347 0.410 LOG__n000075 (CHOICE478) + LUT4:I2->O 1 0.347 0.608 LOG__n0000120 (CHOICE481) + LUT4:I0->O 1 0.347 0.410 LOG__n0000170 (CHOICE484) + LUT4:I2->O 1 0.347 0.608 LOG__n0000219 (CHOICE487) + LUT4:I0->O 1 0.347 0.410 LOG__n0000269 (CHOICE490) + LUT4:I2->O 1 0.347 0.607 LOG__n0000318 (CHOICE493) + LUT4:I0->O 1 0.347 0.410 LOG__n0000368 (CHOICE496) + LUT3:I2->O 1 0.347 0.000 LOG__n0000399 (N338) + FDS:D 0.293 LOG_0 ---------------------------------------- - Total 11.608ns (5.822ns logic, 5.786ns route) - (50.2% logic, 49.8% route) + Total 11.651ns (5.822ns logic, 5.829ns route) + (50.0% logic, 50.0% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' Total number of paths / destination ports: 2 / 2 ------------------------------------------------------------------------- -Offset: 4.575ns (Levels of Logic = 1) - Source: DATA_OUT (FF) - Destination: DATA_OUT (PAD) +Offset: 4.880ns (Levels of Logic = 1) + Source: OUTPUT_ACTIVE (FF) + Destination: COUNTING (PAD) Source Clock: CLOCK rising - Data Path: DATA_OUT to DATA_OUT + Data Path: OUTPUT_ACTIVE to COUNTING Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDRE:C->Q 1 0.449 0.383 DATA_OUT (DATA_OUT_OBUF) - OBUF:I->O 3.743 DATA_OUT_OBUF (DATA_OUT) + FDRE:C->Q 12 0.449 0.688 OUTPUT_ACTIVE (OUTPUT_ACTIVE) + OBUF:I->O 3.743 COUNTING_OBUF (COUNTING) ---------------------------------------- - Total 4.575ns (4.192ns logic, 0.383ns route) - (91.6% logic, 8.4% route) + Total 4.880ns (4.192ns logic, 0.688ns route) + (85.9% logic, 14.1% route) ========================================================================= -CPU : 7.20 / 9.72 s | Elapsed : 7.00 / 9.00 s +CPU : 6.00 / 6.36 s | Elapsed : 6.00 / 7.00 s --> Total memory usage is 121148 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 2 ( 0 filtered) -Number of infos : 0 ( 0 filtered) +Number of warnings : 1 ( 0 filtered) +Number of infos : 1 ( 0 filtered) 1.2 dirac/docs/synthesis_reports/expgolomb/exp_golomb_decoder.syr http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/expgolomb/exp_golomb_decoder.syr.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: exp_golomb_decoder.syr =================================================================== RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/expgolomb/exp_golomb_decoder.syr,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- exp_golomb_decoder.syr 6 Sep 2006 18:41:03 -0000 1.1 +++ exp_golomb_decoder.syr 19 Sep 2006 12:12:10 -0000 1.2 @@ -1,10 +1,10 @@ Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav -CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 2.38 s | Elapsed : 0.00 / 2.00 s --> Parameter xsthdpdir set to ./xst -CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 2.38 s | Elapsed : 0.00 / 2.00 s --> Reading design: exp_golomb_decoder.prj @@ -112,19 +112,14 @@ Synthesizing Unit <exp_golomb_decoder>. Related source file is "C:/Xilinx/bin/exp-golomb-decoder/EXP_GOLOMB_DECODER.vhd". - Found 5-bit comparator equal for signal <$n0005> created at line 83. - Found 32-bit register for signal <DATA_1>. - Found 32-bit register for signal <DATA_2>. - Found 32-bit register for signal <DATA_STORE>. + Found 32-bit register for signal <DATA_OUT>. + Found 32-bit subtractor for signal <$n0005> created at line 62. + Found 1-bit register for signal <CALC_COMPLETE>. + Found 32-bit register for signal <DATA>. Found 1-bit register for signal <MODE>. - Found 5-bit up counter for signal <NUMBITS_1>. - Found 5-bit up counter for signal <NUMBITS_2>. - Found 32-bit adder for signal <SUM>. Summary: - inferred 2 Counter(s). - inferred 97 D-type flip-flop(s). + inferred 34 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). - inferred 1 Comparator(s). Unit <exp_golomb_decoder> synthesized. @@ -142,14 +137,10 @@ Macro Statistics # Adders/Subtractors : 1 - 32-bit adder : 1 -# Counters : 2 - 5-bit up counter : 2 -# Registers : 66 - 1-bit register : 65 - 32-bit register : 1 -# Comparators : 1 - 5-bit comparator equal : 1 + 32-bit subtractor : 1 +# Registers : 4 + 1-bit register : 2 + 32-bit register : 2 ========================================================================= @@ -163,6 +154,7 @@ Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block exp_golomb_decoder, actual ratio is 0. +FlipFlop CALC_COMPLETE has been replicated 1 time(s) to handle iob=true attribute. ========================================================================= * Final Report * @@ -178,31 +170,26 @@ # IOs : 37 Macro Statistics : -# Registers : 68 -# 1-bit register : 65 +# Registers : 35 +# 1-bit register : 34 # 32-bit register : 1 -# 5-bit register : 2 # Adders/Subtractors : 1 -# 32-bit adder : 1 -# Comparators : 1 -# 5-bit comparator equal : 1 +# 32-bit subtractor : 1 Cell Usage : -# BELS : 159 +# BELS : 134 # GND : 1 -# INV : 2 -# LUT2 : 4 -# LUT2_L : 33 -# LUT3 : 40 -# LUT3_D : 1 -# LUT4 : 11 -# LUT4_D : 2 -# LUT4_L : 2 +# INV : 32 +# LUT1_L : 1 +# LUT2 : 34 +# LUT3 : 1 +# LUT4 : 1 # MUXCY : 31 # VCC : 1 -# XORCY : 31 -# FlipFlops/Latches : 107 -# FDRE : 107 +# XORCY : 32 +# FlipFlops/Latches : 67 +# FDRE : 66 +# FDSE : 1 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 36 @@ -215,9 +202,9 @@ Selected Device : 2v2000bg575-6 - Number of Slices: 64 out of 10752 0% - Number of Slice Flip Flops: 107 out of 21504 0% - Number of 4 input LUTs: 93 out of 21504 0% + Number of Slices: 37 out of 10752 0% + Number of Slice Flip Flops: 67 out of 21504 0% + Number of 4 input LUTs: 37 out of 21504 0% Number of bonded IOBs: 37 out of 408 9% Number of GCLKs: 1 out of 16 6% @@ -234,16 +221,16 @@ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ -CLOCK | BUFGP | 107 | +CLOCK | BUFGP | 67 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -6 - Minimum period: 4.169ns (Maximum Frequency: 239.894MHz) - Minimum input arrival time before clock: 2.955ns - Maximum output required time after clock: 8.894ns + Minimum period: 4.152ns (Maximum Frequency: 240.877MHz) + Minimum input arrival time before clock: 2.790ns + Maximum output required time after clock: 4.575ns Maximum combinational path delay: No path found Timing Detail: @@ -252,133 +239,99 @@ ========================================================================= Timing constraint: Default period analysis for Clock 'CLOCK' - Clock period: 4.169ns (frequency: 239.894MHz) - Total number of paths / destination ports: 2896 / 286 + Clock period: 4.152ns (frequency: 240.877MHz) + Total number of paths / destination ports: 725 / 134 ------------------------------------------------------------------------- -Delay: 4.169ns (Levels of Logic = 33) - Source: DATA_1_0 (FF) - Destination: DATA_STORE_31 (FF) +Delay: 4.152ns (Levels of Logic = 33) + Source: DATA_0 (FF) + Destination: DATA_OUT_31 (FF) Source Clock: CLOCK rising Destination Clock: CLOCK rising - Data Path: DATA_1_0 to DATA_STORE_31 + Data Path: DATA_0 to DATA_OUT_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDRE:C->Q 3 0.449 0.760 DATA_1_0 (DATA_1_0) - LUT2_L:I0->LO 2 0.347 0.000 exp_golomb_decoder_SUM<0>lut (SUM<0>) - MUXCY:S->O 1 0.235 0.000 exp_golomb_decoder_SUM<0>cy (exp_golomb_decoder_SUM<0>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<1>cy (exp_golomb_decoder_SUM<1>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<2>cy (exp_golomb_decoder_SUM<2>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<3>cy (exp_golomb_decoder_SUM<3>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<4>cy (exp_golomb_decoder_SUM<4>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<5>cy (exp_golomb_decoder_SUM<5>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<6>cy (exp_golomb_decoder_SUM<6>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<7>cy (exp_golomb_decoder_SUM<7>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<8>cy (exp_golomb_decoder_SUM<8>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<9>cy (exp_golomb_decoder_SUM<9>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<10>cy (exp_golomb_decoder_SUM<10>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<11>cy (exp_golomb_decoder_SUM<11>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<12>cy (exp_golomb_decoder_SUM<12>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<13>cy (exp_golomb_decoder_SUM<13>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<14>cy (exp_golomb_decoder_SUM<14>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<15>cy (exp_golomb_decoder_SUM<15>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<16>cy (exp_golomb_decoder_SUM<16>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<17>cy (exp_golomb_decoder_SUM<17>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<18>cy (exp_golomb_decoder_SUM<18>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<19>cy (exp_golomb_decoder_SUM<19>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<20>cy (exp_golomb_decoder_SUM<20>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<21>cy (exp_golomb_decoder_SUM<21>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<22>cy (exp_golomb_decoder_SUM<22>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<23>cy (exp_golomb_decoder_SUM<23>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<24>cy (exp_golomb_decoder_SUM<24>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<25>cy (exp_golomb_decoder_SUM<25>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<26>cy (exp_golomb_decoder_SUM<26>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<27>cy (exp_golomb_decoder_SUM<27>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<28>cy (exp_golomb_decoder_SUM<28>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<29>cy (exp_golomb_decoder_SUM<29>_cyo) - MUXCY:CI->O 0 0.042 0.000 exp_golomb_decoder_SUM<30>cy (exp_golomb_decoder_SUM<30>_cyo) - XORCY:CI->O 2 0.824 0.000 exp_golomb_decoder_SUM<31>_xor (SUM<31>) - FDRE:D 0.293 DATA_STORE_31 + FDSE:C->Q 2 0.449 0.743 DATA_0 (DATA_0) + LUT1_L:I0->LO 1 0.347 0.000 DATA_0_rt (DATA_0_rt) + MUXCY:S->O 1 0.235 0.000 exp_golomb_decoder__n0005<0>cy (exp_golomb_decoder__n0005<0>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<1>cy (exp_golomb_decoder__n0005<1>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<2>cy (exp_golomb_decoder__n0005<2>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<3>cy (exp_golomb_decoder__n0005<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<4>cy (exp_golomb_decoder__n0005<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<5>cy (exp_golomb_decoder__n0005<5>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<6>cy (exp_golomb_decoder__n0005<6>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<7>cy (exp_golomb_decoder__n0005<7>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<8>cy (exp_golomb_decoder__n0005<8>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<9>cy (exp_golomb_decoder__n0005<9>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<10>cy (exp_golomb_decoder__n0005<10>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<11>cy (exp_golomb_decoder__n0005<11>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<12>cy (exp_golomb_decoder__n0005<12>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<13>cy (exp_golomb_decoder__n0005<13>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<14>cy (exp_golomb_decoder__n0005<14>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<15>cy (exp_golomb_decoder__n0005<15>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<16>cy (exp_golomb_decoder__n0005<16>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<17>cy (exp_golomb_decoder__n0005<17>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<18>cy (exp_golomb_decoder__n0005<18>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<19>cy (exp_golomb_decoder__n0005<19>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<20>cy (exp_golomb_decoder__n0005<20>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<21>cy (exp_golomb_decoder__n0005<21>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<22>cy (exp_golomb_decoder__n0005<22>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<23>cy (exp_golomb_decoder__n0005<23>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<24>cy (exp_golomb_decoder__n0005<24>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<25>cy (exp_golomb_decoder__n0005<25>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<26>cy (exp_golomb_decoder__n0005<26>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<27>cy (exp_golomb_decoder__n0005<27>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<28>cy (exp_golomb_decoder__n0005<28>_cyo) + MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder__n0005<29>cy (exp_golomb_decoder__n0005<29>_cyo) + MUXCY:CI->O 0 0.042 0.000 exp_golomb_decoder__n0005<30>cy (exp_golomb_decoder__n0005<30>_cyo) + XORCY:CI->O 1 0.824 0.000 exp_golomb_decoder__n0005<31>_xor (_n0005<31>) + FDRE:D 0.293 DATA_OUT_31 ---------------------------------------- - Total 4.169ns (3.408ns logic, 0.760ns route) - (81.8% logic, 18.2% route) + Total 4.152ns (3.408ns logic, 0.743ns route) + (82.1% logic, 17.9% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' - Total number of paths / destination ports: 221 / 183 + Total number of paths / destination ports: 169 / 137 ------------------------------------------------------------------------- -Offset: 2.955ns (Levels of Logic = 2) +Offset: 2.790ns (Levels of Logic = 2) Source: RESET (PAD) - Destination: DATA_2_9 (FF) + Destination: CALC_COMPLETE (FF) Destination Clock: CLOCK rising - Data Path: RESET to DATA_2_9 + Data Path: RESET to CALC_COMPLETE Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUF:I->O 40 0.653 1.044 RESET_IBUF (RESET_IBUF) - LUT4:I0->O 12 0.347 0.689 _n00021_7 (_n000216) - FDRE:R 0.222 DATA_2_9 + IBUF:I->O 65 0.653 1.032 RESET_IBUF (RESET_IBUF) + LUT2:I1->O 3 0.347 0.535 _n00021 (_n0002) + FDRE:R 0.222 MODE ---------------------------------------- - Total 2.955ns (1.222ns logic, 1.733ns route) - (41.4% logic, 58.6% route) + Total 2.790ns (1.222ns logic, 1.568ns route) + (43.8% logic, 56.2% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' - Total number of paths / destination ports: 1947 / 33 + Total number of paths / destination ports: 33 / 33 ------------------------------------------------------------------------- -Offset: 8.894ns (Levels of Logic = 35) - Source: DATA_1_0 (FF) - Destination: DATA_OUT<31> (PAD) +Offset: 4.575ns (Levels of Logic = 1) + Source: CALC_COMPLETE_1 (FF) + Destination: READY (PAD) Source Clock: CLOCK rising - Data Path: DATA_1_0 to DATA_OUT<31> + Data Path: CALC_COMPLETE_1 to READY Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDRE:C->Q 3 0.449 0.760 DATA_1_0 (DATA_1_0) - LUT2_L:I0->LO 2 0.347 0.000 exp_golomb_decoder_SUM<0>lut (SUM<0>) - MUXCY:S->O 1 0.235 0.000 exp_golomb_decoder_SUM<0>cy (exp_golomb_decoder_SUM<0>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<1>cy (exp_golomb_decoder_SUM<1>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<2>cy (exp_golomb_decoder_SUM<2>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<3>cy (exp_golomb_decoder_SUM<3>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<4>cy (exp_golomb_decoder_SUM<4>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<5>cy (exp_golomb_decoder_SUM<5>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<6>cy (exp_golomb_decoder_SUM<6>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<7>cy (exp_golomb_decoder_SUM<7>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<8>cy (exp_golomb_decoder_SUM<8>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<9>cy (exp_golomb_decoder_SUM<9>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<10>cy (exp_golomb_decoder_SUM<10>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<11>cy (exp_golomb_decoder_SUM<11>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<12>cy (exp_golomb_decoder_SUM<12>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<13>cy (exp_golomb_decoder_SUM<13>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<14>cy (exp_golomb_decoder_SUM<14>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<15>cy (exp_golomb_decoder_SUM<15>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<16>cy (exp_golomb_decoder_SUM<16>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<17>cy (exp_golomb_decoder_SUM<17>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<18>cy (exp_golomb_decoder_SUM<18>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<19>cy (exp_golomb_decoder_SUM<19>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<20>cy (exp_golomb_decoder_SUM<20>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<21>cy (exp_golomb_decoder_SUM<21>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<22>cy (exp_golomb_decoder_SUM<22>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<23>cy (exp_golomb_decoder_SUM<23>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<24>cy (exp_golomb_decoder_SUM<24>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<25>cy (exp_golomb_decoder_SUM<25>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<26>cy (exp_golomb_decoder_SUM<26>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<27>cy (exp_golomb_decoder_SUM<27>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<28>cy (exp_golomb_decoder_SUM<28>_cyo) - MUXCY:CI->O 1 0.042 0.000 exp_golomb_decoder_SUM<29>cy (exp_golomb_decoder_SUM<29>_cyo) - MUXCY:CI->O 0 0.042 0.000 exp_golomb_decoder_SUM<30>cy (exp_golomb_decoder_SUM<30>_cyo) - XORCY:CI->O 2 0.824 0.546 exp_golomb_decoder_SUM<31>_xor (SUM<31>) - LUT3:I2->O 1 0.347 0.383 DATA_OUT<31>1 (DATA_OUT_31_OBUF) - OBUF:I->O 3.743 DATA_OUT_31_OBUF (DATA_OUT<31>) + FDRE:C->Q 1 0.449 0.383 CALC_COMPLETE_1 (CALC_COMPLETE_1) + OBUF:I->O 3.743 READY_OBUF (READY) ---------------------------------------- - Total 8.894ns (7.205ns logic, 1.689ns route) - (81.0% logic, 19.0% route) + Total 4.575ns (4.192ns logic, 0.383ns route) + (91.6% logic, 8.4% route) ========================================================================= -CPU : 6.84 / 7.22 s | Elapsed : 7.00 / 7.00 s +CPU : 6.19 / 8.66 s | Elapsed : 7.00 / 9.00 s -->

     
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