OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Tue Sep 19 14:12:08 CEST 2006
Subject: [cvs-checkins] MODIFIED: dirac ...

Date: 00/06/09 19:14:12

Modified: dirac/docs/synthesis_reports/decoder arithmeticdecoder.syr storage_register.syr symbol_detector.syr Log: Adjusted bitwidths and exp-golomb data format to be compatible with the Dirac Specification and software version 0.6.0. Updated test datasets and synthesis reports accordingly. Arithmetic coding and decoding are now COMPLETE. Revision Changes Path 1.2 dirac/docs/synthesis_reports/decoder/arithmeticdecoder.syr http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/decoder/arithmeticdecoder.syr.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: arithmeticdecoder.syr =================================================================== RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/decoder/arithmeticdecoder.syr,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- arithmeticdecoder.syr 6 Sep 2006 18:41:02 -0000 1.1 +++ arithmeticdecoder.syr 19 Sep 2006 12:12:07 -0000 1.2 @@ -1,10 +1,10 @@ Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav -CPU : 0.00 / 2.34 s | Elapsed : 0.00 / 2.00 s +CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst -CPU : 0.00 / 2.34 s | Elapsed : 0.00 / 2.00 s +CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 1.00 s --> Reading design: arithmeticdecoder.prj @@ -32,7 +32,7 @@ ---- Target Parameters Output File Name : "arithmeticdecoder" Output Format : NGC -Target Device : xc2v250-6-cs144 +Target Device : xc2v2000-6-bf957 ---- Source Options Top Module Name : arithmeticdecoder @@ -95,30 +95,30 @@ ========================================================================= * HDL Compilation * ========================================================================= -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" in Library work. -Architecture rtl of Entity divider is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd" in Library work. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/Divider.vhd" in Library work. +Entity <divider> compiled. +Entity <divider> (Architecture <rtl>) compiled. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/UPDATER.vhd" in Library work. Architecture rtl of Entity updater is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" in Library work. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" in Library work. Architecture rtl of Entity halving_manager is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd" in Library work. -Architecture rtl of Entity fifo is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/INPUT_CONTROL.vhd" in Library work. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/FIFO.vhd" in Library work. +Entity <fifo> compiled. +Entity <fifo> (Architecture <rtl>) compiled. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/INPUT_CONTROL.vhd" in Library work. Architecture rtl of Entity input_control is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work. Architecture rtl of Entity context_manager is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/STORAGE_REGISTER.vhd" in Library work. -Entity <storage_register> compiled. -Entity <storage_register> (Architecture <rtl>) compiled. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd" in Library work. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/STORAGE_REGISTER.vhd" in Library work. +Architecture rtl of Entity storage_register is up to date. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd" in Library work. Architecture rtl of Entity arithmetic_unit is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/CONVERGENCE_CHECK.vhd" in Library work. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/CONVERGENCE_CHECK.vhd" in Library work. Architecture rtl of Entity convergence_check is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/SYMBOL_DETECTOR.vhd" in Library work. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/SYMBOL_DETECTOR.vhd" in Library work. Architecture rtl of Entity symbol_detector is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/ARITHMETICDECODER.vhd" in Library work. -Entity <arithmeticdecoder> compiled. -Entity <arithmeticdecoder> (Architecture <rtl>) compiled. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/ARITHMETICDECODER.vhd" in Library work. +Architecture rtl of Entity arithmeticdecoder is up to date. ========================================================================= * HDL Analysis * @@ -136,22 +136,25 @@ Entity <FIFO> analyzed. Unit <FIFO> generated. Analyzing Entity <CONTEXT_MANAGER> (Architecture <rtl>). -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 118: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 141: Index value(s) does not match array range, simulation mismatch. Entity <CONTEXT_MANAGER> analyzed. Unit <CONTEXT_MANAGER> generated. Analyzing Entity <DIVIDER> (Architecture <rtl>). -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/Divider.vhd" line 308: Index value(s) does not match array range, simulation mismatch. Entity <DIVIDER> analyzed. Unit <DIVIDER> generated. Analyzing Entity <UPDATER> (Architecture <rtl>). Entity <UPDATER> analyzed. Unit <UPDATER> generated. Analyzing Entity <HALVING_MANAGER> (Architecture <rtl>). -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:1610 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" line 78: Width mismatch. <NUMERATOR2> has a width of 8 bits but assigned expression is 10-bit wide. +WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch. Entity <HALVING_MANAGER> analyzed. Unit <HALVING_MANAGER> generated. Analyzing Entity <STORAGE_REGISTER> (Architecture <rtl>). @@ -172,7 +175,7 @@ ========================================================================= Synthesizing Unit <HALVING_MANAGER>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd". + Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd". Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108. Found 3-bit 4-to-1 multiplexer for signal <$n0050>. Found 3-bit 4-to-1 multiplexer for signal <$n0051>. @@ -266,13 +269,13 @@ Found 3-bit addsub for signal <$n0142>. Found 3-bit addsub for signal <$n0143>. Found 3-bit addsub for signal <$n0144>. - Found 10-bit comparator greater for signal <$n0147> created at line 99. + Found 8-bit comparator greater for signal <$n0147> created at line 99. Found 3-bit comparator greater for signal <$n0241> created at line 108. Found 1-bit register for signal <AFTER_TRIGGER>. - Found 10-bit register for signal <DENOMINATOR>. - Found 10-bit adder for signal <DENOMINATOR2>. - Found 10-bit register for signal <NUMERATOR>. - Found 10-bit adder for signal <NUMERATOR2>. + Found 8-bit register for signal <DENOMINATOR>. + Found 8-bit adder for signal <DENOMINATOR2>. + Found 8-bit register for signal <NUMERATOR>. + Found 8-bit adder for signal <NUMERATOR2>. Found 138-bit register for signal <SHIFTS>. Summary: inferred 139 D-type flip-flop(s). @@ -283,51 +286,48 @@ Synthesizing Unit <UPDATER>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd". + Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/UPDATER.vhd". WARNING:Xst:1780 - Signal <HALVING_ALLOWED> is never used or assigned. Found 1-bit register for signal <UPDATE>. - Found 10-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>. - Found 10-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>. - Found 10-bit adder for signal <$n0009> created at line 51. - Found 10-bit adder for signal <$n0011> created at line 73. - Found 10-bit adder for signal <$n0012> created at line 84. - Found 10-bit adder for signal <$n0013> created at line 62. - Found 10-bit register for signal <DENOMINATOR2>. - Found 10-bit register for signal <NUMERATOR1>. - Found 10-bit register for signal <NUMERATOR2>. - Found 10-bit register for signal <NUMERATOR3>. - Found 10-bit register for signal <NUMERATOR4>. + Found 8-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>. + Found 8-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>. + Found 8-bit adder for signal <$n0009> created at line 51. + Found 8-bit adder for signal <$n0011> created at line 73. + Found 8-bit adder for signal <$n0012> created at line 84. + Found 8-bit adder for signal <$n0013> created at line 62. + Found 8-bit register for signal <DENOMINATOR2>. + Found 8-bit register for signal <NUMERATOR1>. + Found 8-bit register for signal <NUMERATOR2>. + Found 8-bit register for signal <NUMERATOR3>. + Found 8-bit register for signal <NUMERATOR4>. Found 1-bit xor2 for signal <UPDATE_SWITCH>. Summary: inferred 1 D-type flip-flop(s). inferred 4 Adder/Subtractor(s). - inferred 20 Multiplexer(s). + inferred 16 Multiplexer(s). Unit <UPDATER> synthesized. Synthesizing Unit <DIVIDER>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd". -WARNING:Xst:646 - Signal <TOTAL<41:32>> is assigned but never used. -WARNING:Xst:646 - Signal <TOTAL<21:0>> is assigned but never used. - Found 1022x32-bit ROM for signal <$n0002> created at line 1079. - Found 16x10-bit multiplier for signal <$n0003> created at line 1086. - Found 16x10-bit multiplier for signal <$n0004> created at line 1093. - Found 10-bit subtractor for signal <INDEX>. - Found 10-bit register for signal <NUMERATOR2>. - Found 26-bit register for signal <PRODUCT1>. - Found 26-bit register for signal <PRODUCT2>. - Found 32-bit register for signal <RECIPROCAL>. - Found 42-bit adder for signal <TOTAL>. + Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/Divider.vhd". +WARNING:Xst:646 - Signal <PRODUCT<23:16>> is assigned but never used. +WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used. + Found 254x16-bit ROM for signal <$n0002> created at line 308. + Found 16x8-bit multiplier for signal <$n0003> created at line 315. + Found 8-bit subtractor for signal <INDEX>. + Found 8-bit register for signal <NUMERATOR2>. + Found 24-bit register for signal <PRODUCT>. + Found 16-bit register for signal <RECIPROCAL>. Summary: inferred 1 ROM(s). - inferred 84 D-type flip-flop(s). - inferred 2 Adder/Subtractor(s). - inferred 2 Multiplier(s). + inferred 40 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 1 Multiplier(s). Unit <DIVIDER> synthesized. Synthesizing Unit <FIFO>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd". + Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/FIFO.vhd". Found 256x1-bit dual-port distributed RAM for signal <GET_OUTPUT>. ----------------------------------------------------------------------- | aspect ratio | 256-word x 1-bit | | @@ -352,7 +352,7 @@ Synthesizing Unit <SYMBOL_DETECTOR>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/SYMBOL_DETECTOR.vhd". + Related source file is "c:/xilinx/bin/arithmeticdecoder/SYMBOL_DETECTOR.vhd". Found 16-bit comparator greatequal for signal <$n0001> created at line 23. Summary: inferred 1 Comparator(s). @@ -360,35 +360,35 @@ Synthesizing Unit <CONVERGENCE_CHECK>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/CONVERGENCE_CHECK.vhd". + Related source file is "c:/xilinx/bin/arithmeticdecoder/CONVERGENCE_CHECK.vhd". Unit <CONVERGENCE_CHECK> synthesized. Synthesizing Unit <ARITHMETIC_UNIT>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd". -WARNING:Xst:646 - Signal <PRODUCT<9:0>> is assigned but never used. + Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd". +WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used. WARNING:Xst:646 - Signal <DIFFERENCE3<16>> is assigned but never used. WARNING:Xst:646 - Signal <DIFFERENCE4<16>> is assigned but never used. WARNING:Xst:646 - Signal <RESULT0<16>> is assigned but never used. - Found 17x10-bit multiplier for signal <$n0000> created at line 48. + Found 17x8-bit multiplier for signal <$n0000> created at line 48. Found 1-bit register for signal <DELAY1>. Found 17-bit register for signal <DIFFERENCE1>. Found 17-bit adder for signal <DIFFERENCE2>. Found 17-bit subtractor for signal <DIFFERENCE3>. Found 17-bit subtractor for signal <DIFFERENCE4>. Found 17-bit register for signal <LOW2>. - Found 27-bit register for signal <PRODUCT>. + Found 25-bit register for signal <PRODUCT>. Found 17-bit adder for signal <RESULT>. Found 17-bit subtractor for signal <RESULT0>. Summary: - inferred 62 D-type flip-flop(s). + inferred 60 D-type flip-flop(s). inferred 5 Adder/Subtractor(s). inferred 1 Multiplier(s). Unit <ARITHMETIC_UNIT> synthesized. Synthesizing Unit <STORAGE_REGISTER>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/STORAGE_REGISTER.vhd". + Related source file is "c:/xilinx/bin/arithmeticdecoder/STORAGE_REGISTER.vhd". Found 16-bit 4-to-1 multiplexer for signal <$n0001>. Found 16-bit register for signal <Q>. Summary: @@ -398,11 +398,11 @@ Synthesizing Unit <CONTEXT_MANAGER>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd". - Found 46x20-bit dual-port block RAM for signal <PROBABILITY>. + Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd". + Found 46x16-bit dual-port block RAM for signal <PROBABILITY>. ----------------------------------------------------------------------- | mode | write-first | | - | aspect ratio | 46-word x 20-bit | | + | aspect ratio | 46-word x 16-bit | | | clock | connected to signal <CLOCK> | rise | | dual clock | connected to signal <CLOCK> | rise | | dual enable | connected to signal <SET> | high | @@ -414,21 +414,21 @@ | dual data out | connected to signal <RATIO> | | | ram_style | Auto | | ----------------------------------------------------------------------- - Found 1-bit 64-to-1 multiplexer for signal <$n0003> created at line 141. + Found 1-bit 46-to-1 multiplexer for signal <$n0003> created at line 141. Found 1-bit register for signal <CONTEXT_VALID>. Found 2-bit register for signal <DATA_READY>. Found 6-bit register for signal <OLD_CONTEXT>. Found 6-bit register for signal <READ_ADDRESS>. - Found 64-bit register for signal <RESET_FLAGS>. + Found 46-bit register for signal <RESET_FLAGS>. Summary: inferred 1 RAM(s). - inferred 79 D-type flip-flop(s). + inferred 61 D-type flip-flop(s). inferred 1 Multiplexer(s). Unit <CONTEXT_MANAGER> synthesized. Synthesizing Unit <INPUT_CONTROL>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/INPUT_CONTROL.vhd". + Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/INPUT_CONTROL.vhd". Found 1-bit register for signal <HELD<0>>. Found 1-bit 4-to-1 multiplexer for signal <OUTPUT<0>>. Summary: @@ -438,7 +438,7 @@ Synthesizing Unit <arithmeticdecoder>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/ARITHMETICDECODER.vhd". + Related source file is "c:/xilinx/bin/arithmeticdecoder/ARITHMETICDECODER.vhd". WARNING:Xst:646 - Signal <HIGH_VALUE<13:0>> is assigned but never used. Unit <arithmeticdecoder> synthesized. @@ -458,9 +458,6 @@ Found registered multiplier on signal <_n0003>: - 1 register level(s) found in a register connected to the multiplier macro ouput. Pushing register(s) into the multiplier macro. - Found registered multiplier on signal <_n0004>: - - 1 register level(s) found in a register connected to the multiplier macro ouput. - Pushing register(s) into the multiplier macro. Advanced Registered AddSub inference ... Dynamic shift register inference ... @@ -469,41 +466,40 @@ Macro Statistics # Block RAMs : 2 - 1022x32-bit single-port block RAM : 1 - 46x20-bit dual-port block RAM : 1 + 254x16-bit single-port block RAM : 1 + 46x16-bit dual-port block RAM : 1 # LUT RAMs : 1 256x1-bit dual-port distributed RAM: 1 -# Multipliers : 3 - 16x10-bit registered multiplier : 2 - 17x10-bit registered multiplier : 1 -# Adders/Subtractors : 59 - 10-bit adder : 6 - 10-bit subtractor : 1 +# Multipliers : 2 + 16x8-bit registered multiplier : 1 + 17x8-bit registered multiplier : 1 +# Adders/Subtractors : 58 17-bit adder : 2 17-bit subtractor : 3 3-bit addsub : 46 - 42-bit adder : 1 + 8-bit adder : 6 + 8-bit subtractor : 1 # Counters : 2 8-bit up counter : 2 -# Registers : 133 - 1-bit register : 71 - 10-bit register : 8 +# Registers : 115 + 1-bit register : 53 16-bit register : 4 17-bit register : 2 3-bit register : 46 6-bit register : 2 + 8-bit register : 8 # Comparators : 4 - 10-bit comparator greater : 1 16-bit comparator greatequal : 1 3-bit comparator greater : 1 8-bit comparator equal : 1 + 8-bit comparator greater : 1 # Multiplexers : 55 1-bit 4-to-1 multiplexer : 1 - 1-bit 64-to-1 multiplexer : 1 - 10-bit 4-to-1 multiplexer : 2 + 1-bit 46-to-1 multiplexer : 1 16-bit 4-to-1 multiplexer : 4 3-bit 4-to-1 multiplexer : 46 3-bit 46-to-1 multiplexer : 1 + 8-bit 4-to-1 multiplexer : 2 # Xors : 1 1-bit xor2 : 1 @@ -533,23 +529,20 @@ Optimizing unit <FIFO> ... Optimizing unit <ARITHMETIC_UNIT> ... -Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... Register <PROBABILITY_PROBUPDATE_UPDATE> equivalent to <PROBABILITY_DATA_READY_0> has been removed +Register <PROBABILITY_DIVISION_NUMERATOR2_5> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_5> has been removed Register <PROBABILITY_DIVISION_NUMERATOR2_7> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_7> has been removed -Register <PROBABILITY_DIVISION_NUMERATOR2_9> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_9> has been removed -Register <PROBABILITY_DIVISION_NUMERATOR2_8> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_8> has been removed +Register <PROBABILITY_DIVISION_NUMERATOR2_6> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_6> has been removed Register <PROBABILITY_DIVISION_NUMERATOR2_0> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_0> has been removed Register <PROBABILITY_DIVISION_NUMERATOR2_1> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_1> has been removed Register <PROBABILITY_DIVISION_NUMERATOR2_2> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_2> has been removed Register <PROBABILITY_DIVISION_NUMERATOR2_3> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_3> has been removed Register <PROBABILITY_DIVISION_NUMERATOR2_4> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_4> has been removed -Register <PROBABILITY_DIVISION_NUMERATOR2_5> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_5> has been removed -Register <PROBABILITY_DIVISION_NUMERATOR2_6> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_6> has been removed -Found area constraint ratio of 100 (+ 5) on block arithmeticdecoder, actual ratio is 33. -FlipFlop PROBABILITY_READ_ADDRESS_0 has been replicated 3 time(s) +Found area constraint ratio of 100 (+ 5) on block arithmeticdecoder, actual ratio is 4. ========================================================================= * Final Report * @@ -566,11 +559,11 @@ Macro Statistics : # RAM : 3 -# 1022x32-bit single-port block RAM: 1 +# 254x16-bit single-port block RAM: 1 # 256x1-bit dual-port distributed RAM: 1 -# 46x20-bit dual-port block RAM: 1 -# Registers : 207 -# 1-bit register : 151 +# 46x16-bit dual-port block RAM: 1 +# Registers : 173 +# 1-bit register : 117 # 16-bit register : 4 # 17-bit register : 2 # 3-bit register : 46 @@ -578,83 +571,81 @@ # 8-bit register : 2 # Multiplexers : 55 # 1-bit 4-to-1 multiplexer : 1 -# 1-bit 64-to-1 multiplexer : 1 -# 10-bit 4-to-1 multiplexer : 2 +# 1-bit 46-to-1 multiplexer : 1 # 16-bit 4-to-1 multiplexer : 4 # 3-bit 4-to-1 multiplexer : 46 # 3-bit 46-to-1 multiplexer : 1 -# Adders/Subtractors : 15 -# 10-bit adder : 6 -# 10-bit subtractor : 1 +# 8-bit 4-to-1 multiplexer : 2 +# Adders/Subtractors : 14 # 17-bit adder : 2 # 17-bit subtractor : 3 -# 42-bit adder : 1 -# 8-bit adder : 2 -# Multipliers : 3 -# 16x10-bit registered multiplier: 2 -# 17x10-bit registered multiplier: 1 +# 8-bit adder : 8 +# 8-bit subtractor : 1 +# Multipliers : 2 +# 16x8-bit registered multiplier: 1 +# 17x8-bit registered multiplier: 1 # Comparators : 4 -# 10-bit comparator greater : 1 # 16-bit comparator greatequal: 1 # 3-bit comparator greater : 1 # 8-bit comparator equal : 1 +# 8-bit comparator greater : 1 # Xors : 92 # 1-bit xor3 : 92 Cell Usage : -# BELS : 1384 +# BELS : 1220 # GND : 1 # INV : 34 -# LUT1 : 31 -# LUT1_L : 28 +# LUT1 : 30 +# LUT1_L : 18 # LUT2 : 40 # LUT2_D : 1 -# LUT2_L : 41 -# LUT3 : 109 -# LUT3_D : 4 -# LUT3_L : 154 -# LUT4 : 332 -# LUT4_D : 26 -# LUT4_L : 72 -# MUXCY : 187 -# MUXF5 : 123 -# MUXF6 : 23 -# MUXF7 : 10 -# MUXF8 : 5 +# LUT2_L : 31 +# LUT3 : 67 +# LUT3_D : 3 +# LUT3_L : 124 +# LUT4 : 287 +# LUT4_D : 14 +# LUT4_L : 139 +# MUXCY : 152 +# MUXF5 : 116 +# MUXF6 : 19 +# MUXF7 : 8 +# MUXF8 : 4 # VCC : 1 -# XORCY : 162 -# FlipFlops/Latches : 405 +# XORCY : 131 +# FlipFlops/Latches : 370 # FD : 6 -# FDE : 41 -# FDR : 49 -# FDRE : 237 +# FDE : 38 +# FDR : 39 +# FDRE : 233 # FDRSE : 1 # FDS : 5 -# FDSE : 66 -# RAMS : 7 +# FDSE : 48 +# RAMS : 6 # RAM64X1D : 4 -# RAMB16_S18 : 2 +# RAMB16_S36 : 1 # RAMB16_S36_S36 : 1 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 13 # IBUF : 11 # OBUF : 2 -# MULTs : 3 -# MULT18X18S : 3 +# MULTs : 2 +# MULT18X18S : 2 ========================================================================= Device utilization summary: --------------------------- -Selected Device : 2v250cs144-6 +Selected Device : 2v2000bf957-6 - Number of Slices: 490 out of 1536 31% - Number of Slice Flip Flops: 405 out of 3072 13% - Number of 4 input LUTs: 854 out of 3072 27% - Number of bonded IOBs: 14 out of 92 15% - Number of BRAMs: 3 out of 24 12% - Number of MULT18X18s: 3 out of 24 12% + Number of Slices: 447 out of 10752 4% + Number of Slice Flip Flops: 370 out of 21504 1% + Number of 4 input LUTs: 770 out of 21504 3% + Number of bonded IOBs: 14 out of 624 2% + Number of BRAMs: 2 out of 56 3% + Number of MULT18X18s: 2 out of 56 3% Number of GCLKs: 1 out of 16 6% @@ -670,16 +661,16 @@ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ -CLOCK | BUFGP | 413 | +CLOCK | BUFGP | 377 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -6 - Minimum period: 9.680ns (Maximum Frequency: 103.303MHz) - Minimum input arrival time before clock: 10.225ns - Maximum output required time after clock: 11.576ns + Minimum period: 9.935ns (Maximum Frequency: 100.654MHz) + Minimum input arrival time before clock: 10.481ns + Maximum output required time after clock: 11.374ns Maximum combinational path delay: No path found Timing Detail: @@ -688,101 +679,111 @@ ========================================================================= Timing constraint: Default period analysis for Clock 'CLOCK' - Clock period: 9.680ns (frequency: 103.303MHz) - Total number of paths / destination ports: 273761 / 786 + Clock period: 9.935ns (frequency: 100.654MHz) + Total number of paths / destination ports: 196171 / 732 ------------------------------------------------------------------------- -Delay: 9.680ns (Levels of Logic = 12) - Source: PROBABILITY_REFRESH_SHIFTS_0_1 (FF) - Destination: PROBABILITY_Mram_PROBABILITY_inst_ramb_0 (RAM) +Delay: 9.935ns (Levels of Logic = 17) + Source: PROBABILITY_REFRESH_SHIFTS_32_2 (FF) + Destination: PROBABILITY_PROBUPDATE_NUMERATOR4_7 (FF) Source Clock: CLOCK rising Destination Clock: CLOCK rising - Data Path: PROBABILITY_REFRESH_SHIFTS_0_1 to PROBABILITY_Mram_PROBABILITY_inst_ramb_0 + Data Path: PROBABILITY_REFRESH_SHIFTS_32_2 to PROBABILITY_PROBUPDATE_NUMERATOR4_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDRE:C->Q 5 0.449 0.734 PROBABILITY_REFRESH_SHIFTS_0_1 (PROBABILITY_REFRESH_SHIFTS_0_1) - LUT3_L:I1->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>31 (PROBABILITY_REFRESH_MUX_BLOCK_N38) - MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_14 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF515) - MUXF6:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_9 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF67) - MUXF7:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2>_rn_3 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF73) - MUXF8:I0->O 1 0.354 0.608 PROBABILITY_REFRESH_CONTEXT<3>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81) - LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH__n0241109_F (N961) - MUXF5:I0->O 15 0.345 0.763 PROBABILITY_REFRESH__n0241109 (PROBABILITY_REFRESH__n0241) - LUT4_D:I3->O 7 0.347 0.630 PROBABILITY_REFRESH__n0145_1 (PROBABILITY_REFRESH__n01451) - LUT3:I2->O 1 0.347 0.548 PROBABILITY_REFRESH_DENOMINATOR_OUT<3>1 (PROBABILITY_FRACTION2<3>) - LUT4:I1->O 1 0.347 0.409 PROBABILITY_PROBUPDATE__n00144 (CHOICE132) - LUT4:I2->O 20 0.347 0.769 PROBABILITY_PROBUPDATE__n001417 (PROBABILITY_PROBUPDATE_HALVE_VALUES) - MUXF5:S->O 1 0.553 0.382 PROBABILITY_PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_4111 (PROBABILITY_NEWPROB<15>) - RAMB16_S36_S36:DIA15 0.000 PROBABILITY_Mram_PROBABILITY_inst_ramb_0 + FDRE:C->Q 4 0.449 0.717 PROBABILITY_REFRESH_SHIFTS_32_2 (PROBABILITY_REFRESH_SHIFTS_32_2) + LUT3_L:I1->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<1>16 (PROBABILITY_REFRESH_MUX_BLOCK_N64) + MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_18 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF57) + MUXF6:I0->O 1 0.354 0.548 PROBABILITY_REFRESH_CONTEXT<2>_rn_7 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF62) + LUT4:I1->O 2 0.347 0.545 PROBABILITY_REFRESH__n024172 (CHOICE371) + LUT4_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH__n0241109_SW11_F (N988) + MUXF5:I0->O 3 0.345 0.563 PROBABILITY_REFRESH__n0241109_SW11 (N826) + LUT4_D:I2->O 9 0.347 0.665 PROBABILITY_REFRESH__n0145_1 (PROBABILITY_REFRESH__n01451) + LUT4_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH_NUMERATOR_OUT<2>12 (N650) + MUXCY:S->O 1 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<1>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<1>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<2>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<2>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<3>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<4>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<5>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<5>_cyo) + XORCY:CI->O 2 0.824 0.744 PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_xor (PROBABILITY_PROBUPDATE__n0013<6>) + LUT1_L:I0->LO 1 0.347 0.000 PROBABILITY_PROBUPDATE__n0013<6>_rt (PROBABILITY_PROBUPDATE__n0013<6>_rt) + MUXCY:S->O 0 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<6>_cyo) + XORCY:CI->O 1 0.824 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<7>_xor (PROBABILITY_PROBUPDATE__n0011<7>) + FDR:D 0.293 PROBABILITY_PROBUPDATE_NUMERATOR4_7 ---------------------------------------- - Total 9.680ns (4.836ns logic, 4.844ns route) - (50.0% logic, 50.0% route) + Total 9.935ns (6.154ns logic, 3.781ns route) + (61.9% logic, 38.1% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' - Total number of paths / destination ports: 124379 / 894 + Total number of paths / destination ports: 94958 / 834 ------------------------------------------------------------------------- -Offset: 10.225ns (Levels of Logic = 13) - Source: CONTEXT_SELECT<4> (PAD) - Destination: PROBABILITY_Mram_PROBABILITY_inst_ramb_0 (RAM) +Offset: 10.481ns (Levels of Logic = 18) + Source: CONTEXT_SELECT<1> (PAD) + Destination: PROBABILITY_PROBUPDATE_NUMERATOR4_7 (FF) Destination Clock: CLOCK rising - Data Path: CONTEXT_SELECT<4> to PROBABILITY_Mram_PROBABILITY_inst_ramb_0 + Data Path: CONTEXT_SELECT<1> to PROBABILITY_PROBUPDATE_NUMERATOR4_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUF:I->O 56 0.653 1.075 CONTEXT_SELECT_4_IBUF (CONTEXT_SELECT_4_IBUF) - LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>19 (PROBABILITY_REFRESH_MUX_BLOCK_N26) - MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_8 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF59) - MUXF6:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_6 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF64) - MUXF7:I1->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2>_rn_2 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF72) - MUXF8:I1->O 1 0.354 0.608 PROBABILITY_REFRESH_CONTEXT<3>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81) - LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH__n0241109_F (N961) - MUXF5:I0->O 15 0.345 0.763 PROBABILITY_REFRESH__n0241109 (PROBABILITY_REFRESH__n0241) - LUT4_D:I3->O 7 0.347 0.630 PROBABILITY_REFRESH__n0145_1 (PROBABILITY_REFRESH__n01451) - LUT3:I2->O 1 0.347 0.548 PROBABILITY_REFRESH_DENOMINATOR_OUT<3>1 (PROBABILITY_FRACTION2<3>) - LUT4:I1->O 1 0.347 0.409 PROBABILITY_PROBUPDATE__n00144 (CHOICE132) - LUT4:I2->O 20 0.347 0.769 PROBABILITY_PROBUPDATE__n001417 (PROBABILITY_PROBUPDATE_HALVE_VALUES) - MUXF5:S->O 1 0.553 0.382 PROBABILITY_PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_4111 (PROBABILITY_NEWPROB<15>) - RAMB16_S36_S36:DIA15 0.000 PROBABILITY_Mram_PROBABILITY_inst_ramb_0 + IBUF:I->O 48 0.653 1.060 CONTEXT_SELECT_1_IBUF (CONTEXT_SELECT_1_IBUF) + LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<1>15 (PROBABILITY_REFRESH_MUX_BLOCK_N63) + MUXF5:I1->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_18 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF57) + MUXF6:I0->O 1 0.354 0.548 PROBABILITY_REFRESH_CONTEXT<2>_rn_7 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF62) + LUT4:I1->O 2 0.347 0.545 PROBABILITY_REFRESH__n024172 (CHOICE371) + LUT4_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH__n0241109_SW11_F (N988) + MUXF5:I0->O 3 0.345 0.563 PROBABILITY_REFRESH__n0241109_SW11 (N826) + LUT4_D:I2->O 9 0.347 0.665 PROBABILITY_REFRESH__n0145_1 (PROBABILITY_REFRESH__n01451) + LUT4_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH_NUMERATOR_OUT<2>12 (N650) + MUXCY:S->O 1 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<1>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<1>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<2>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<2>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<3>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<4>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<5>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<5>_cyo) + XORCY:CI->O 2 0.824 0.744 PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_xor (PROBABILITY_PROBUPDATE__n0013<6>) + LUT1_L:I0->LO 1 0.347 0.000 PROBABILITY_PROBUPDATE__n0013<6>_rt (PROBABILITY_PROBUPDATE__n0013<6>_rt) + MUXCY:S->O 0 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<6>_cyo) + XORCY:CI->O 1 0.824 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<7>_xor (PROBABILITY_PROBUPDATE__n0011<7>) + FDR:D 0.293 PROBABILITY_PROBUPDATE_NUMERATOR4_7 ---------------------------------------- - Total 10.225ns (5.040ns logic, 5.185ns route) - (49.3% logic, 50.7% route) + Total 10.481ns (6.358ns logic, 4.123ns route) + (60.7% logic, 39.3% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' Total number of paths / destination ports: 426 / 2 ------------------------------------------------------------------------- -Offset: 11.576ns (Levels of Logic = 7) - Source: ARITH_Mmult__n00001_inst_mult_2 (MULT) +Offset: 11.374ns (Levels of Logic = 7) + Source: ARITH_Mmult__n00001_inst_mult_1 (MULT) Destination: DATA_OUT (PAD) Source Clock: CLOCK rising - Data Path: ARITH_Mmult__n00001_inst_mult_2 to DATA_OUT + Data Path: ARITH_Mmult__n00001_inst_mult_1 to DATA_OUT Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - MULT18X18S:C->P24 3 1.976 0.701 ARITH_Mmult__n00001_inst_mult_2 (ARITH_PRODUCT<24>) + MULT18X18S:C->P22 3 1.782 0.700 ARITH_Mmult__n00001_inst_mult_1 (ARITH_PRODUCT<22>) LUT2_L:I1->LO 1 0.347 0.000 ARITH_ARITHMETIC_UNIT_RESULT_OUT1<14>lut (ARITH_N55) MUXCY:S->O 0 0.235 0.000 ARITH_ARITHMETIC_UNIT_RESULT_OUT1<14>cy (ARITH_ARITHMETIC_UNIT_RESULT_OUT1<14>_cyo) XORCY:CI->O 3 0.824 0.701 ARITH_ARITHMETIC_UNIT_RESULT_OUT1<15>_xor (ARITHMETIC_UNIT_RESULT_OUT1<15>) LUT2_L:I1->LO 1 0.347 0.000 XNor_stagelut15 (N17) - MUXCY:S->O 71 0.794 1.044 XNor_stagecy_rn_14 (OUTPUT__n0001) + MUXCY:S->O 67 0.794 1.036 XNor_stagecy_rn_14 (OUTPUT__n0001) LUT2_D:I1->O 2 0.347 0.518 DATA_OUT1 (DATA_OUT_OBUF) OBUF:I->O 3.743 DATA_OUT_OBUF (DATA_OUT) ---------------------------------------- - Total 11.576ns (8.613ns logic, 2.963ns route) - (74.4% logic, 25.6% route) + Total 11.374ns (8.419ns logic, 2.955ns route) + (74.0% logic, 26.0% route) ========================================================================= -CPU : 27.55 / 29.98 s | Elapsed : 28.00 / 30.00 s +CPU : 25.86 / 26.25 s | Elapsed : 26.00 / 27.00 s --> -Total memory usage is 109820 kilobytes +Total memory usage is 128316 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 18 ( 0 filtered) +Number of warnings : 21 ( 0 filtered) Number of infos : 4 ( 0 filtered) 1.2 dirac/docs/synthesis_reports/decoder/storage_register.syr http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/decoder/storage_register.syr.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: storage_register.syr =================================================================== RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/decoder/storage_register.syr,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- storage_register.syr 6 Sep 2006 18:41:02 -0000 1.1 +++ storage_register.syr 19 Sep 2006 12:12:07 -0000 1.2 @@ -1,10 +1,10 @@ Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav -CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst -CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s --> Reading design: storage_register.prj @@ -32,7 +32,7 @@ ---- Target Parameters Output File Name : "storage_register" Output Format : NGC -Target Device : xc2v250-6-cs144 +Target Device : xc2v2000-6-bf957 ---- Source Options Top Module Name : storage_register @@ -95,7 +95,7 @@ ========================================================================= * HDL Compilation * ========================================================================= -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/STORAGE_REGISTER.vhd" in Library work. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/STORAGE_REGISTER.vhd" in Library work. Architecture rtl of Entity storage_register is up to date. ========================================================================= @@ -110,7 +110,7 @@ ========================================================================= Synthesizing Unit <storage_register>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/STORAGE_REGISTER.vhd". + Related source file is "c:/xilinx/bin/arithmeticdecoder/STORAGE_REGISTER.vhd". Found 16-bit 4-to-1 multiplexer for signal <$n0001>. Found 16-bit register for signal <Q>. Summary: @@ -144,7 +144,7 @@ ========================================================================= Optimizing unit <storage_register> ... -Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... @@ -186,12 +186,12 @@ Device utilization summary: --------------------------- -Selected Device : 2v250cs144-6 +Selected Device : 2v2000bf957-6 - Number of Slices: 10 out of 1536 0% - Number of Slice Flip Flops: 17 out of 3072 0% - Number of 4 input LUTs: 18 out of 3072 0% - Number of bonded IOBs: 38 out of 92 41% + Number of Slices: 10 out of 10752 0% + Number of Slice Flip Flops: 17 out of 21504 0% + Number of 4 input LUTs: 18 out of 21504 0% + Number of bonded IOBs: 38 out of 624 6% Number of GCLKs: 1 out of 16 6% @@ -286,11 +286,11 @@ (89.0% logic, 11.0% route) ========================================================================= -CPU : 4.30 / 4.66 s | Elapsed : 4.00 / 4.00 s +CPU : 4.76 / 5.14 s | Elapsed : 5.00 / 5.00 s --> -Total memory usage is 100604 kilobytes +Total memory usage is 121148 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) 1.2 dirac/docs/synthesis_reports/decoder/symbol_detector.syr http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/decoder/symbol_detector.syr.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: symbol_detector.syr =================================================================== RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/decoder/symbol_detector.syr,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- symbol_detector.syr 6 Sep 2006 18:41:02 -0000 1.1 +++ symbol_detector.syr 19 Sep 2006 12:12:07 -0000 1.2 @@ -1,10 +1,10 @@ Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav -CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst -CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 1.00 s --> Reading design: symbol_detector.prj @@ -32,7 +32,7 @@ ---- Target Parameters Output File Name : "symbol_detector" Output Format : NGC -Target Device : xc2v250-6-cs144 +Target Device : xc2v2000-6-bf957 ---- Source Options Top Module Name : symbol_detector @@ -95,7 +95,7 @@ ========================================================================= * HDL Compilation * ========================================================================= -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/SYMBOL_DETECTOR.vhd" in Library work. +Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/SYMBOL_DETECTOR.vhd" in Library work. Architecture rtl of Entity symbol_detector is up to date. ========================================================================= @@ -110,7 +110,7 @@ ========================================================================= Synthesizing Unit <symbol_detector>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/SYMBOL_DETECTOR.vhd". + Related source file is "c:/xilinx/bin/arithmeticdecoder/SYMBOL_DETECTOR.vhd". Found 16-bit comparator greatequal for signal <$n0001> created at line 23. Summary: inferred 1 Comparator(s). @@ -140,7 +140,7 @@ ========================================================================= Optimizing unit <symbol_detector> ... -Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... @@ -176,11 +176,11 @@ Device utilization summary: --------------------------- -Selected Device : 2v250cs144-6 +Selected Device : 2v2000bf957-6 - Number of Slices: 9 out of 1536 0% - Number of 4 input LUTs: 17 out of 3072 0% - Number of bonded IOBs: 34 out of 92 36% + Number of Slices: 9 out of 10752 0% + Number of 4 input LUTs: 17 out of 21504 0% + Number of bonded IOBs: 34 out of 624 5% ========================================================================= @@ -244,11 +244,11 @@ (80.9% logic, 19.1% route) ========================================================================= -CPU : 4.19 / 4.56 s | Elapsed : 4.00 / 4.00 s +CPU : 4.61 / 5.00 s | Elapsed : 4.00 / 5.00 s --> -Total memory usage is 100604 kilobytes +Total memory usage is 121148 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered)