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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Tue Sep 19 14:12:05 CEST 2006
    Subject: [cvs-checkins] MODIFIED: dirac ...
    Top
    Date: 00/06/09 19:14:12

    Modified: dirac/docs/synthesis_reports/common arithmetic_unit.syr
    context_manager.syr convergence_check.syr
    divider.syr fifo.syr halving_manager.syr
    input_control.syr updater.syr
    Log:
    Adjusted bitwidths and exp-golomb data format to be compatible with the Dirac Specification and software version 0.6.0. Updated test datasets and synthesis reports accordingly. Arithmetic coding and decoding are now COMPLETE.


    Revision Changes Path
    1.2 dirac/docs/synthesis_reports/common/arithmetic_unit.syr

    http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/common/arithmetic_unit.syr.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: arithmetic_unit.syr
    ===================================================================
    RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/common/arithmetic_unit.syr,v
    retrieving revision 1.1
    retrieving revision 1.2
    diff -u -b -r1.1 -r1.2
    --- arithmetic_unit.syr 6 Sep 2006 18:41:01 -0000 1.1
    +++ arithmetic_unit.syr 19 Sep 2006 12:12:04 -0000 1.2
    @@ -1,10 +1,10 @@
    Release 7.1.04i - xst H.42
    Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
    --> Parameter TMPDIR set to __projnav
    -CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 1.00 s
    +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s

    --> Parameter xsthdpdir set to ./xst
    -CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 1.00 s
    +CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s

    --> Reading design: arithmetic_unit.prj

    @@ -32,7 +32,7 @@
    ---- Target Parameters
    Output File Name : "arithmetic_unit"
    Output Format : NGC
    -Target Device : xc2v250-6-cs144
    +Target Device : xc2v2000-6-bg575

    ---- Source Options
    Top Module Name : arithmetic_unit
    @@ -65,7 +65,7 @@

    ---- General Options
    Optimization Goal : Speed
    -Optimization Effort : 1
    +Optimization Effort : 2
    Keep Hierarchy : NO
    Global Optimization : AllClockNets
    RTL Output : Yes
    @@ -95,7 +95,7 @@
    =========================================================================
    * HDL Compilation *
    =========================================================================
    -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd" in Library work.
    +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/ARITHMETIC_UNIT.vhd" in Library work.
    Architecture rtl of Entity arithmetic_unit is up to date.

    =========================================================================
    @@ -110,23 +110,23 @@
    =========================================================================

    Synthesizing Unit <arithmetic_unit>.
    - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd".
    -WARNING:Xst:646 - Signal <PRODUCT<9:0>> is assigned but never used.
    + Related source file is "C:/Xilinx/bin/ArithmeticCoder/ARITHMETIC_UNIT.vhd".
    +WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used.
    WARNING:Xst:646 - Signal <DIFFERENCE3<16>> is assigned but never used.
    WARNING:Xst:646 - Signal <DIFFERENCE4<16>> is assigned but never used.
    WARNING:Xst:646 - Signal <RESULT0<16>> is assigned but never used.
    - Found 17x10-bit multiplier for signal <$n0000> created at line 48.
    + Found 17x8-bit multiplier for signal <$n0000> created at line 48.
    Found 1-bit register for signal <DELAY1>.
    Found 17-bit register for signal <DIFFERENCE1>.
    Found 17-bit adder for signal <DIFFERENCE2>.
    Found 17-bit subtractor for signal <DIFFERENCE3>.
    Found 17-bit subtractor for signal <DIFFERENCE4>.
    Found 17-bit register for signal <LOW2>.
    - Found 27-bit register for signal <PRODUCT>.
    + Found 25-bit register for signal <PRODUCT>.
    Found 17-bit adder for signal <RESULT>.
    Found 17-bit subtractor for signal <RESULT0>.
    Summary:
    - inferred 62 D-type flip-flop(s).
    + inferred 60 D-type flip-flop(s).
    inferred 5 Adder/Subtractor(s).
    inferred 1 Multiplier(s).
    Unit <arithmetic_unit> synthesized.
    @@ -149,7 +149,7 @@

    Macro Statistics
    # Multipliers : 1
    - 17x10-bit registered multiplier : 1
    + 17x8-bit registered multiplier : 1
    # Adders/Subtractors : 5
    17-bit adder : 2
    17-bit subtractor : 3 @@ -166,11 +166,11 @@ WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DIFFERENCE1_16> (without init value) has a constant value of 0 in block <arithmetic_unit>. Optimizing unit <arithmetic_unit> ... -Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block arithmetic_unit, actual ratio is 3. +Found area constraint ratio of 100 (+ 5) on block arithmetic_unit, actual ratio is 0. ========================================================================= * Final Report * @@ -183,7 +183,7 @@ Keep Hierarchy : NO Design Statistics -# IOs : 110 +# IOs : 108 Macro Statistics : # Registers : 3 @@ -193,7 +193,7 @@ # 17-bit adder : 2 # 17-bit subtractor : 3 # Multipliers : 1 -# 17x10-bit registered multiplier: 1 +# 17x8-bit registered multiplier: 1 Cell Usage : # BELS : 236 @@ -209,8 +209,8 @@ # FDR : 1 # Clock Buffers : 1 # BUFGP : 1 -# IO Buffers : 109 -# IBUF : 44 +# IO Buffers : 107 +# IBUF : 42 # OBUF : 65 # MULTs : 1 # MULT18X18S : 1 @@ -219,17 +219,15 @@ Device utilization summary: --------------------------- -Selected Device : 2v250cs144-6 +Selected Device : 2v2000bg575-6 - Number of Slices: 59 out of 1536 3% - Number of Slice Flip Flops: 33 out of 3072 1% - Number of 4 input LUTs: 49 out of 3072 1% - Number of bonded IOBs: 110 out of 92 119% (*) - Number of MULT18X18s: 1 out of 24 4% + Number of Slices: 59 out of 10752 0% + Number of Slice Flip Flops: 33 out of 21504 0% + Number of 4 input LUTs: 49 out of 21504 0% + Number of bonded IOBs: 108 out of 408 26% + Number of MULT18X18s: 1 out of 56 1% Number of GCLKs: 1 out of 16 6% -WARNING:Xst:1336 - (*) More than 100% of Device resources are used - ========================================================================= TIMING REPORT @@ -252,7 +250,7 @@ Minimum period: No path found Minimum input arrival time before clock: 6.731ns - Maximum output required time after clock: 10.035ns + Maximum output required time after clock: 9.842ns Maximum combinational path delay: No path found Timing Detail: @@ -261,7 +259,7 @@ ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' - Total number of paths / destination ports: 228 / 93 + Total number of paths / destination ports: 226 / 91 ------------------------------------------------------------------------- Offset: 6.731ns (Levels of Logic = 17) Source: DIFFERENCE<1> (PAD) @@ -298,7 +296,7 @@ Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' Total number of paths / destination ports: 3233 / 65 ------------------------------------------------------------------------- -Offset: 10.035ns (Levels of Logic = 7) +Offset: 9.842ns (Levels of Logic = 7) Source: Mmult__n00001_inst_mult_0 (MULT) Destination: RESULT_OUT0<15> (PAD) Source Clock: CLOCK rising @@ -307,7 +305,7 @@ Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - MULT18X18S:C->P23 3 1.879 0.700 Mmult__n00001_inst_mult_0 (PRODUCT<23>) + MULT18X18S:C->P21 3 1.685 0.700 Mmult__n00001_inst_mult_0 (PRODUCT<21>) LUT2:I1->O 1 0.347 0.000 arithmetic_unit_RESULT_OUT1<13>lut (N54) MUXCY:S->O 1 0.235 0.000 arithmetic_unit_RESULT_OUT1<13>cy (arithmetic_unit_RESULT_OUT1<13>_cyo) XORCY:CI->O 2 0.824 0.518 arithmetic_unit_RESULT_OUT1<14>_xor (RESULT_OUT1_14_OBUF) @@ -316,17 +314,17 @@ XORCY:CI->O 1 0.824 0.383 arithmetic_unit_RESULT_OUT0<15>_xor (RESULT_OUT0_15_OBUF) OBUF:I->O 3.743 RESULT_OUT0_15_OBUF (RESULT_OUT0<15>) ---------------------------------------- - Total 10.035ns (8.434ns logic, 1.601ns route) - (84.0% logic, 16.0% route) + Total 9.842ns (8.240ns logic, 1.601ns route) + (83.7% logic, 16.3% route) ========================================================================= -CPU : 4.94 / 5.31 s | Elapsed : 5.00 / 6.00 s +CPU : 5.33 / 5.69 s | Elapsed : 5.00 / 6.00 s --> -Total memory usage is 100604 kilobytes +Total memory usage is 121148 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 7 ( 0 filtered) +Number of warnings : 6 ( 0 filtered) Number of infos : 0 ( 0 filtered) 1.2 dirac/docs/synthesis_reports/common/context_manager.syr http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/common/context_manager.syr.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: context_manager.syr =================================================================== RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/common/context_manager.syr,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- context_manager.syr 6 Sep 2006 18:41:01 -0000 1.1 +++ context_manager.syr 19 Sep 2006 12:12:04 -0000 1.2 @@ -1,10 +1,10 @@ Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav -CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst -CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s --> Reading design: context_manager.prj @@ -32,7 +32,7 @@ ---- Target Parameters Output File Name : "context_manager" Output Format : NGC -Target Device : xc2v250-6-cs144 +Target Device : xc2v2000-6-bg575 ---- Source Options Top Module Name : context_manager @@ -65,7 +65,7 @@ ---- General Options Optimization Goal : Speed -Optimization Effort : 1 +Optimization Effort : 2 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes @@ -95,35 +95,38 @@ ========================================================================= * HDL Compilation * ========================================================================= -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" in Library work. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" in Library work. Architecture rtl of Entity divider is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd" in Library work. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd" in Library work. Architecture rtl of Entity updater is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" in Library work. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" in Library work. Architecture rtl of Entity halving_manager is up to date. -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work. Architecture rtl of Entity context_manager is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity <context_manager> (Architecture <rtl>). -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 118: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 141: Index value(s) does not match array range, simulation mismatch. Entity <context_manager> analyzed. Unit <context_manager> generated. Analyzing Entity <DIVIDER> (Architecture <rtl>). -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 308: Index value(s) does not match array range, simulation mismatch. Entity <DIVIDER> analyzed. Unit <DIVIDER> generated. Analyzing Entity <UPDATER> (Architecture <rtl>). Entity <UPDATER> analyzed. Unit <UPDATER> generated. Analyzing Entity <HALVING_MANAGER> (Architecture <rtl>). -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:1610 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 78: Width mismatch. <NUMERATOR2> has a width of 8 bits but assigned expression is 10-bit wide. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch. Entity <HALVING_MANAGER> analyzed. Unit <HALVING_MANAGER> generated. @@ -132,7 +135,7 @@ ========================================================================= Synthesizing Unit <HALVING_MANAGER>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd". + Related source file is "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd". Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108. Found 3-bit 4-to-1 multiplexer for signal <$n0050>. Found 3-bit 4-to-1 multiplexer for signal <$n0051>. @@ -226,13 +229,13 @@ Found 3-bit addsub for signal <$n0142>. Found 3-bit addsub for signal <$n0143>. Found 3-bit addsub for signal <$n0144>. - Found 10-bit comparator greater for signal <$n0147> created at line 99. + Found 8-bit comparator greater for signal <$n0147> created at line 99. Found 3-bit comparator greater for signal <$n0241> created at line 108. Found 1-bit register for signal <AFTER_TRIGGER>. - Found 10-bit register for signal <DENOMINATOR>. - Found 10-bit adder for signal <DENOMINATOR2>. - Found 10-bit register for signal <NUMERATOR>. - Found 10-bit adder for signal <NUMERATOR2>. + Found 8-bit register for signal <DENOMINATOR>. + Found 8-bit adder for signal <DENOMINATOR2>. + Found 8-bit register for signal <NUMERATOR>. + Found 8-bit adder for signal <NUMERATOR2>. Found 138-bit register for signal <SHIFTS>. Summary: inferred 139 D-type flip-flop(s). @@ -243,55 +246,52 @@ Synthesizing Unit <UPDATER>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd". + Related source file is "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd". WARNING:Xst:1780 - Signal <HALVING_ALLOWED> is never used or assigned. Found 1-bit register for signal <UPDATE>. - Found 10-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>. - Found 10-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>. - Found 10-bit adder for signal <$n0009> created at line 51. - Found 10-bit adder for signal <$n0011> created at line 73. - Found 10-bit adder for signal <$n0012> created at line 84. - Found 10-bit adder for signal <$n0013> created at line 62. - Found 10-bit register for signal <DENOMINATOR2>. - Found 10-bit register for signal <NUMERATOR1>. - Found 10-bit register for signal <NUMERATOR2>. - Found 10-bit register for signal <NUMERATOR3>. - Found 10-bit register for signal <NUMERATOR4>. + Found 8-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>. + Found 8-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>. + Found 8-bit adder for signal <$n0009> created at line 51. + Found 8-bit adder for signal <$n0011> created at line 73. + Found 8-bit adder for signal <$n0012> created at line 84. + Found 8-bit adder for signal <$n0013> created at line 62. + Found 8-bit register for signal <DENOMINATOR2>. + Found 8-bit register for signal <NUMERATOR1>. + Found 8-bit register for signal <NUMERATOR2>. + Found 8-bit register for signal <NUMERATOR3>. + Found 8-bit register for signal <NUMERATOR4>. Found 1-bit xor2 for signal <UPDATE_SWITCH>. Summary: inferred 1 D-type flip-flop(s). inferred 4 Adder/Subtractor(s). - inferred 20 Multiplexer(s). + inferred 16 Multiplexer(s). Unit <UPDATER> synthesized. Synthesizing Unit <DIVIDER>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd". -WARNING:Xst:646 - Signal <TOTAL<41:32>> is assigned but never used. -WARNING:Xst:646 - Signal <TOTAL<21:0>> is assigned but never used. - Found 1022x32-bit ROM for signal <$n0002> created at line 1079. - Found 16x10-bit multiplier for signal <$n0003> created at line 1086. - Found 16x10-bit multiplier for signal <$n0004> created at line 1093. - Found 10-bit subtractor for signal <INDEX>. - Found 10-bit register for signal <NUMERATOR2>. - Found 26-bit register for signal <PRODUCT1>. - Found 26-bit register for signal <PRODUCT2>. - Found 32-bit register for signal <RECIPROCAL>. - Found 42-bit adder for signal <TOTAL>. + Related source file is "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd". +WARNING:Xst:646 - Signal <PRODUCT<23:16>> is assigned but never used. +WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used. + Found 254x16-bit ROM for signal <$n0002> created at line 308. + Found 16x8-bit multiplier for signal <$n0003> created at line 315. + Found 8-bit subtractor for signal <INDEX>. + Found 8-bit register for signal <NUMERATOR2>. + Found 24-bit register for signal <PRODUCT>. + Found 16-bit register for signal <RECIPROCAL>. Summary: inferred 1 ROM(s). - inferred 84 D-type flip-flop(s). - inferred 2 Adder/Subtractor(s). - inferred 2 Multiplier(s). + inferred 40 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 1 Multiplier(s). Unit <DIVIDER> synthesized. Synthesizing Unit <context_manager>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd". - Found 46x20-bit dual-port block RAM for signal <PROBABILITY>. + Related source file is "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd". + Found 46x16-bit dual-port block RAM for signal <PROBABILITY>. ----------------------------------------------------------------------- | mode | write-first | | - | aspect ratio | 46-word x 20-bit | | + | aspect ratio | 46-word x 16-bit | | | clock | connected to signal <CLOCK> | rise | | dual clock | connected to signal <CLOCK> | rise | | dual enable | connected to signal <SET> | high | @@ -303,15 +303,15 @@ | dual data out | connected to signal <RATIO> | | | ram_style | Auto | | ----------------------------------------------------------------------- - Found 1-bit 64-to-1 multiplexer for signal <$n0003> created at line 141. + Found 1-bit 46-to-1 multiplexer for signal <$n0003> created at line 141. Found 1-bit register for signal <CONTEXT_VALID>. Found 2-bit register for signal <DATA_READY>. Found 6-bit register for signal <OLD_CONTEXT>. Found 6-bit register for signal <READ_ADDRESS>. - Found 64-bit register for signal <RESET_FLAGS>. + Found 46-bit register for signal <RESET_FLAGS>. Summary: inferred 1 RAM(s). - inferred 79 D-type flip-flop(s). + inferred 61 D-type flip-flop(s). inferred 1 Multiplexer(s). Unit <context_manager> synthesized. @@ -328,9 +328,6 @@ Found registered multiplier on signal <_n0003>: - 1 register level(s) found in a register connected to the multiplier macro ouput. Pushing register(s) into the multiplier macro. - Found registered multiplier on signal <_n0004>: - - 1 register level(s) found in a register connected to the multiplier macro ouput. - Pushing register(s) into the multiplier macro. Advanced Registered AddSub inference ... Dynamic shift register inference ... @@ -339,28 +336,27 @@ Macro Statistics # Block RAMs : 2 - 1022x32-bit single-port block RAM : 1 - 46x20-bit dual-port block RAM : 1 -# Multipliers : 2 - 16x10-bit registered multiplier : 2 -# Adders/Subtractors : 54 - 10-bit adder : 6 - 10-bit subtractor : 1 + 254x16-bit single-port block RAM : 1 + 46x16-bit dual-port block RAM : 1 +# Multipliers : 1 + 16x8-bit registered multiplier : 1 +# Adders/Subtractors : 53 3-bit addsub : 46 - 42-bit adder : 1 -# Registers : 125 - 1-bit register : 69 - 10-bit register : 8 + 8-bit adder : 6 + 8-bit subtractor : 1 +# Registers : 107 + 1-bit register : 51 3-bit register : 46 6-bit register : 2 + 8-bit register : 8 # Comparators : 2 - 10-bit comparator greater : 1 3-bit comparator greater : 1 + 8-bit comparator greater : 1 # Multiplexers : 50 - 1-bit 64-to-1 multiplexer : 1 - 10-bit 4-to-1 multiplexer : 2 + 1-bit 46-to-1 multiplexer : 1 3-bit 4-to-1 multiplexer : 46 3-bit 46-to-1 multiplexer : 1 + 8-bit 4-to-1 multiplexer : 2 # Xors : 1 1-bit xor2 : 1 @@ -377,23 +373,20 @@ Optimizing unit <UPDATER> ... Optimizing unit <DIVIDER> ... -Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... Register <PROBUPDATE_UPDATE> equivalent to <DATA_READY_0> has been removed +Register <DIVISION_NUMERATOR2_5> equivalent to <PROBUPDATE_NUMERATOR1_5> has been removed Register <DIVISION_NUMERATOR2_7> equivalent to <PROBUPDATE_NUMERATOR1_7> has been removed -Register <DIVISION_NUMERATOR2_9> equivalent to <PROBUPDATE_NUMERATOR1_9> has been removed -Register <DIVISION_NUMERATOR2_8> equivalent to <PROBUPDATE_NUMERATOR1_8> has been removed +Register <DIVISION_NUMERATOR2_6> equivalent to <PROBUPDATE_NUMERATOR1_6> has been removed Register <DIVISION_NUMERATOR2_0> equivalent to <PROBUPDATE_NUMERATOR1_0> has been removed Register <DIVISION_NUMERATOR2_1> equivalent to <PROBUPDATE_NUMERATOR1_1> has been removed Register <DIVISION_NUMERATOR2_2> equivalent to <PROBUPDATE_NUMERATOR1_2> has been removed Register <DIVISION_NUMERATOR2_3> equivalent to <PROBUPDATE_NUMERATOR1_3> has been removed Register <DIVISION_NUMERATOR2_4> equivalent to <PROBUPDATE_NUMERATOR1_4> has been removed -Register <DIVISION_NUMERATOR2_5> equivalent to <PROBUPDATE_NUMERATOR1_5> has been removed -Register <DIVISION_NUMERATOR2_6> equivalent to <PROBUPDATE_NUMERATOR1_6> has been removed -Found area constraint ratio of 100 (+ 5) on block context_manager, actual ratio is 24. -FlipFlop READ_ADDRESS_0 has been replicated 3 time(s) +Found area constraint ratio of 100 (+ 5) on block context_manager, actual ratio is 3. ========================================================================= * Final Report * @@ -406,84 +399,83 @@ Keep Hierarchy : NO Design Statistics -# IOs : 23 +# IOs : 21 Macro Statistics : # RAM : 2 -# 1022x32-bit single-port block RAM: 1 -# 46x20-bit dual-port block RAM: 1 -# Registers : 197 -# 1-bit register : 149 +# 254x16-bit single-port block RAM: 1 +# 46x16-bit dual-port block RAM: 1 +# Registers : 163 +# 1-bit register : 115 # 3-bit register : 46 # 6-bit register : 2 # Multiplexers : 50 -# 1-bit 64-to-1 multiplexer : 1 -# 10-bit 4-to-1 multiplexer : 2 +# 1-bit 46-to-1 multiplexer : 1 # 3-bit 4-to-1 multiplexer : 46 # 3-bit 46-to-1 multiplexer : 1 -# Adders/Subtractors : 8 -# 10-bit adder : 6 -# 10-bit subtractor : 1 -# 42-bit adder : 1 -# Multipliers : 2 -# 16x10-bit registered multiplier: 2 +# 8-bit 4-to-1 multiplexer : 2 +# Adders/Subtractors : 7 +# 8-bit adder : 6 +# 8-bit subtractor : 1 +# Multipliers : 1 +# 16x8-bit registered multiplier: 1 # Comparators : 2 -# 10-bit comparator greater : 1 # 3-bit comparator greater : 1 +# 8-bit comparator greater : 1 # Xors : 92 # 1-bit xor3 : 92 Cell Usage : -# BELS : 960 +# BELS : 799 # GND : 1 # INV : 1 -# LUT1 : 20 -# LUT1_L : 9 -# LUT2 : 33 -# LUT3 : 89 +# LUT1 : 11 +# LUT1_L : 7 +# LUT2 : 23 +# LUT3 : 87 # LUT3_D : 4 -# LUT3_L : 151 -# LUT4 : 319 -# LUT4_D : 24 -# LUT4_L : 16 -# MUXCY : 77 -# MUXF5 : 107 -# MUXF6 : 23 -# MUXF7 : 10 -# MUXF8 : 5 +# LUT3_L : 89 +# LUT4 : 293 +# LUT4_D : 12 +# LUT4_L : 56 +# MUXCY : 42 +# MUXF5 : 102 +# MUXF6 : 19 +# MUXF7 : 8 +# MUXF8 : 4 # VCC : 1 -# XORCY : 70 -# FlipFlops/Latches : 291 +# XORCY : 39 +# FlipFlops/Latches : 256 # FD : 6 -# FDE : 9 -# FDR : 48 -# FDRE : 156 +# FDE : 6 +# FDR : 38 +# FDRE : 152 # FDRSE : 1 # FDS : 5 -# FDSE : 66 -# RAMS : 3 -# RAMB16_S18 : 2 +# FDSE : 48 +# RAMS : 2 +# RAMB16_S36 : 1 # RAMB16_S36_S36 : 1 # Clock Buffers : 1 # BUFGP : 1 -# IO Buffers : 22 +# IO Buffers : 20 # IBUF : 11 -# OBUF : 11 -# MULTs : 2 -# MULT18X18S : 2 +# OBUF : 9 +# MULTs : 1 +# MULT18X18S : 1 ========================================================================= Device utilization summary: --------------------------- -Selected Device : 2v250cs144-6 +Selected Device : 2v2000bg575-6 - Number of Slices: 359 out of 1536 23% - Number of Slice Flip Flops: 291 out of 3072 9% - Number of 4 input LUTs: 665 out of 3072 21% - Number of bonded IOBs: 23 out of 92 25% - Number of BRAMs: 3 out of 24 12% - Number of MULT18X18s: 2 out of 24 8% + Number of Slices: 316 out of 10752 2% + Number of Slice Flip Flops: 256 out of 21504 1% + Number of 4 input LUTs: 582 out of 21504 2% + Number of bonded IOBs: 21 out of 408 5% + Number of BRAMs: 2 out of 56 3% + Number of MULT18X18s: 1 out of 56 1% Number of GCLKs: 1 out of 16 6% @@ -499,16 +491,16 @@ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ -CLOCK | BUFGP | 294 | +CLOCK | BUFGP | 258 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -6 - Minimum period: 9.680ns (Maximum Frequency: 103.303MHz) - Minimum input arrival time before clock: 10.225ns - Maximum output required time after clock: 8.362ns + Minimum period: 10.073ns (Maximum Frequency: 99.275MHz) + Minimum input arrival time before clock: 10.619ns + Maximum output required time after clock: 5.682ns Maximum combinational path delay: No path found Timing Detail: @@ -517,103 +509,106 @@ ========================================================================= Timing constraint: Default period analysis for Clock 'CLOCK' - Clock period: 9.680ns (frequency: 103.303MHz) - Total number of paths / destination ports: 223210 / 475 + Clock period: 10.073ns (frequency: 99.275MHz) + Total number of paths / destination ports: 147629 / 423 ------------------------------------------------------------------------- -Delay: 9.680ns (Levels of Logic = 12) - Source: REFRESH_SHIFTS_0_1 (FF) - Destination: Mram_PROBABILITY_inst_ramb_0 (RAM) +Delay: 10.073ns (Levels of Logic = 17) + Source: REFRESH_SHIFTS_32_2 (FF) + Destination: PROBUPDATE_NUMERATOR4_7 (FF) Source Clock: CLOCK rising Destination Clock: CLOCK rising - Data Path: REFRESH_SHIFTS_0_1 to Mram_PROBABILITY_inst_ramb_0 + Data Path: REFRESH_SHIFTS_32_2 to PROBUPDATE_NUMERATOR4_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDRE:C->Q 5 0.449 0.734 REFRESH_SHIFTS_0_1 (REFRESH_SHIFTS_0_1) - LUT3_L:I1->LO 1 0.347 0.000 REFRESH_CONTEXT<4>31 (REFRESH_MUX_BLOCK_N38) - MUXF5:I0->O 1 0.345 0.000 REFRESH_CONTEXT<1>_rn_14 (REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF515) - MUXF6:I0->O 1 0.354 0.000 REFRESH_CONTEXT<0>_rn_9 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF67) - MUXF7:I0->O 1 0.354 0.000 REFRESH_CONTEXT<2>_rn_3 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF73) - MUXF8:I0->O 1 0.354 0.608 REFRESH_CONTEXT<3>_rn_0 (REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81) - LUT3_L:I0->LO 1 0.347 0.000 REFRESH__n0241109_F (N797) - MUXF5:I0->O 15 0.345 0.763 REFRESH__n0241109 (REFRESH__n0241) - LUT4_D:I3->O 7 0.347 0.630 REFRESH__n0145_1 (REFRESH__n01451) - LUT3:I2->O 1 0.347 0.548 REFRESH_DENOMINATOR_OUT<3>1 (FRACTION2<3>) - LUT4:I1->O 1 0.347 0.409 PROBUPDATE__n00144 (CHOICE11) - LUT4:I2->O 20 0.347 0.769 PROBUPDATE__n001417 (PROBUPDATE_HALVE_VALUES) - MUXF5:S->O 1 0.553 0.382 PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6111 (NEWPROB<17>) - RAMB16_S36_S36:DIA17 0.000 Mram_PROBABILITY_inst_ramb_0 + FDRE:C->Q 4 0.449 0.717 REFRESH_SHIFTS_32_2 (REFRESH_SHIFTS_32_2) + LUT3_L:I1->LO 1 0.347 0.000 REFRESH_CONTEXT<1>16 (REFRESH_MUX_BLOCK_N64) + MUXF5:I0->O 1 0.345 0.000 REFRESH_CONTEXT<0>_rn_18 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF57) + MUXF6:I0->O 1 0.354 0.548 REFRESH_CONTEXT<2>_rn_7 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF62) + LUT4:I1->O 2 0.347 0.684 REFRESH__n024172 (CHOICE250) + LUT4_L:I1->LO 1 0.347 0.000 REFRESH__n0241109_SW11_F (N764) + MUXF5:I0->O 3 0.345 0.563 REFRESH__n0241109_SW11 (N673) + LUT4_D:I2->O 9 0.347 0.665 REFRESH__n0145_1 (REFRESH__n01451) + LUT4_L:I2->LO 1 0.347 0.000 REFRESH_NUMERATOR_OUT<2>12 (N590) + MUXCY:S->O 1 0.235 0.000 PROBUPDATE_UPDATER__n0013<1>cy (PROBUPDATE_UPDATER__n0013<1>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<2>cy (PROBUPDATE_UPDATER__n0013<2>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<3>cy (PROBUPDATE_UPDATER__n0013<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<4>cy (PROBUPDATE_UPDATER__n0013<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<5>cy (PROBUPDATE_UPDATER__n0013<5>_cyo) + XORCY:CI->O 2 0.824 0.744 PROBUPDATE_UPDATER__n0013<6>_xor (PROBUPDATE__n0013<6>) + LUT1_L:I0->LO 1 0.347 0.000 PROBUPDATE__n0013<6>_rt (PROBUPDATE__n0013<6>_rt) + MUXCY:S->O 0 0.235 0.000 PROBUPDATE_UPDATER__n0011<6>cy (PROBUPDATE_UPDATER__n0011<6>_cyo) + XORCY:CI->O 1 0.824 0.000 PROBUPDATE_UPDATER__n0011<7>_xor (PROBUPDATE__n0011<7>) + FDR:D 0.293 PROBUPDATE_NUMERATOR4_7 ---------------------------------------- - Total 9.680ns (4.836ns logic, 4.844ns route) - (50.0% logic, 50.0% route) + Total 10.073ns (6.154ns logic, 3.919ns route) + (61.1% logic, 38.9% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' - Total number of paths / destination ports: 124256 / 757 + Total number of paths / destination ports: 94125 / 679 ------------------------------------------------------------------------- -Offset: 10.225ns (Levels of Logic = 13) - Source: CONTEXT_NUMBER<4> (PAD) - Destination: Mram_PROBABILITY_inst_ramb_0 (RAM) +Offset: 10.619ns (Levels of Logic = 18) + Source: CONTEXT_NUMBER<1> (PAD) + Destination: PROBUPDATE_NUMERATOR4_7 (FF) Destination Clock: CLOCK rising - Data Path: CONTEXT_NUMBER<4> to Mram_PROBABILITY_inst_ramb_0 + Data Path: CONTEXT_NUMBER<1> to PROBUPDATE_NUMERATOR4_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUF:I->O 56 0.653 1.075 CONTEXT_NUMBER_4_IBUF (CONTEXT_NUMBER_4_IBUF) - LUT3_L:I0->LO 1 0.347 0.000 REFRESH_CONTEXT<4>19 (REFRESH_MUX_BLOCK_N26) - MUXF5:I0->O 1 0.345 0.000 REFRESH_CONTEXT<1>_rn_8 (REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF59) - MUXF6:I0->O 1 0.354 0.000 REFRESH_CONTEXT<0>_rn_6 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF64) - MUXF7:I1->O 1 0.354 0.000 REFRESH_CONTEXT<2>_rn_2 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF72) - MUXF8:I1->O 1 0.354 0.608 REFRESH_CONTEXT<3>_rn_0 (REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81) - LUT3_L:I0->LO 1 0.347 0.000 REFRESH__n0241109_F (N797) - MUXF5:I0->O 15 0.345 0.763 REFRESH__n0241109 (REFRESH__n0241) - LUT4_D:I3->O 7 0.347 0.630 REFRESH__n0145_1 (REFRESH__n01451) - LUT3:I2->O 1 0.347 0.548 REFRESH_DENOMINATOR_OUT<3>1 (FRACTION2<3>) - LUT4:I1->O 1 0.347 0.409 PROBUPDATE__n00144 (CHOICE11) - LUT4:I2->O 20 0.347 0.769 PROBUPDATE__n001417 (PROBUPDATE_HALVE_VALUES) - MUXF5:S->O 1 0.553 0.382 PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6111 (NEWPROB<17>) - RAMB16_S36_S36:DIA17 0.000 Mram_PROBABILITY_inst_ramb_0 + IBUF:I->O 48 0.653 1.060 CONTEXT_NUMBER_1_IBUF (CONTEXT_NUMBER_1_IBUF) + LUT3_L:I0->LO 1 0.347 0.000 REFRESH_CONTEXT<1>15 (REFRESH_MUX_BLOCK_N63) + MUXF5:I1->O 1 0.345 0.000 REFRESH_CONTEXT<0>_rn_18 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF57) + MUXF6:I0->O 1 0.354 0.548 REFRESH_CONTEXT<2>_rn_7 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF62) + LUT4:I1->O 2 0.347 0.684 REFRESH__n024172 (CHOICE250) + LUT4_L:I1->LO 1 0.347 0.000 REFRESH__n0241109_SW11_F (N764) + MUXF5:I0->O 3 0.345 0.563 REFRESH__n0241109_SW11 (N673) + LUT4_D:I2->O 9 0.347 0.665 REFRESH__n0145_1 (REFRESH__n01451) + LUT4_L:I2->LO 1 0.347 0.000 REFRESH_NUMERATOR_OUT<2>12 (N590) + MUXCY:S->O 1 0.235 0.000 PROBUPDATE_UPDATER__n0013<1>cy (PROBUPDATE_UPDATER__n0013<1>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<2>cy (PROBUPDATE_UPDATER__n0013<2>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<3>cy (PROBUPDATE_UPDATER__n0013<3>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<4>cy (PROBUPDATE_UPDATER__n0013<4>_cyo) + MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<5>cy (PROBUPDATE_UPDATER__n0013<5>_cyo) + XORCY:CI->O 2 0.824 0.744 PROBUPDATE_UPDATER__n0013<6>_xor (PROBUPDATE__n0013<6>) + LUT1_L:I0->LO 1 0.347 0.000 PROBUPDATE__n0013<6>_rt (PROBUPDATE__n0013<6>_rt) + MUXCY:S->O 0 0.235 0.000 PROBUPDATE_UPDATER__n0011<6>cy (PROBUPDATE_UPDATER__n0011<6>_cyo) + XORCY:CI->O 1 0.824 0.000 PROBUPDATE_UPDATER__n0011<7>_xor (PROBUPDATE__n0011<7>) + FDR:D 0.293 PROBUPDATE_NUMERATOR4_7 ---------------------------------------- - Total 10.225ns (5.040ns logic, 5.185ns route) - (49.3% logic, 50.7% route) + Total 10.619ns (6.358ns logic, 4.261ns route) + (59.9% logic, 40.1% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' - Total number of paths / destination ports: 301 / 11 + Total number of paths / destination ports: 10 / 9 ------------------------------------------------------------------------- -Offset: 8.362ns (Levels of Logic = 9) - Source: DIVISION_Mmult__n00041_inst_mult_0 (MULT) - Destination: PROB<9> (PAD) +Offset: 5.682ns (Levels of Logic = 2) + Source: DATA_READY_0 (FF) + Destination: READY (PAD) Source Clock: CLOCK rising - Data Path: DIVISION_Mmult__n00041_inst_mult_0 to PROB<9> + Data Path: DATA_READY_0 to READY Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - MULT18X18S:C->P25 1 2.073 0.548 DIVISION_Mmult__n00041_inst_mult_0 (DIVISION_PRODUCT2<25>) - LUT2:I1->O 1 0.347 0.000 DIVISION_DIVIDER_QUOTIENT<3>lut (DIVISION_N23) - MUXCY:S->O 1 0.235 0.000 DIVISION_DIVIDER_QUOTIENT<3>cy (DIVISION_DIVIDER_QUOTIENT<3>_cyo) - MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<4>cy (DIVISION_DIVIDER_QUOTIENT<4>_cyo) - MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<5>cy (DIVISION_DIVIDER_QUOTIENT<5>_cyo) - MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<6>cy (DIVISION_DIVIDER_QUOTIENT<6>_cyo) - MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<7>cy (DIVISION_DIVIDER_QUOTIENT<7>_cyo) - MUXCY:CI->O 0 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<8>cy (DIVISION_DIVIDER_QUOTIENT<8>_cyo) - XORCY:CI->O 1 0.824 0.383 DIVISION_DIVIDER_QUOTIENT<9>_xor (PROB_9_OBUF) - OBUF:I->O 3.743 PROB_9_OBUF (PROB<9>) + FDR:C->Q 3 0.449 0.760 DATA_READY_0 (DATA_READY_0) + LUT2:I0->O 1 0.347 0.383 READY1 (READY_OBUF) + OBUF:I->O 3.743 READY_OBUF (READY) ---------------------------------------- - Total 8.362ns (7.432ns logic, 0.930ns route) - (88.9% logic, 11.1% route) + Total 5.682ns (4.539ns logic, 1.143ns route) + (79.9% logic, 20.1% route) ========================================================================= -CPU : 18.47 / 18.83 s | Elapsed : 18.00 / 18.00 s +CPU : 19.75 / 20.13 s | Elapsed : 20.00 / 20.00 s --> -Total memory usage is 106748 kilobytes +Total memory usage is 126268 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 10 ( 0 filtered) +Number of warnings : 13 ( 0 filtered) Number of infos : 3 ( 0 filtered) 1.2 dirac/docs/synthesis_reports/common/convergence_check.syr http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/common/convergence_check.syr.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: convergence_check.syr =================================================================== RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/common/convergence_check.syr,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- convergence_check.syr 6 Sep 2006 18:41:01 -0000 1.1 +++ convergence_check.syr 19 Sep 2006 12:12:04 -0000 1.2 @@ -32,7 +32,7 @@ ---- Target Parameters Output File Name : "convergence_check" Output Format : NGC -Target Device : xc2v250-6-cs144 +Target Device : xc2v2000-6-bg575 ---- Source Options Top Module Name : convergence_check @@ -65,7 +65,7 @@ ---- General Options Optimization Goal : Speed -Optimization Effort : 1 +Optimization Effort : 2 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes @@ -95,7 +95,7 @@ ========================================================================= * HDL Compilation * ========================================================================= -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/CONVERGENCE_CHECK.vhd" in Library work. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/CONVERGENCE_CHECK.vhd" in Library work. Architecture rtl of Entity convergence_check is up to date. ========================================================================= @@ -110,7 +110,7 @@ ========================================================================= Synthesizing Unit <convergence_check>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/CONVERGENCE_CHECK.vhd". + Related source file is "C:/Xilinx/bin/ArithmeticCoder/CONVERGENCE_CHECK.vhd". Unit <convergence_check> synthesized. @@ -134,7 +134,7 @@ ========================================================================= Optimizing unit <convergence_check> ... -Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... @@ -166,11 +166,11 @@ Device utilization summary: --------------------------- -Selected Device : 2v250cs144-6 +Selected Device : 2v2000bg575-6 - Number of Slices: 2 out of 1536 0% - Number of 4 input LUTs: 3 out of 3072 0% - Number of bonded IOBs: 7 out of 92 7% + Number of Slices: 2 out of 10752 0% + Number of 4 input LUTs: 3 out of 21504 0% + Number of bonded IOBs: 7 out of 408 1% ========================================================================= @@ -218,11 +218,11 @@ (75.9% logic, 24.1% route) ========================================================================= -CPU : 4.06 / 4.42 s | Elapsed : 4.00 / 4.00 s +CPU : 4.25 / 4.61 s | Elapsed : 4.00 / 4.00 s --> -Total memory usage is 100604 kilobytes +Total memory usage is 120124 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) 1.2 dirac/docs/synthesis_reports/common/divider.syr http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/common/divider.syr.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: divider.syr =================================================================== RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/common/divider.syr,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- divider.syr 6 Sep 2006 18:41:01 -0000 1.1 +++ divider.syr 19 Sep 2006 12:12:04 -0000 1.2 @@ -1,10 +1,10 @@ Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav -CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst -CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s --> Reading design: divider.prj @@ -32,7 +32,7 @@ ---- Target Parameters Output File Name : "divider" Output Format : NGC -Target Device : xc2v250-6-cs144 +Target Device : xc2v2000-6-bg575 ---- Source Options Top Module Name : divider @@ -65,7 +65,7 @@ ---- General Options Optimization Goal : Speed -Optimization Effort : 1 +Optimization Effort : 2 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes @@ -95,14 +95,14 @@ ========================================================================= * HDL Compilation * ========================================================================= -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" in Library work. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" in Library work. Architecture rtl of Entity divider is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity <divider> (Architecture <rtl>). -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 308: Index value(s) does not match array range, simulation mismatch. Entity <divider> analyzed. Unit <divider> generated. @@ -111,23 +111,20 @@ ========================================================================= Synthesizing Unit <divider>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd". -WARNING:Xst:646 - Signal <TOTAL<41:32>> is assigned but never used. -WARNING:Xst:646 - Signal <TOTAL<21:0>> is assigned but never used. - Found 1022x32-bit ROM for signal <$n0002> created at line 1079. - Found 16x10-bit multiplier for signal <$n0003> created at line 1086. - Found 16x10-bit multiplier for signal <$n0004> created at line 1093. - Found 10-bit subtractor for signal <INDEX>. - Found 10-bit register for signal <NUMERATOR2>. - Found 26-bit register for signal <PRODUCT1>. - Found 26-bit register for signal <PRODUCT2>. - Found 32-bit register for signal <RECIPROCAL>. - Found 42-bit adder for signal <TOTAL>. + Related source file is "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd". +WARNING:Xst:646 - Signal <PRODUCT<23:16>> is assigned but never used. +WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used. + Found 254x16-bit ROM for signal <$n0002> created at line 308. + Found 16x8-bit multiplier for signal <$n0003> created at line 315. + Found 8-bit subtractor for signal <INDEX>. + Found 8-bit register for signal <NUMERATOR2>. + Found 24-bit register for signal <PRODUCT>. + Found 16-bit register for signal <RECIPROCAL>. Summary: inferred 1 ROM(s). - inferred 84 D-type flip-flop(s). - inferred 2 Adder/Subtractor(s). - inferred 2 Multiplier(s). + inferred 40 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 1 Multiplier(s). Unit <divider> synthesized. @@ -142,9 +139,6 @@ Found registered multiplier on signal <_n0003>: - 1 register level(s) found in a register connected to the multiplier macro ouput. Pushing register(s) into the multiplier macro. - Found registered multiplier on signal <_n0004>: - - 1 register level(s) found in a register connected to the multiplier macro ouput. - Pushing register(s) into the multiplier macro. Advanced Registered AddSub inference ... Dynamic shift register inference ... @@ -153,14 +147,13 @@ Macro Statistics # Block RAMs : 1 - 1022x32-bit single-port block RAM : 1 -# Multipliers : 2 - 16x10-bit registered multiplier : 2 -# Adders/Subtractors : 2 - 10-bit subtractor : 1 - 42-bit adder : 1 + 254x16-bit single-port block RAM : 1 +# Multipliers : 1 + 16x8-bit registered multiplier : 1 +# Adders/Subtractors : 1 + 8-bit subtractor : 1 # Registers : 1 - 10-bit register : 1 + 8-bit register : 1 ========================================================================= @@ -169,11 +162,11 @@ ========================================================================= Optimizing unit <divider> ... -Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block divider, actual ratio is 1. +Found area constraint ratio of 100 (+ 5) on block divider, actual ratio is 0. ========================================================================= * Final Report * @@ -186,52 +179,50 @@ Keep Hierarchy : NO Design Statistics -# IOs : 32 +# IOs : 26 Macro Statistics : # RAM : 1 -# 1022x32-bit single-port block RAM: 1 -# Registers : 10 -# 1-bit register : 10 -# Adders/Subtractors : 2 -# 10-bit subtractor : 1 -# 42-bit adder : 1 -# Multipliers : 2 -# 16x10-bit registered multiplier: 2 +# 254x16-bit single-port block RAM: 1 +# Registers : 8 +# 1-bit register : 8 +# Adders/Subtractors : 1 +# 8-bit subtractor : 1 +# Multipliers : 1 +# 16x8-bit registered multiplier: 1 Cell Usage : -# BELS : 69 +# BELS : 13 # GND : 1 -# LUT1 : 5 -# LUT2 : 20 -# MUXCY : 23 +# LUT2 : 4 +# LUT3 : 2 +# LUT4 : 5 # VCC : 1 -# XORCY : 19 -# FlipFlops/Latches : 10 -# FDR : 9 +# FlipFlops/Latches : 8 +# FDR : 7 # FDS : 1 -# RAMS : 2 -# RAMB16_S18 : 2 +# RAMS : 1 +# RAMB16_S36 : 1 # Clock Buffers : 1 # BUFGP : 1 -# IO Buffers : 31 -# IBUF : 21 -# OBUF : 10 -# MULTs : 2 -# MULT18X18S : 2 +# IO Buffers : 25 +# IBUF : 17 +# OBUF : 8 +# MULTs : 1 +# MULT18X18S : 1 ========================================================================= Device utilization summary: --------------------------- -Selected Device : 2v250cs144-6 +Selected Device : 2v2000bg575-6 - Number of Slices: 19 out of 1536 1% - Number of Slice Flip Flops: 10 out of 3072 0% - Number of 4 input LUTs: 25 out of 3072 0% - Number of bonded IOBs: 32 out of 92 34% - Number of BRAMs: 2 out of 24 8% - Number of MULT18X18s: 2 out of 24 8% + Number of Slices: 6 out of 10752 0% + Number of Slice Flip Flops: 8 out of 21504 0% + Number of 4 input LUTs: 11 out of 21504 0% + Number of bonded IOBs: 26 out of 408 6% + Number of BRAMs: 1 out of 56 1% + Number of MULT18X18s: 1 out of 56 1% Number of GCLKs: 1 out of 16 6% @@ -247,16 +238,16 @@ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ -CLOCK | BUFGP | 12 | +CLOCK | BUFGP | 9 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -6 - Minimum period: 3.967ns (Maximum Frequency: 252.048MHz) - Minimum input arrival time before clock: 1.644ns - Maximum output required time after clock: 8.362ns + Minimum period: 3.832ns (Maximum Frequency: 260.994MHz) + Minimum input arrival time before clock: 1.615ns + Maximum output required time after clock: 5.229ns Maximum combinational path delay: No path found Timing Detail: @@ -265,77 +256,69 @@ ========================================================================= Timing constraint: Default period analysis for Clock 'CLOCK' - Clock period: 3.967ns (frequency: 252.048MHz) - Total number of paths / destination ports: 20 / 20 + Clock period: 3.832ns (frequency: 260.994MHz) + Total number of paths / destination ports: 8 / 8 ------------------------------------------------------------------------- -Delay: 3.967ns (Levels of Logic = 0) - Source: NUMERATOR2_9 (FF) - Destination: Mmult__n00041_inst_mult_0 (MULT) +Delay: 3.832ns (Levels of Logic = 0) + Source: NUMERATOR2_7 (FF) + Destination: Mmult__n00031_inst_mult_0 (MULT) Source Clock: CLOCK rising Destination Clock: CLOCK rising - Data Path: NUMERATOR2_9 to Mmult__n00041_inst_mult_0 + Data Path: NUMERATOR2_7 to Mmult__n00031_inst_mult_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDR:C->Q 2 0.449 0.519 NUMERATOR2_9 (NUMERATOR2_9) - MULT18X18S:B9 3.000 Mmult__n00041_inst_mult_0 + FDR:C->Q 1 0.449 0.382 NUMERATOR2_7 (NUMERATOR2_7) + MULT18X18S:B7 3.000 Mmult__n00031_inst_mult_0 ---------------------------------------- - Total 3.967ns (3.449ns logic, 0.519ns route) - (86.9% logic, 13.1% route) + Total 3.832ns (3.449ns logic, 0.382ns route) + (90.0% logic, 10.0% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' - Total number of paths / destination ports: 20 / 20 + Total number of paths / destination ports: 16 / 16 ------------------------------------------------------------------------- -Offset: 1.644ns (Levels of Logic = 1) +Offset: 1.615ns (Levels of Logic = 1) Source: RESET (PAD) - Destination: NUMERATOR2_7 (FF) + Destination: NUMERATOR2_5 (FF) Destination Clock: CLOCK rising - Data Path: RESET to NUMERATOR2_7 + Data Path: RESET to NUMERATOR2_5 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUF:I->O 20 0.653 0.769 RESET_IBUF (RESET_IBUF) + IBUF:I->O 16 0.653 0.740 RESET_IBUF (RESET_IBUF) FDR:R 0.222 NUMERATOR2_2 ---------------------------------------- - Total 1.644ns (0.875ns logic, 0.769ns route) - (53.2% logic, 46.8% route) + Total 1.615ns (0.875ns logic, 0.740ns route) + (54.2% logic, 45.8% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' - Total number of paths / destination ports: 299 / 10 + Total number of paths / destination ports: 8 / 8 ------------------------------------------------------------------------- -Offset: 8.362ns (Levels of Logic = 9) - Source: Mmult__n00041_inst_mult_0 (MULT) - Destination: QUOTIENT<9> (PAD) +Offset: 5.229ns (Levels of Logic = 1) + Source: Mmult__n00031_inst_mult_0 (MULT) + Destination: QUOTIENT<7> (PAD) Source Clock: CLOCK rising - Data Path: Mmult__n00041_inst_mult_0 to QUOTIENT<9> + Data Path: Mmult__n00031_inst_mult_0 to QUOTIENT<7> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - MULT18X18S:C->P25 1 2.073 0.548 Mmult__n00041_inst_mult_0 (PRODUCT2<25>) - LUT2:I1->O 1 0.347 0.000 divider_QUOTIENT<3>lut (N23) - MUXCY:S->O 1 0.235 0.000 divider_QUOTIENT<3>cy (divider_QUOTIENT<3>_cyo) - MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<4>cy (divider_QUOTIENT<4>_cyo) - MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<5>cy (divider_QUOTIENT<5>_cyo) - MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<6>cy (divider_QUOTIENT<6>_cyo) - MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<7>cy (divider_QUOTIENT<7>_cyo) - MUXCY:CI->O 0 0.042 0.000 divider_QUOTIENT<8>cy (divider_QUOTIENT<8>_cyo) - XORCY:CI->O 1 0.824 0.383 divider_QUOTIENT<9>_xor (QUOTIENT_9_OBUF) - OBUF:I->O 3.743 QUOTIENT_9_OBUF (QUOTIENT<9>) + MULT18X18S:C->P15 1 1.103 0.383 Mmult__n00031_inst_mult_0 (QUOTIENT_7_OBUF) + OBUF:I->O 3.743 QUOTIENT_7_OBUF (QUOTIENT<7>) ---------------------------------------- - Total 8.362ns (7.432ns logic, 0.930ns route) - (88.9% logic, 11.1% route) + Total 5.229ns (4.846ns logic, 0.383ns route) + (92.7% logic, 7.3% route) ========================================================================= -CPU : 5.28 / 5.66 s | Elapsed : 5.00 / 5.00 s +CPU : 4.83 / 5.22 s | Elapsed : 5.00 / 5.00 s --> -Total memory usage is 101628 kilobytes +Total memory usage is 121148 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 3 ( 0 filtered) 1.2 dirac/docs/synthesis_reports/common/fifo.syr http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/common/fifo.syr.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: fifo.syr =================================================================== RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/common/fifo.syr,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- fifo.syr 6 Sep 2006 18:41:01 -0000 1.1 +++ fifo.syr 19 Sep 2006 12:12:04 -0000 1.2 @@ -1,10 +1,10 @@ Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav -CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst -CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s --> Reading design: fifo.prj @@ -32,7 +32,7 @@ ---- Target Parameters Output File Name : "fifo" Output Format : NGC -Target Device : xc2v250-6-cs144 +Target Device : xc2v2000-6-bg575 ---- Source Options Top Module Name : fifo @@ -65,7 +65,7 @@ ---- General Options Optimization Goal : Speed -Optimization Effort : 1 +Optimization Effort : 2 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes @@ -95,19 +95,245 @@ ========================================================================= * HDL Compilation * ========================================================================= -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd" in Library work. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/FIFO.vhd" in Library work. Architecture rtl of Entity fifo is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity <fifo> (Architecture <rtl>). -ERROR:Xst:834 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd" line 13: Generic <WIDTH> has not been given a value. +Entity <fifo> analyzed. Unit <fifo> generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit <fifo>. + Related source file is "C:/Xilinx/bin/ArithmeticCoder/FIFO.vhd". + Found 256x1-bit dual-port distributed RAM for signal <GET_OUTPUT>. + ----------------------------------------------------------------------- + | aspect ratio | 256-word x 1-bit | | + | clock | connected to signal <CLOCK> | rise | + | write enable | connected to signal <WRITE_ENABLE> | high | + | address | connected to signal <WRITE_ADDRESS> | | + | dual address | connected to signal <READ_ADDRESS> | | + | data in | connected to signal <DATA_IN> | | + | data out | not connected | | + | dual data out | connected to signal <DATA_OUT> | | + | ram_style | Auto | | + ----------------------------------------------------------------------- +INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + Found 8-bit comparator equal for signal <$n0003> created at line 69. + Found 8-bit up counter for signal <READ_ADDRESS>. + Found 8-bit up counter for signal <WRITE_ADDRESS>. + Summary: + inferred 1 RAM(s). + inferred 2 Counter(s). + inferred 1 Comparator(s). +Unit <fifo> synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# LUT RAMs : 1 + 256x1-bit dual-port distributed RAM: 1 +# Counters : 2 + 8-bit up counter : 2 +# Comparators : 1 + 8-bit comparator equal : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit <fifo> ... +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block fifo, actual ratio is 0. +FlipFlop WRITE_ADDRESS_0 has been replicated 2 time(s) +FlipFlop WRITE_ADDRESS_1 has been replicated 2 time(s) +FlipFlop WRITE_ADDRESS_2 has been replicated 2 time(s) +FlipFlop WRITE_ADDRESS_3 has been replicated 2 time(s) + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : fifo.ngr +Top Level Output File Name : fifo +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 7 + +Macro Statistics : +# RAM : 1 +# 256x1-bit dual-port distributed RAM: 1 +# Registers : 2 +# 8-bit register : 2 +# Adders/Subtractors : 2 +# 8-bit adder : 2 +# Comparators : 1 +# 8-bit comparator equal : 1 + +Cell Usage : +# BELS : 62 +# GND : 1 +# INV : 2 +# LUT1_L : 14 +# LUT2 : 1 +# LUT3 : 6 +# LUT4_L : 4 +# MUXCY : 18 +# MUXF5 : 1 +# VCC : 1 +# XORCY : 14 +# FlipFlops/Latches : 24 +# FDRE : 24 +# RAMS : 4 +# RAM64X1D : 4 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 6 +# IBUF : 4 +# OBUF : 2 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2v2000bg575-6 + + Number of Slices: 40 out of 10752 0% + Number of Slice Flip Flops: 24 out of 21504 0% + Number of 4 input LUTs: 41 out of 21504 0% + Number of bonded IOBs: 7 out of 408 1% + Number of GCLKs: 1 out of 16 6% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +CLOCK | BUFGP | 28 | +-----------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -6 + + Minimum period: 4.346ns (Maximum Frequency: 230.123MHz) + Minimum input arrival time before clock: 2.595ns + Maximum output required time after clock: 7.806ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLOCK' + Clock period: 4.346ns (frequency: 230.123MHz) + Total number of paths / destination ports: 276 / 84 +------------------------------------------------------------------------- +Delay: 4.346ns (Levels of Logic = 6) + Source: READ_ADDRESS_1 (FF) + Destination: READ_ADDRESS_6 (FF) + Source Clock: CLOCK rising + Destination Clock: CLOCK rising + + Data Path: READ_ADDRESS_1 to READ_ADDRESS_6 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 18 0.449 0.789 READ_ADDRESS_1 (READ_ADDRESS_1) + LUT4_L:I3->LO 1 0.347 0.000 Eq_stagelut (N4) + MUXCY:S->O 1 0.235 0.000 Eq_stagecy (Eq_stage_cyo) + MUXCY:CI->O 1 0.042 0.000 Eq_stagecy_rn_0 (Eq_stage_cyo1) + MUXCY:CI->O 1 0.042 0.000 Eq_stagecy_rn_1 (Eq_stage_cyo2) + MUXCY:CI->O 2 0.601 0.684 Eq_stagecy_rn_2 (EMPTY_OBUF) + LUT2:I1->O 8 0.347 0.621 _n00021 (_n0002) + FDRE:CE 0.190 READ_ADDRESS_0 + ---------------------------------------- + Total 4.346ns (2.253ns logic, 2.093ns route) + (51.8% logic, 48.2% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' + Total number of paths / destination ports: 56 / 56 +------------------------------------------------------------------------- +Offset: 2.595ns (Levels of Logic = 2) + Source: WRITE_ENABLE (PAD) + Destination: Mram_GET_OUTPUT_inst_ramx1d_2 (RAM) + Destination Clock: CLOCK rising + + Data Path: WRITE_ENABLE to Mram_GET_OUTPUT_inst_ramx1d_2 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 20 0.653 0.796 WRITE_ENABLE_IBUF (WRITE_ENABLE_IBUF) + LUT3:I2->O 1 0.347 0.382 Mram_GET_OUTPUT_inst_lut2_41 (Mram_GET_OUTPUT_inst_lut2_4) + RAM64X1D:WE 0.416 Mram_GET_OUTPUT_inst_ramx1d_0 + ---------------------------------------- + Total 2.595ns (1.416ns logic, 1.179ns route) + (54.6% logic, 45.4% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' + Total number of paths / destination ports: 47 / 2 +------------------------------------------------------------------------- +Offset: 7.806ns (Levels of Logic = 4) + Source: READ_ADDRESS_0 (FF) + Destination: DATA_OUT<0> (PAD) + Source Clock: CLOCK rising + + Data Path: READ_ADDRESS_0 to DATA_OUT<0> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 18 0.449 0.756 READ_ADDRESS_0 (READ_ADDRESS_0) + RAM64X1D:DPRA0->DPO 1 1.236 0.548 Mram_GET_OUTPUT_inst_ramx1d_0 (Mram_GET_OUTPUT__net8) + LUT3:I1->O 1 0.347 0.000 Mram_GET_OUTPUT_inst_lut3_21 (Mram_GET_OUTPUT_inst_lut3_2) + MUXF5:I0->O 1 0.345 0.383 Mram_GET_OUTPUT_inst_mux_f5_1 (DATA_OUT) + OBUF:I->O 3.743 DATA_OUT_0_OBUF (DATA_OUT<0>) + ---------------------------------------- + Total 7.806ns (6.120ns logic, 1.687ns route) + (78.4% logic, 21.6% route) + +========================================================================= +CPU : 4.76 / 5.14 s | Elapsed : 5.00 / 5.00 s + --> -Total memory usage is 77708 kilobytes +Total memory usage is 121148 kilobytes -Number of errors : 1 ( 0 filtered) +Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) -Number of infos : 0 ( 0 filtered) +Number of infos : 1 ( 0 filtered) 1.2 dirac/docs/synthesis_reports/common/halving_manager.syr http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/common/halving_manager.syr.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: halving_manager.syr =================================================================== RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/common/halving_manager.syr,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- halving_manager.syr 6 Sep 2006 18:41:01 -0000 1.1 +++ halving_manager.syr 19 Sep 2006 12:12:04 -0000 1.2 @@ -1,10 +1,10 @@ Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav -CPU : 0.00 / 0.31 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst -CPU : 0.00 / 0.31 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s --> Reading design: halving_manager.prj @@ -32,7 +32,7 @@ ---- Target Parameters Output File Name : "halving_manager" Output Format : NGC -Target Device : xc2v250-6-cs144 +Target Device : xc2v2000-6-bg575 ---- Source Options Top Module Name : halving_manager @@ -65,7 +65,7 @@ ---- General Options Optimization Goal : Speed -Optimization Effort : 1 +Optimization Effort : 2 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes @@ -95,17 +95,18 @@ ========================================================================= * HDL Compilation * ========================================================================= -Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" in Library work. +Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" in Library work. Architecture rtl of Entity halving_manager is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity <halving_manager> (Architecture <rtl>). -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch. -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:1610 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 78: Width mismatch. <NUMERATOR2> has a width of 8 bits but assigned expression is 10-bit wide. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch. Entity <halving_manager> analyzed. Unit <halving_manager> generated. @@ -114,7 +115,7 @@ ========================================================================= Synthesizing Unit <halving_manager>. - Related source file is "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd". + Related source file is "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd". Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108. Found 3-bit 4-to-1 multiplexer for signal <$n0050>. Found 3-bit 4-to-1 multiplexer for signal <$n0051>. @@ -208,13 +209,13 @@ Found 3-bit addsub for signal <$n0142>. Found 3-bit addsub for signal <$n0143>. Found 3-bit addsub for signal <$n0144>. - Found 10-bit comparator greater for signal <$n0147> created at line 99. + Found 8-bit comparator greater for signal <$n0147> created at line 99. Found 3-bit comparator greater for signal <$n0241> created at line 108. Found 1-bit register for signal <AFTER_TRIGGER>. - Found 10-bit register for signal <DENOMINATOR>. - Found 10-bit adder for signal <DENOMINATOR2>. - Found 10-bit register for signal <NUMERATOR>. - Found 10-bit adder for signal <NUMERATOR2>. + Found 8-bit register for signal <DENOMINATOR>. + Found 8-bit adder for signal <DENOMINATOR2>. + Found 8-bit register for signal <NUMERATOR>. + Found 8-bit adder for signal <NUMERATOR2>. Found 138-bit register for signal <SHIFTS>. Summary: inferred 139 D-type flip-flop(s). @@ -239,15 +240,15 @@ Macro Statistics # Adders/Subtractors : 48 - 10-bit adder : 2 3-bit addsub : 46 + 8-bit adder : 2 # Registers : 49 1-bit register : 1 - 10-bit register : 2 3-bit register : 46 + 8-bit register : 2 # Comparators : 2 - 10-bit comparator greater : 1 3-bit comparator greater : 1 + 8-bit comparator greater : 1 # Multiplexers : 47 3-bit 4-to-1 multiplexer : 46 3-bit 46-to-1 multiplexer : 1 @@ -259,11 +260,11 @@ ========================================================================= Optimizing unit <halving_manager> ... -Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. +Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block halving_manager, actual ratio is 16. +Found area constraint ratio of 100 (+ 5) on block halving_manager, actual ratio is 2. ========================================================================= * Final Report * @@ -276,61 +277,62 @@ Keep Hierarchy : NO Design Statistics -# IOs : 51 +# IOs : 43 Macro Statistics : -# Registers : 67 -# 1-bit register : 21 +# Registers : 63 +# 1-bit register : 17 # 3-bit register : 46 # Multiplexers : 47 # 3-bit 4-to-1 multiplexer : 46 # 3-bit 46-to-1 multiplexer : 1 # Adders/Subtractors : 2 -# 10-bit adder : 2 +# 8-bit adder : 2 # Comparators : 2 -# 10-bit comparator greater : 1 # 3-bit comparator greater : 1 +# 8-bit comparator greater : 1 # Xors : 92 # 1-bit xor3 : 92 Cell Usage : -# BELS : 570 +# BELS : 550 # GND : 1 # INV : 1 -# LUT1 : 15 +# LUT1 : 11 # LUT2 : 9 -# LUT3 : 70 -# LUT3_L : 132 -# LUT4 : 118 -# LUT4_D : 18 +# LUT3 : 68 +# LUT3_D : 1 +# LUT3_L : 127 +# LUT4 : 117 +# LUT4_D : 17 # LUT4_L : 112 -# MUXCY : 18 +# MUXCY : 14 # MUXF5 : 35 # MUXF6 : 15 # MUXF7 : 6 # MUXF8 : 3 # VCC : 1 -# XORCY : 16 -# FlipFlops/Latches : 159 +# XORCY : 12 +# FlipFlops/Latches : 155 # FDR : 1 -# FDRE : 156 +# FDRE : 152 # FDSE : 2 # Clock Buffers : 1 # BUFGP : 1 -# IO Buffers : 50 -# IBUF : 29 -# OBUF : 21 +# IO Buffers : 42 +# IBUF : 25 +# OBUF : 17 ========================================================================= Device utilization summary: --------------------------- -Selected Device : 2v250cs144-6 +Selected Device : 2v2000bg575-6 - Number of Slices: 263 out of 1536 17% - Number of Slice Flip Flops: 159 out of 3072 5% - Number of 4 input LUTs: 474 out of 3072 15% - Number of bonded IOBs: 51 out of 92 55% + Number of Slices: 256 out of 10752 2% + Number of Slice Flip Flops: 155 out of 21504 0% + Number of 4 input LUTs: 462 out of 21504 2% + Number of bonded IOBs: 43 out of 408 10% Number of GCLKs: 1 out of 16 6% @@ -346,7 +348,7 @@ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ -CLOCK | BUFGP | 159 | +CLOCK | BUFGP | 155 | -----------------------------------+------------------------+-------+ Timing Summary: @@ -355,8 +357,8 @@ Minimum period: 6.759ns (Maximum Frequency: 147.951MHz) Minimum input arrival time before clock: 7.315ns - Maximum output required time after clock: 11.278ns - Maximum combinational path delay: 11.850ns + Maximum output required time after clock: 11.248ns + Maximum combinational path delay: 11.821ns Timing Detail: -------------- @@ -365,15 +367,15 @@ ========================================================================= Timing constraint: Default period analysis for Clock 'CLOCK' Clock period: 6.759ns (frequency: 147.951MHz) - Total number of paths / destination ports: 44219 / 316 + Total number of paths / destination ports: 42357 / 308 ------------------------------------------------------------------------- Delay: 6.759ns (Levels of Logic = 8) Source: SHIFTS_0_1 (FF) - Destination: SHIFTS_8_2 (FF) + Destination: SHIFTS_0_2 (FF) Source Clock: CLOCK rising Destination Clock: CLOCK rising - Data Path: SHIFTS_0_1 to SHIFTS_8_2 + Data Path: SHIFTS_0_1 to SHIFTS_0_2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ @@ -382,105 +384,105 @@ MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_14 (MUX_BLOCK_CONTEXT<1>_MUXF515) MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_9 (MUX_BLOCK_CONTEXT<0>_MUXF67) MUXF7:I0->O 2 0.354 0.743 CONTEXT<2>_rn_3 (MUX_BLOCK_CONTEXT<2>_MUXF73) - LUT4_L:I0->LO 1 0.347 0.000 _n0241106_1_F (N760) + LUT4_L:I0->LO 1 0.347 0.000 _n0241106_1_F (N744) MUXF5:I0->O 4 0.345 0.579 _n0241106_1 (_n0241106) LUT4_D:I2->O 15 0.347 0.758 Ker601 (N60) - LUT4:I2->O 3 0.347 0.535 _n0484 (_n0484) - FDRE:CE 0.190 SHIFTS_20_0 + LUT4:I2->O 3 0.347 0.535 _n0486 (_n0486) + FDRE:CE 0.190 SHIFTS_16_0 ---------------------------------------- Total 6.759ns (3.425ns logic, 3.334ns route) (50.7% logic, 49.3% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' - Total number of paths / destination ports: 39794 / 476 + Total number of paths / destination ports: 38734 / 464 ------------------------------------------------------------------------- Offset: 7.315ns (Levels of Logic = 9) Source: CONTEXT<4> (PAD) - Destination: SHIFTS_8_2 (FF) + Destination: SHIFTS_0_2 (FF) Destination Clock: CLOCK rising - Data Path: CONTEXT<4> to SHIFTS_8_2 + Data Path: CONTEXT<4> to SHIFTS_0_2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 53 0.653 1.069 CONTEXT_4_IBUF (CONTEXT_4_IBUF) - LUT3_L:I0->LO 1 0.347 0.000 CONTEXT<4>19 (MUX_BLOCK_N26) - MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_8 (MUX_BLOCK_CONTEXT<1>_MUXF59) - MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_6 (MUX_BLOCK_CONTEXT<0>_MUXF64) - MUXF7:I1->O 2 0.354 0.743 CONTEXT<2>_rn_2 (MUX_BLOCK_CONTEXT<2>_MUXF72) - LUT4_L:I0->LO 1 0.347 0.000 _n0241106_1_G (N761) - MUXF5:I1->O 4 0.345 0.579 _n0241106_1 (_n0241106) + LUT3_L:I0->LO 1 0.347 0.000 CONTEXT<4>25 (MUX_BLOCK_N32) + MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_11 (MUX_BLOCK_CONTEXT<1>_MUXF512) + MUXF6:I1->O 1 0.354 0.000 CONTEXT<0>_rn_8 (MUX_BLOCK_CONTEXT<0>_MUXF66) + MUXF7:I1->O 2 0.354 0.743 CONTEXT<2>_rn_3 (MUX_BLOCK_CONTEXT<2>_MUXF73) + LUT4_L:I0->LO 1 0.347 0.000 _n0241106_1_F (N744) + MUXF5:I0->O 4 0.345 0.579 _n0241106_1 (_n0241106) LUT4_D:I2->O 15 0.347 0.758 Ker601 (N60) - LUT4:I2->O 3 0.347 0.535 _n0484 (_n0484) - FDRE:CE 0.190 SHIFTS_20_0 + LUT4:I2->O 3 0.347 0.535 _n0486 (_n0486) + FDRE:CE 0.190 SHIFTS_16_0 ---------------------------------------- Total 7.315ns (3.629ns logic, 3.686ns route) (49.6% logic, 50.4% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' - Total number of paths / destination ports: 3148 / 21 + Total number of paths / destination ports: 2514 / 17 ------------------------------------------------------------------------- -Offset: 11.278ns (Levels of Logic = 10) +Offset: 11.248ns (Levels of Logic = 10) Source: SHIFTS_0_2 (FF) - Destination: DENOMINATOR_OUT<9> (PAD) + Destination: DENOMINATOR_OUT<7> (PAD) Source Clock: CLOCK rising - Data Path: SHIFTS_0_2 to DENOMINATOR_OUT<9> + Data Path: SHIFTS_0_2 to DENOMINATOR_OUT<7> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDRE:C->Q 3 0.449 0.700 SHIFTS_0_2 (SHIFTS_0_2) + FDRE:C->Q 3 0.449 0.701 SHIFTS_0_2 (SHIFTS_0_2) LUT3_L:I1->LO 1 0.347 0.000 CONTEXT<4>47 (MUX_BLOCK_N60) MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_22 (MUX_BLOCK_CONTEXT<1>_MUXF523) MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_16 (MUX_BLOCK_CONTEXT<0>_MUXF611) MUXF7:I0->O 2 0.354 0.000 CONTEXT<2>_rn_6 (MUX_BLOCK_CONTEXT<2>_MUXF75) MUXF8:I0->O 1 0.354 0.547 CONTEXT<3>_rn_1 (MUX_BLOCK_CONTEXT<3>_MUXF82) - LUT4:I1->O 16 0.347 0.905 _n0241106 (CHOICE33) - LUT4:I1->O 1 0.347 0.415 _n0145_SW1 (N718) - LUT4:I3->O 20 0.347 0.994 _n0145 (_n0145) + LUT4:I1->O 16 0.347 0.905 _n0241106 (CHOICE31) + LUT4:I1->O 1 0.347 0.415 _n0145_SW1 (N702) + LUT4:I3->O 16 0.347 0.964 _n0145 (_n0145) LUT3:I0->O 1 0.347 0.383 NUMERATOR_OUT<0>1 (NUMERATOR_OUT_0_OBUF) OBUF:I->O 3.743 NUMERATOR_OUT_0_OBUF (NUMERATOR_OUT<0>) ---------------------------------------- - Total 11.278ns (7.334ns logic, 3.944ns route) - (65.0% logic, 35.0% route) + Total 11.248ns (7.334ns logic, 3.914ns route) + (65.2% logic, 34.8% route) ========================================================================= Timing constraint: Default path analysis - Total number of paths / destination ports: 2813 / 21 + Total number of paths / destination ports: 2277 / 17 ------------------------------------------------------------------------- -Delay: 11.850ns (Levels of Logic = 11) +Delay: 11.821ns (Levels of Logic = 11) Source: CONTEXT<4> (PAD) - Destination: DENOMINATOR_OUT<9> (PAD) + Destination: DENOMINATOR_OUT<7> (PAD) - Data Path: CONTEXT<4> to DENOMINATOR_OUT<9> + Data Path: CONTEXT<4> to DENOMINATOR_OUT<7> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 53 0.653 1.069 CONTEXT_4_IBUF (CONTEXT_4_IBUF) - LUT3_L:I0->LO 1 0.347 0.000 CONTEXT<4>35 (MUX_BLOCK_N48) - MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_16 (MUX_BLOCK_CONTEXT<1>_MUXF517) - MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_13 (MUX_BLOCK_CONTEXT<0>_MUXF68) - MUXF7:I1->O 2 0.354 0.000 CONTEXT<2>_rn_5 (MUX_BLOCK_CONTEXT<2>_MUXF74) - MUXF8:I1->O 1 0.354 0.547 CONTEXT<3>_rn_1 (MUX_BLOCK_CONTEXT<3>_MUXF82) - LUT4:I1->O 16 0.347 0.905 _n0241106 (CHOICE33) - LUT4:I1->O 1 0.347 0.415 _n0145_SW1 (N718) - LUT4:I3->O 20 0.347 0.994 _n0145 (_n0145) + LUT3_L:I0->LO 1 0.347 0.000 CONTEXT<4>41 (MUX_BLOCK_N54) + MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_19 (MUX_BLOCK_CONTEXT<1>_MUXF520) + MUXF6:I1->O 1 0.354 0.000 CONTEXT<0>_rn_15 (MUX_BLOCK_CONTEXT<0>_MUXF610) + MUXF7:I1->O 2 0.354 0.000 CONTEXT<2>_rn_6 (MUX_BLOCK_CONTEXT<2>_MUXF75) + MUXF8:I0->O 1 0.354 0.547 CONTEXT<3>_rn_1 (MUX_BLOCK_CONTEXT<3>_MUXF82) + LUT4:I1->O 16 0.347 0.905 _n0241106 (CHOICE31) + LUT4:I1->O 1 0.347 0.415 _n0145_SW1 (N702) + LUT4:I3->O 16 0.347 0.964 _n0145 (_n0145) LUT3:I0->O 1 0.347 0.383 NUMERATOR_OUT<0>1 (NUMERATOR_OUT_0_OBUF) OBUF:I->O 3.743 NUMERATOR_OUT_0_OBUF (NUMERATOR_OUT<0>) ---------------------------------------- - Total 11.850ns (7.538ns logic, 4.312ns route) - (63.6% logic, 36.4% route) + Total 11.821ns (7.538ns logic, 4.283ns route) + (63.8% logic, 36.2% route) ========================================================================= -CPU : 13.28 / 13.63 s | Elapsed : 14.00 / 14.00 s +CPU : 15.17 / 15.55 s | Elapsed : 15.00 / 15.00 s --> -Total memory usage is 103676 kilobytes +Total memory usage is 124220 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 4 ( 0 filtered) +Number of warnings : 5 ( 0 filtered) Number of infos : 1 ( 0 filtered) 1.2 dirac/docs/synthesis_reports/common/input_control.syr http://www.opencores.org/cvsweb.shtml/dirac/docs/synthesis_reports/common/input_control.syr.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: input_control.syr =================================================================== RCS file: /cvsroot/petebleackley/dirac/docs/synthesis_reports/common/input_control.syr,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- input_control.syr 6 Sep 2006 18:41:01 -0000 1.1 +++ input_control.syr 19 Sep 2006 12:12:04 -0000 1.2 @@ -1,10 +1,10 @@