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From: cvs at opencores.org<cvs@o...>
Date: Sat Jul 29 00:32:25 CEST 2006
Subject: [cvs-checkins] MODIFIED: fpuvhdl ...
Date: 00/06/07 29:00:32

Modified: fpuvhdl/fpuvhdl/adder fpadd_normalize_struct.vhd
fpadd_pipeline.vhd fpadd_single_cycle.vhd
fpadd_stage1_struct.vhd fpadd_stage2_struct.vhd
fpadd_stage3_struct.vhd fpadd_stage4_struct.vhd
fpadd_stage5_struct.vhd fpadd_stage6_struct.vhd
Log:
Removed reference to the HAVOC library. Using default work.

Corrected bug in the underflow check of the multiplier.


Revision Changes Path
1.2 fpuvhdl/fpuvhdl/adder/fpadd_normalize_struct.vhd

http://www.opencores.org/cvsweb.shtml/fpuvhdl/fpuvhdl/adder/fpadd_normalize_struct.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: fpadd_normalize_struct.vhd
===================================================================
RCS file: /cvsroot/gmarcus/fpuvhdl/fpuvhdl/adder/fpadd_normalize_struct.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- fpadd_normalize_struct.vhd 5 Nov 2004 14:06:30 -0000 1.1
+++ fpadd_normalize_struct.vhd 28 Jul 2006 22:32:25 -0000 1.2
@@ -1,4 +1,4 @@
--- VHDL Entity HAVOC.FPadd_normalize.symbol
+-- VHDL Entity work.FPadd_normalize.symbol
--
-- Created by
-- Guillermo Marcus, gmarcus@i...
@@ -27,7 +27,7 @@
END FPadd_normalize ;

--
--- VHDL Architecture HAVOC.FPadd_normalize.struct
+-- VHDL Architecture work.FPadd_normalize.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@i...
@@ -44,8 +44,6 @@
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

-LIBRARY HAVOC;
-
ARCHITECTURE struct OF FPadd_normalize IS

-- Architecture declarations
@@ -75,7 +73,7 @@

-- Optional embedded configurations
-- pragma synthesis_off
- FOR ALL : FPlzc USE ENTITY HAVOC.FPlzc;
+ FOR ALL : FPlzc USE ENTITY work.FPlzc;
-- pragma synthesis_on





1.2 fpuvhdl/fpuvhdl/adder/fpadd_pipeline.vhd

http://www.opencores.org/cvsweb.shtml/fpuvhdl/fpuvhdl/adder/fpadd_pipeline.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: fpadd_pipeline.vhd
===================================================================
RCS file: /cvsroot/gmarcus/fpuvhdl/fpuvhdl/adder/fpadd_pipeline.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- fpadd_pipeline.vhd 5 Nov 2004 14:06:30 -0000 1.1
+++ fpadd_pipeline.vhd 28 Jul 2006 22:32:25 -0000 1.2
@@ -1,4 +1,4 @@
--- VHDL Entity HAVOC.FPadd.symbol
+-- VHDL Entity work.FPadd.symbol
--
-- Created by
-- Guillermo Marcus, gmarcus@i...
@@ -27,7 +27,7 @@
END FPadd ;

--
--- VHDL Architecture HAVOC.FPadd.pipeline
+-- VHDL Architecture work.FPadd.pipeline
--
-- Created by
-- Guillermo Marcus, gmarcus@i...
@@ -43,8 +43,6 @@
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-LIBRARY HAVOC;
-
ARCHITECTURE pipeline OF FPadd IS

-- Architecture declarations
@@ -237,12 +235,12 @@ -- Optional embedded configurations -- pragma synthesis_off - FOR ALL : FPadd_stage1 USE ENTITY HAVOC.FPadd_stage1; - FOR ALL : FPadd_stage2 USE ENTITY HAVOC.FPadd_stage2; - FOR ALL : FPadd_stage3 USE ENTITY HAVOC.FPadd_stage3; - FOR ALL : FPadd_stage4 USE ENTITY HAVOC.FPadd_stage4; - FOR ALL : FPadd_stage5 USE ENTITY HAVOC.FPadd_stage5; - FOR ALL : FPadd_stage6 USE ENTITY HAVOC.FPadd_stage6; + FOR ALL : FPadd_stage1 USE ENTITY work.FPadd_stage1; + FOR ALL : FPadd_stage2 USE ENTITY work.FPadd_stage2; + FOR ALL : FPadd_stage3 USE ENTITY work.FPadd_stage3; + FOR ALL : FPadd_stage4 USE ENTITY work.FPadd_stage4; + FOR ALL : FPadd_stage5 USE ENTITY work.FPadd_stage5; + FOR ALL : FPadd_stage6 USE ENTITY work.FPadd_stage6; -- pragma synthesis_on 1.2 fpuvhdl/fpuvhdl/adder/fpadd_single_cycle.vhd http://www.opencores.org/cvsweb.shtml/fpuvhdl/fpuvhdl/adder/fpadd_single_cycle.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: fpadd_single_cycle.vhd =================================================================== RCS file: /cvsroot/gmarcus/fpuvhdl/fpuvhdl/adder/fpadd_single_cycle.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- fpadd_single_cycle.vhd 5 Nov 2004 14:06:30 -0000 1.1 +++ fpadd_single_cycle.vhd 28 Jul 2006 22:32:25 -0000 1.2 @@ -1,4 +1,4 @@ --- VHDL Entity HAVOC.FPadd.symbol +-- VHDL Entity work.FPadd.symbol -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -27,7 +27,7 @@ END FPadd ; -- --- VHDL Architecture HAVOC.FPadd.single_cycle +-- VHDL Architecture work.FPadd.single_cycle -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -43,8 +43,6 @@ USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -LIBRARY HAVOC; - ARCHITECTURE single_cycle OF FPadd IS -- Architecture declarations @@ -220,15 +218,15 @@ -- Optional embedded configurations -- pragma synthesis_off - FOR ALL : FPadd_normalize USE ENTITY HAVOC.FPadd_normalize; - FOR ALL : FPalign USE ENTITY HAVOC.FPalign; - FOR ALL : FPinvert USE ENTITY HAVOC.FPinvert; - FOR ALL : FPnormalize USE ENTITY HAVOC.FPnormalize; - FOR ALL : FPround USE ENTITY HAVOC.FPround; - FOR ALL : FPselComplement USE ENTITY HAVOC.FPselComplement; - FOR ALL : FPswap USE ENTITY HAVOC.FPswap; - FOR ALL : PackFP USE ENTITY HAVOC.PackFP; - FOR ALL : UnpackFP USE ENTITY HAVOC.UnpackFP; + FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize; + FOR ALL : FPalign USE ENTITY work.FPalign; + FOR ALL : FPinvert USE ENTITY work.FPinvert; + FOR ALL : FPnormalize USE ENTITY work.FPnormalize; + FOR ALL : FPround USE ENTITY work.FPround; + FOR ALL : FPselComplement USE ENTITY work.FPselComplement; + FOR ALL : FPswap USE ENTITY work.FPswap; + FOR ALL : PackFP USE ENTITY work.PackFP; + FOR ALL : UnpackFP USE ENTITY work.UnpackFP; -- pragma synthesis_on 1.2 fpuvhdl/fpuvhdl/adder/fpadd_stage1_struct.vhd http://www.opencores.org/cvsweb.shtml/fpuvhdl/fpuvhdl/adder/fpadd_stage1_struct.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: fpadd_stage1_struct.vhd =================================================================== RCS file: /cvsroot/gmarcus/fpuvhdl/fpuvhdl/adder/fpadd_stage1_struct.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- fpadd_stage1_struct.vhd 5 Nov 2004 14:06:30 -0000 1.1 +++ fpadd_stage1_struct.vhd 28 Jul 2006 22:32:25 -0000 1.2 @@ -1,4 +1,4 @@ --- VHDL Entity HAVOC.FPadd_stage1.interface +-- VHDL Entity work.FPadd_stage1.interface -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -41,7 +41,7 @@ END FPadd_stage1 ; -- --- VHDL Architecture HAVOC.FPadd_stage1.struct +-- VHDL Architecture work.FPadd_stage1.struct -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -57,8 +57,6 @@ USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -LIBRARY HAVOC; - ARCHITECTURE struct OF FPadd_stage1 IS -- Architecture declarations @@ -103,7 +101,7 @@ -- Optional embedded configurations -- pragma synthesis_off - FOR ALL : UnpackFP USE ENTITY HAVOC.UnpackFP; + FOR ALL : UnpackFP USE ENTITY work.UnpackFP; -- pragma synthesis_on 1.2 fpuvhdl/fpuvhdl/adder/fpadd_stage2_struct.vhd http://www.opencores.org/cvsweb.shtml/fpuvhdl/fpuvhdl/adder/fpadd_stage2_struct.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: fpadd_stage2_struct.vhd =================================================================== RCS file: /cvsroot/gmarcus/fpuvhdl/fpuvhdl/adder/fpadd_stage2_struct.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- fpadd_stage2_struct.vhd 5 Nov 2004 14:06:30 -0000 1.1 +++ fpadd_stage2_struct.vhd 28 Jul 2006 22:32:25 -0000 1.2 @@ -1,4 +1,4 @@ --- VHDL Entity HAVOC.FPadd_stage2.interface +-- VHDL Entity work.FPadd_stage2.interface -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -49,7 +49,7 @@ END FPadd_stage2 ; -- --- VHDL Architecture HAVOC.FPadd_stage2.struct +-- VHDL Architecture work.FPadd_stage2.struct -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -65,8 +65,6 @@ USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -LIBRARY HAVOC; - ARCHITECTURE struct OF FPadd_stage2 IS -- Architecture declarations @@ -123,8 +121,8 @@ -- Optional embedded configurations -- pragma synthesis_off - FOR ALL : FPalign USE ENTITY HAVOC.FPalign; - FOR ALL : FPswap USE ENTITY HAVOC.FPswap; + FOR ALL : FPalign USE ENTITY work.FPalign; + FOR ALL : FPswap USE ENTITY work.FPswap; -- pragma synthesis_on 1.2 fpuvhdl/fpuvhdl/adder/fpadd_stage3_struct.vhd http://www.opencores.org/cvsweb.shtml/fpuvhdl/fpuvhdl/adder/fpadd_stage3_struct.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: fpadd_stage3_struct.vhd =================================================================== RCS file: /cvsroot/gmarcus/fpuvhdl/fpuvhdl/adder/fpadd_stage3_struct.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- fpadd_stage3_struct.vhd 5 Nov 2004 14:06:30 -0000 1.1 +++ fpadd_stage3_struct.vhd 28 Jul 2006 22:32:25 -0000 1.2 @@ -1,4 +1,4 @@ --- VHDL Entity HAVOC.FPadd_stage3.interface +-- VHDL Entity work.FPadd_stage3.interface -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -41,7 +41,7 @@ END FPadd_stage3 ; -- --- VHDL Architecture HAVOC.FPadd_stage3.struct +-- VHDL Architecture work.FPadd_stage3.struct -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -57,8 +57,6 @@ USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -LIBRARY HAVOC; - ARCHITECTURE struct OF FPadd_stage3 IS -- Architecture declarations @@ -86,7 +84,7 @@ -- Optional embedded configurations -- pragma synthesis_off - FOR ALL : FPinvert USE ENTITY HAVOC.FPinvert; + FOR ALL : FPinvert USE ENTITY work.FPinvert; -- pragma synthesis_on 1.2 fpuvhdl/fpuvhdl/adder/fpadd_stage4_struct.vhd http://www.opencores.org/cvsweb.shtml/fpuvhdl/fpuvhdl/adder/fpadd_stage4_struct.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: fpadd_stage4_struct.vhd =================================================================== RCS file: /cvsroot/gmarcus/fpuvhdl/fpuvhdl/adder/fpadd_stage4_struct.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- fpadd_stage4_struct.vhd 5 Nov 2004 14:06:30 -0000 1.1 +++ fpadd_stage4_struct.vhd 28 Jul 2006 22:32:25 -0000 1.2 @@ -1,4 +1,4 @@ --- VHDL Entity HAVOC.FPadd_stage4.interface +-- VHDL Entity work.FPadd_stage4.interface -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -38,7 +38,7 @@ END FPadd_stage4 ; -- --- VHDL Architecture HAVOC.FPadd_stage4.struct +-- VHDL Architecture work.FPadd_stage4.struct -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -54,8 +54,6 @@ USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -LIBRARY HAVOC; - ARCHITECTURE struct OF FPadd_stage4 IS -- Architecture declarations @@ -98,8 +96,8 @@ -- Optional embedded configurations -- pragma synthesis_off - FOR ALL : FPadd_normalize USE ENTITY HAVOC.FPadd_normalize; - FOR ALL : FPselComplement USE ENTITY HAVOC.FPselComplement; + FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize; + FOR ALL : FPselComplement USE ENTITY work.FPselComplement; -- pragma synthesis_on 1.2 fpuvhdl/fpuvhdl/adder/fpadd_stage5_struct.vhd http://www.opencores.org/cvsweb.shtml/fpuvhdl/fpuvhdl/adder/fpadd_stage5_struct.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: fpadd_stage5_struct.vhd =================================================================== RCS file: /cvsroot/gmarcus/fpuvhdl/fpuvhdl/adder/fpadd_stage5_struct.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- fpadd_stage5_struct.vhd 5 Nov 2004 14:06:30 -0000 1.1 +++ fpadd_stage5_struct.vhd 28 Jul 2006 22:32:25 -0000 1.2 @@ -1,4 +1,4 @@ --- VHDL Entity HAVOC.FPadd_stage5.interface +-- VHDL Entity work.FPadd_stage5.interface -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -39,7 +39,7 @@ END FPadd_stage5 ; -- --- VHDL Architecture HAVOC.FPadd_stage5.struct +-- VHDL Architecture work.FPadd_stage5.struct -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -55,8 +55,6 @@ USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -LIBRARY HAVOC; - ARCHITECTURE struct OF FPadd_stage5 IS -- Architecture declarations @@ -94,8 +92,8 @@ -- Optional embedded configurations -- pragma synthesis_off - FOR ALL : FPnormalize USE ENTITY HAVOC.FPnormalize; - FOR ALL : FPround USE ENTITY HAVOC.FPround; + FOR ALL : FPnormalize USE ENTITY work.FPnormalize; + FOR ALL : FPround USE ENTITY work.FPround; -- pragma synthesis_on 1.2 fpuvhdl/fpuvhdl/adder/fpadd_stage6_struct.vhd http://www.opencores.org/cvsweb.shtml/fpuvhdl/fpuvhdl/adder/fpadd_stage6_struct.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: fpadd_stage6_struct.vhd =================================================================== RCS file: /cvsroot/gmarcus/fpuvhdl/fpuvhdl/adder/fpadd_stage6_struct.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- fpadd_stage6_struct.vhd 5 Nov 2004 14:06:30 -0000 1.1 +++ fpadd_stage6_struct.vhd 28 Jul 2006 22:32:25 -0000 1.2 @@ -1,4 +1,4 @@ --- VHDL Entity HAVOC.FPadd_stage6.interface +-- VHDL Entity work.FPadd_stage6.interface -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -32,7 +32,7 @@ END FPadd_stage6 ; -- --- VHDL Architecture HAVOC.FPadd_stage6.struct +-- VHDL Architecture work.FPadd_stage6.struct -- -- Created by -- Guillermo Marcus, gmarcus@i... @@ -48,8 +48,6 @@ USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -LIBRARY HAVOC; - ARCHITECTURE struct OF FPadd_stage6 IS -- Architecture declarations @@ -77,7 +75,7 @@ -- Optional embedded configurations -- pragma synthesis_off - FOR ALL : PackFP USE ENTITY HAVOC.PackFP; + FOR ALL : PackFP USE ENTITY work.PackFP; -- pragma synthesis_on