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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Jul 24 17:38:57 CEST 2006
Subject: [cvs-checkins] MODIFIED: mb-jpeg ...
Date: 00/06/07 24:17:38 Added: mb-jpeg/pcores/fsl_dct_v1_00_a/data fsl_dct_v2_1_0.mpd
fsl_dct_v2_1_0.pao
Log:
DCT FSL Accelerator Template
Revision Changes Path
1.1 mb-jpeg/pcores/fsl_dct_v1_00_a/data/fsl_dct_v2_1_0.mpd
http://www.opencores.org/cvsweb.shtml/mb-jpeg/pcores/fsl_dct_v1_00_a/data/fsl_dct_v2_1_0.mpd?rev=1.1&content-type=text/x-cvsweb-markup
Index: fsl_dct_v2_1_0.mpd
===================================================================
##############################################################################
## Filename: D:\mb-jpeg\pcores/fsl_dct_v1_00_a/data/fsl_dct_v2_1_0.mpd
## Description: Microprocessor Peripheral Description
## Date: Fri Jul 21 08:31:12 2006 (by Create and Import Peripheral Wizard)
##############################################################################
BEGIN fsl_dct
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION CORE_STATE = DEVELOPMENT
OPTION HDL = VHDL
## Bus Interfaces
BUS_INTERFACE BUS=SFSL, BUS_STD=FSL, BUS_TYPE=SLAVE
BUS_INTERFACE BUS=MFSL, BUS_STD=FSL, BUS_TYPE=MASTER
## Peripheral ports
PORT FSL_Clk = "", DIR=I, SIGIS=Clk, BUS=MFSL:SFSL
PORT FSL_Rst = OPB_Rst, DIR=I, BUS=MFSL:SFSL
PORT FSL_S_Clk = FSL_S_Clk, DIR=O, SIGIS=Clk, BUS=SFSL
PORT FSL_S_Read = FSL_S_Read, DIR=O, BUS=SFSL
PORT FSL_S_Data = FSL_S_Data, DIR=I, VEC=[0:31], BUS=SFSL
PORT FSL_S_Control = FSL_S_Control, DIR=I, BUS=SFSL
PORT FSL_S_Exists = FSL_S_Exists, DIR=I, BUS=SFSL
PORT FSL_M_Clk = FSL_M_Clk, DIR=O, SIGIS=Clk, BUS=MFSL
PORT FSL_M_Write = FSL_M_Write, DIR=O, BUS=MFSL
PORT FSL_M_Data = FSL_M_Data, DIR=O, VEC=[0:31], BUS=MFSL
PORT FSL_M_Control = FSL_M_Control, DIR=O, BUS=MFSL
PORT FSL_M_Full = FSL_M_Full, DIR=I, BUS=MFSL
END
1.1 mb-jpeg/pcores/fsl_dct_v1_00_a/data/fsl_dct_v2_1_0.pao
http://www.opencores.org/cvsweb.shtml/mb-jpeg/pcores/fsl_dct_v1_00_a/data/fsl_dct_v2_1_0.pao?rev=1.1&content-type=text/x-cvsweb-markup
Index: fsl_dct_v2_1_0.pao
===================================================================
##############################################################################
## Filename: D:\mb-jpeg\pcores/fsl_dct_v1_00_a/data/fsl_dct_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Fri Jul 21 08:31:12 2006 (by Create and Import Peripheral Wizard)
##############################################################################
lib fsl_dct_v1_00_a fsl_dct vhdl
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