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Message
From: cvs at opencores.org<cvs@o...>
Date: Sun Jun 25 06:58:56 CEST 2006
Subject: [cvs-checkins] MODIFIED: ethernet_tri_mode ...
Date: 00/06/06 25:06:58 Modified: ethernet_tri_mode/rtl/verilog/MAC_rx MAC_rx_FF.v
MAC_rx_ctrl.v
Log:
no message
Revision Changes Path
1.5 ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_FF.v
http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_FF.v.diff?r1=1.4&r2=1.5
(In the diff below, changes in quantity of whitespace are not shown.)
Index: MAC_rx_FF.v
===================================================================
RCS file: /cvsroot/maverickist/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_FF.v,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- MAC_rx_FF.v 28 May 2006 05:09:20 -0000 1.4
+++ MAC_rx_FF.v 25 Jun 2006 04:58:56 -0000 1.5
@@ -39,6 +39,9 @@
// CVS Revision History
//
// $Log: MAC_rx_FF.v,v $
+// Revision 1.5 2006/06/25 04:58:56 maverickist
+// no message
+//
// Revision 1.4 2006/05/28 05:09:20 maverickist
// no message
//
@@ -139,7 +142,11 @@
reg Wr_en_tmp;
reg Wr_en_ptr;
wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse;
+wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse4;
+wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse3;
+wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse2;
reg Full;
+reg Almost_full;
reg Empty /* synthesis syn_keep=1 */;
reg [3:0] Current_state /* synthesis syn_keep=1 */;
reg [3:0] Next_state;
@@ -172,7 +179,10 @@
reg [35:0] Dout_dl1;
reg [4:0] Fifo_data_count;
reg Rx_mac_pa_tmp ;
-
+reg Add_wr_jump_tmp ;
+reg Add_wr_jump_tmp_pl1 ;
+reg Add_wr_jump ;
+reg Add_wr_jump_rd_pl1 ;
reg [4:0] Rx_Hwmark_pl ;
reg [4:0] Rx_Lwmark_pl ;
integer i ;
@@ -280,6 +290,11 @@
Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
end
assign Add_wr_pluse=Add_wr+1;
+assign Add_wr_pluse4=Add_wr+4;
+assign Add_wr_pluse3=Add_wr+3;
+assign Add_wr_pluse2=Add_wr+2;
+
+
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
@@ -289,7 +304,19 @@
else
Full <=0;
-assign Fifo_full =Full;
+always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Almost_full <=0;
+ else if (Add_wr_pluse4==Add_rd_ungray||
+ Add_wr_pluse3==Add_rd_ungray||
+ Add_wr_pluse2==Add_rd_ungray||
+ Add_wr_pluse==Add_rd_ungray
+ )
+ Almost_full <=1;
+ else
+ Almost_full <=0;
+
+assign Fifo_full =Almost_full;
//
always @ (posedge Clk_MAC or posedge Reset)
@@ -300,6 +327,28 @@
else if (Wr_en&&!Full)
Add_wr <=Add_wr +1;
+always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_wr_jump_tmp <=0;
+ else if (Current_state==State_err_end)
+ Add_wr_jump_tmp <=1;
+ else
+ Add_wr_jump_tmp <=0;
+
+always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_wr_jump_tmp_pl1 <=0;
+ else
+ Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
+
+always @ (posedge Clk_MAC or posedge Reset)
+ if (Reset)
+ Add_wr_jump <=0;
+ else if (Current_state==State_err_end)
+ Add_wr_jump <=1;
+ else if (Add_wr_jump_tmp_pl1)
+ Add_wr_jump <=0;
+
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
@@ -455,8 +504,10 @@
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
case (Current_state_SYS)
SYS_idle:
- if (Rx_mac_rd&&Rx_mac_ra)
+ if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
Next_state_SYS =SYS_read;
+ else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
+ Next_state_SYS =FF_emtpy_err;
else
Next_state_SYS =Current_state_SYS;
SYS_read:
@@ -513,7 +564,7 @@
Packet_number_inFF <=0;
else if (Packet_number_add_edge&&!Packet_number_sub)
Packet_number_inFF <=Packet_number_inFF + 1;
- else if (!Packet_number_add_edge&&Packet_number_sub)
+ else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
Packet_number_inFF <=Packet_number_inFF - 1;
always @ (posedge Clk_SYS or posedge Reset)
@@ -570,8 +621,14 @@
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
- Add_wr_ungray =0;
+ Add_wr_jump_rd_pl1 <=0;
else
+ Add_wr_jump_rd_pl1 <=Add_wr_jump;
+
+always @ (posedge Clk_SYS or posedge Reset)
+ if (Reset)
+ Add_wr_ungray =0;
+ else if (!Add_wr_jump_rd_pl1)
begin
Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
1.4 ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_ctrl.v
http://www.opencores.org/cvsweb.shtml/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_ctrl.v.diff?r1=1.3&r2=1.4
(In the diff below, changes in quantity of whitespace are not shown.)
Index: MAC_rx_ctrl.v
===================================================================
RCS file: /cvsroot/maverickist/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_ctrl.v,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- MAC_rx_ctrl.v 19 Jan 2006 14:07:54 -0000 1.3
+++ MAC_rx_ctrl.v 25 Jun 2006 04:58:56 -0000 1.4
@@ -39,6 +39,9 @@
// CVS Revision History
//
// $Log: MAC_rx_ctrl.v,v $
+// Revision 1.4 2006/06/25 04:58:56 maverickist
+// no message
+//
// Revision 1.3 2006/01/19 14:07:54 maverickist
// verification is complete.
//
@@ -165,6 +168,8 @@
reg CRC_en;
reg CRC_init;
reg Rx_apply_rmon;
+reg Rx_apply_rmon_tmp;
+reg Rx_apply_rmon_tmp_pl1;
reg [2:0] Rx_pkt_err_type_rmon;
reg MAC_add_en;
reg [2:0] Rx_pkt_type_rmon;
@@ -269,7 +274,7 @@
State_FFFullErrEnd:
Next_state =State_FFFullDrop;
State_IFG:
- if (IFG_counter==RX_IFG_SET)
+ if (IFG_counter==RX_IFG_SET-4) //remove some additional time
Next_state =State_idle;
else
Next_state =Current_state;
@@ -336,7 +341,7 @@
else if (Current_state==State_SFD)
Frame_length_counter <=1;
else if (Current_state==State_data)
- Frame_length_counter <=Frame_length_counter+ 1;
+ Frame_length_counter <=Frame_length_counter+ 1'b1;
always @ (Frame_length_counter or RX_MIN_LENGTH)
if (Frame_length_counter<RX_MIN_LENGTH)
@@ -350,7 +355,22 @@
else
Too_long =0;
-assign Rx_pkt_length_rmon=Frame_length_counter;
+assign Rx_pkt_length_rmon=Frame_length_counter-1'b1;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Rx_apply_rmon_tmp <=0;
+ else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
+ ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
+ Rx_apply_rmon_tmp <=1;
+ else
+ Rx_apply_rmon_tmp <=0;
+
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Rx_apply_rmon_tmp_pl1 <=0;
+ else
+ Rx_apply_rmon_tmp_pl1 <=Rx_apply_rmon_tmp;
always @ (posedge Clk or posedge Reset)
if (Reset)
@@ -358,7 +378,7 @@
else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
Rx_apply_rmon <=1;
- else
+ else if (Rx_apply_rmon_tmp_pl1)
Rx_apply_rmon <=0;
always @ (posedge Clk or posedge Reset)
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