|
Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Jun 23 21:03:43 CEST 2006
Subject: [cvs-checkins] MODIFIED: mb-jpeg ...
Date: 00/06/06 23:21:03 Added: mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src Makefile
config.make hw_exception_handler.S inbyte.c
mb_interface.h microblaze_disable_dcache.s
microblaze_disable_exceptions.s
microblaze_disable_icache.s
microblaze_disable_interrupts.s
microblaze_enable_dcache.s
microblaze_enable_exceptions.s
microblaze_enable_icache.s
microblaze_enable_interrupts.s
microblaze_exception_handler.c
microblaze_exceptions_g.c microblaze_exceptions_g.h
microblaze_exceptions_i.h
microblaze_init_dcache_range.s
microblaze_init_icache_range.s
microblaze_interrupt_handler.c
microblaze_interrupts_g.c microblaze_interrupts_i.h
microblaze_update_dcache.s
microblaze_update_icache.s outbyte.c
Log:
Updated to EDK8.1
Revision Changes Path
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/Makefile
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/Makefile?rev=1.1&content-type=text/x-cvsweb-markup
Index: Makefile
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
######################################################################
# The following are defined in config.make
# LIBSOURCES - Based on if MicroBlaze support Exceptions
# LIBS - Do Build Profile Libraries
include config.make
AS=mb-as
COMPILER=mb-gcc
ARCHIVER=mb-ar
CP=cp
COMPILER_FLAGS=-O2 -c
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
OUTS = *.o
INCLUDEFILES=*.h
libs: $(LIBS)
standalone_libs:
for i in $(LIBSOURCES); do \
echo "Compiling " $$i ;\
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $$i; \
done
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
profile_libs:
(cd profile; $(MAKE) COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(COMPILER)" ARCHIVER="$(ARCHIVER)" libs)
include: standalone_includes profile_includes
standalone_includes:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
profile_includes:
(cd profile; $(MAKE) COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(COMPILER)" ARCHIVER="$(ARCHIVER)" include)
clean:
rm -rf ${OUTS}
(cd profile; $(MAKE) COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(COMPILER)" ARCHIVER="$(ARCHIVER)" clean)
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/config.make
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/config.make?rev=1.1&content-type=text/x-cvsweb-markup
Index: config.make
===================================================================
LIBSOURCES = *.s *.c *.S
PROFILE_ARCH_OBJS = profile_mcount_mb.o
LIBS = standalone_libs
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/hw_exception_handler.S
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/hw_exception_handler.S?rev=1.1&content-type=text/x-cvsweb-markup
Index: hw_exception_handler.S
===================================================================
/*///////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: hw_exception_handler.S,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
//
//////////////////////////////////////////////////////////////////////////////*/
/*
* Microblaze HW Exception Handler
* - Non self-modifying exception handler for the following exception conditions
* - Unalignment
* - Instruction bus error
* - Data bus error
* - Illegal instruction opcode
* - Divide-by-zero
*/
#include "microblaze_exceptions_g.h"
/* Helpful Macros */
#define EX_HANDLER_STACK_SIZ (4*19)
#define RMSR_OFFSET 0
#define REG_OFFSET(regnum) (4*regnum)
#define NUM_TO_REG(num) r ## num
#define R3_TO_STACK(regnum) swi r3, r1, REG_OFFSET(regnum)
#define R3_FROM_STACK(regnum) lwi r3, r1, REG_OFFSET(regnum)
#define PUSH_REG(regnum) swi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
#define POP_REG(regnum) lwi NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
/* Uses r5 */
#define PUSH_MSR \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET;
#define PUSH_MSR_AND_ENABLE_EXC \
mfs r5, rmsr; \
swi r5, r1, RMSR_OFFSET; \
ori r5, r5, 0x100; /* Turn ON the EE bit*/ \
mts rmsr, r5;
/* Uses r5 */
#define POP_MSR \
lwi r5, r1, RMSR_OFFSET; \
mts rmsr, r5;
#define LWREG_NOP \
bri ex_handler_unhandled; \
nop;
#define SWREG_NOP \
bri ex_handler_unhandled; \
nop;
/* r3 is the source */
#define R3_TO_LWREG_V(regnum) \
R3_TO_STACK (regnum); \
bri ex_handler_done;
/* r3 is the source */
#define R3_TO_LWREG(regnum) \
or NUM_TO_REG (regnum), r0, r3; \
bri ex_handler_done;
/* r3 is the target */
#define SWREG_TO_R3_V(regnum) \
R3_FROM_STACK (regnum); \
bri ex_sw_tail;
/* r3 is the target */
#define SWREG_TO_R3(regnum) \
or r3, r0, NUM_TO_REG (regnum); \
bri ex_sw_tail;
/* Extern declarations */
.extern MB_ExceptionVectorTable
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
/*
* hw_exception_handler - Handler for unaligned exceptions
* Exception handler notes:
* - Does not handle exceptions other than unaligned exceptions
* - Does not handle exceptions during load into r17, r1, r0.
* - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case)
*
* Relevant register structures
*
* EAR - |----|----|----|----|----|----|----|----|
* - < ## 32 bit faulting address ## >
*
* ESR - |----|----|----|----|----| - | - |-----|-----|
* - W S REG EXC
*
*
* STACK FRAME STRUCTURE
* ---------------------
*
* +-------------+ + 0
* | MSR |
* +-------------+ + 4
* | r1 |
* | . |
* | . |
* | . |
* | . |
* | r18 |
* +-------------+ + 76
* | . |
* | . |
*/
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
_hw_exception_handler:
addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
PUSH_REG(3);
PUSH_REG(4);
PUSH_REG(5);
PUSH_REG(6);
PUSH_REG(17);
PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */
mfs r3, resr;
andi r5, r3, 0x1F; /* Extract ESR[EXC] */
#if (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER))
xori r6, r5, 1; /* 00001 = Unaligned Exception */
beqi r6, handle_unaligned_ex ; /* Jump to unalignment exception handler*/
#endif /* (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER)) */
#if (! defined (NO_OTHER_EXCEPTIONS) || (defined(USER_SPEC_UNALIGNED_HANDLER)))
handle_other_ex: /* Handle Other exceptions here */
ori r6, r0, 7;
cmp r6, r5, r6; /* >= 7 are unknown exceptions. Do not handle these */
blei r6, ex_handler_done;
PUSH_REG(7); /* Save other volatiles before we make procedure calls below */
PUSH_REG(8);
PUSH_REG(9);
PUSH_REG(10);
PUSH_REG(11);
PUSH_REG(12);
PUSH_REG(15);
PUSH_REG(18);
la r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */
addik r5, r5, -1 /* Interesting exception numbers start range from 1-6.
Convert to array index. */
addk r7, r5, r5; /* Calculate exception vector offset = r5 * 8 */
addk r7, r7, r7;
addk r7, r7, r7;
addk r7, r7, r4; /* Get pointer to exception vector */
lwi r5, r7, 4; /* Load argument to exception handler from table */
lw r7, r7, r0; /* Load vector itself here */
brald r15, r7; /* Branch to handler */
nop;
POP_REG(7); /* Restore other volatiles */
POP_REG(8);
POP_REG(9);
POP_REG(10);
POP_REG(11);
POP_REG(12);
POP_REG(15);
POP_REG(18);
#endif /* (! defined (NO_OTHER_EXCEPTIONS) || (defined(USER_SPEC_UNALIGNED_HANDLER))) */
#if (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER))
bri ex_handler_done; /* Complete exception handling */
handle_unaligned_ex:
andi r6, r3, 0x3E0; /* Mask and extract the register operand */
srl r6, r6; /* r6 >> 5 */
srl r6, r6;
srl r6, r6;
srl r6, r6;
srl r6, r6;
sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */
mfs r4, rear;
andi r6, r3, 0x400; /* Extract ESR[S] */
bnei r6, ex_sw;
ex_lw:
andi r6, r3, 0x800; /* Extract ESR[W] */
beqi r6, ex_lhw;
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lbui r5, r4, 2;
sbi r5, r0, ex_tmp_data_loc_2;
lbui r5, r4, 3;
sbi r5, r0, ex_tmp_data_loc_3;
lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
bri ex_lw_tail;
ex_lhw:
lbui r5, r4, 0; /* Exception address in r4 */
sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
lbui r5, r4, 1;
sbi r5, r0, ex_tmp_data_loc_1;
lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
ex_lw_tail:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
la r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r5;
addk r5, r5, r6;
bra r5;
ex_lw_end: /* Exception handling of load word, ends */
ex_sw:
lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
la r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r5;
add r5, r5, r6;
bra r5;
ex_sw_tail:
mfs r6, resr;
andi r6, r6, 0x800; /* Extract ESR[W] */
beqi r6, ex_shw;
swi r3, r0, ex_tmp_data_loc_0;
lbui r3, r0, ex_tmp_data_loc_0; /* Store the word, byte-by-byte into destination address */
sbi r3, r4, 0;
lbui r3, r0, ex_tmp_data_loc_1;
sbi r3, r4, 1;
lbui r3, r0, ex_tmp_data_loc_2;
sbi r3, r4, 2;
lbui r3, r0, ex_tmp_data_loc_3;
sbi r3, r4, 3;
bri ex_handler_done;
ex_shw:
swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */
lbui r3, r0, ex_tmp_data_loc_2;
sbi r3, r4, 0;
lbui r3, r0, ex_tmp_data_loc_3;
sbi r3, r4, 1;
ex_sw_end: /* Exception handling of store word, ends. */
#endif /* (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER)) */
ex_handler_done:
POP_MSR;
POP_REG(3);
POP_REG(4);
POP_REG(5);
POP_REG(6);
POP_REG(17);
rted r17, 0
addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
ex_handler_unhandled:
bri 0 /* UNHANDLED. TRAP HERE */
.end _hw_exception_handler
#if (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER))
/*
* hw_exception_handler Jump Table
* - Contains code snippets for each register that caused the unaligned exception.
* - Hence exception handler is NOT self-modifying
* - Separate table for load exceptions and store exceptions.
* - Each table is of size: (8 * 32) = 256 bytes
*/
.section .text
.align 4
lw_table:
lw_r0: R3_TO_LWREG (0);
lw_r1: LWREG_NOP;
lw_r2: R3_TO_LWREG (2);
lw_r3: R3_TO_LWREG_V (3);
lw_r4: R3_TO_LWREG_V (4);
lw_r5: R3_TO_LWREG_V (5);
lw_r6: R3_TO_LWREG_V (6);
lw_r7: R3_TO_LWREG (7);
lw_r8: R3_TO_LWREG (8);
lw_r9: R3_TO_LWREG (9);
lw_r10: R3_TO_LWREG (10);
lw_r11: R3_TO_LWREG (11);
lw_r12: R3_TO_LWREG (12);
lw_r13: R3_TO_LWREG (13);
lw_r14: R3_TO_LWREG (14);
lw_r15: R3_TO_LWREG (15);
lw_r16: R3_TO_LWREG (16);
lw_r17: LWREG_NOP;
lw_r18: R3_TO_LWREG (18);
lw_r19: R3_TO_LWREG (19);
lw_r20: R3_TO_LWREG (20);
lw_r21: R3_TO_LWREG (21);
lw_r22: R3_TO_LWREG (22);
lw_r23: R3_TO_LWREG (23);
lw_r24: R3_TO_LWREG (24);
lw_r25: R3_TO_LWREG (25);
lw_r26: R3_TO_LWREG (26);
lw_r27: R3_TO_LWREG (27);
lw_r28: R3_TO_LWREG (28);
lw_r29: R3_TO_LWREG (29);
lw_r30: R3_TO_LWREG (30);
lw_r31: R3_TO_LWREG (31);
sw_table:
sw_r0: SWREG_TO_R3 (0);
sw_r1: SWREG_NOP;
sw_r2: SWREG_TO_R3 (2);
sw_r3: SWREG_TO_R3_V (3);
sw_r4: SWREG_TO_R3_V (4);
sw_r5: SWREG_TO_R3_V (5);
sw_r6: SWREG_TO_R3_V (6);
sw_r7: SWREG_TO_R3 (7);
sw_r8: SWREG_TO_R3 (8);
sw_r9: SWREG_TO_R3 (9);
sw_r10: SWREG_TO_R3 (10);
sw_r11: SWREG_TO_R3 (11);
sw_r12: SWREG_TO_R3 (12);
sw_r13: SWREG_TO_R3 (13);
sw_r14: SWREG_TO_R3 (14);
sw_r15: SWREG_TO_R3 (15);
sw_r16: SWREG_TO_R3 (16);
sw_r17: SWREG_NOP;
sw_r18: SWREG_TO_R3 (18);
sw_r19: SWREG_TO_R3 (19);
sw_r20: SWREG_TO_R3 (20);
sw_r21: SWREG_TO_R3 (21);
sw_r22: SWREG_TO_R3 (22);
sw_r23: SWREG_TO_R3 (23);
sw_r24: SWREG_TO_R3 (24);
sw_r25: SWREG_TO_R3 (25);
sw_r26: SWREG_TO_R3 (26);
sw_r27: SWREG_TO_R3 (27);
sw_r28: SWREG_TO_R3 (28);
sw_r29: SWREG_TO_R3 (29);
sw_r30: SWREG_TO_R3 (30);
sw_r31: SWREG_TO_R3 (31);
/* Temporary data structures used in the handler */
.section .data
.align 2
ex_tmp_data_loc_0:
.byte 0
ex_tmp_data_loc_1:
.byte 0
ex_tmp_data_loc_2:
.byte 0
ex_tmp_data_loc_3:
.byte 0
ex_reg_op:
.byte 0
#endif /* (! defined (NO_UNALIGNED_EXCEPTIONS) && ! defined (USER_SPEC_UNALIGNED_HANDLER)) */
#else /* Dummy exception handler, in case exceptions are not present in the processor */
.global _hw_exception_handler
.section .text
.align 2
.ent _hw_exception_handler
_hw_exception_handler:
bri 0;
.end _hw_exception_handler
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/inbyte.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/inbyte.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: inbyte.c
===================================================================
#include "xparameters.h"
#include "xuartlite_l.h"
char inbyte(void) {
return XUartLite_RecvByte(STDIN_BASEADDRESS);
}
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/mb_interface.h
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/mb_interface.h?rev=1.1&content-type=text/x-cvsweb-markup
Index: mb_interface.h
===================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// File : mb_interface.h
// Date : 2002, March 20.
// Company: Xilinx
// Group : Emerging Software Technologies
//
// Summary:
// Header file for mb_interface
//
// $Id: mb_interface.h,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _MICROBLAZE_INTERFACE_H_
#define _MICROBLAZE_INTERFACE_H_
#include "xbasic_types.h"
extern void microblaze_enable_interrupts(void); // Enable Interrupts
extern void microblaze_disable_interrupts(void); // Disable Interrupts
extern void microblaze_enable_icache(void); // Enable Instruction Cache
extern void microblaze_disable_icache(void); // Disable Instruction Cache
extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); // Register top level interrupt handler
extern void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr); // Register exception handler
extern void microblaze_update_icache (int , int , int );
extern void microblaze_init_icache_range (int , int );
extern void microblaze_update_dcache (int , int , int );
extern void microblaze_init_dcache_range (int , int );
// FSL Access Macros
// Blocking Data Read and Write to FSL no. id
#define microblaze_bread_datafsl(val, id) asm volatile ("get %0, rfsl" #id : "=d" (val))
#define microblaze_bwrite_datafsl(val, id) asm volatile ("put %0, rfsl" #id :: "d" (val))
// Non-blocking Data Read and Write to FSL no. id
#define microblaze_nbread_datafsl(val, id) asm volatile ("nget %0, rfsl" #id : "=d" (val))
#define microblaze_nbwrite_datafsl(val, id) asm volatile ("nput %0, rfsl" #id :: "d" (val))
// Blocking Control Read and Write to FSL no. id
#define microblaze_bread_cntlfsl(val, id) asm volatile ("cget %0, rfsl" #id : "=d" (val))
#define microblaze_bwrite_cntlfsl(val, id) asm volatile ("cput %0, rfsl" #id :: "d" (val))
// Non-blocking Control Read and Write to FSL no. id
#define microblaze_nbread_cntlfsl(val, id) asm volatile ("ncget %0, rfsl" #id : "=d" (val))
#define microblaze_nbwrite_cntlfsl(val, id) asm volatile ("ncput %0, rfsl" #id :: "d" (val))
#endif // _MICROBLAZE_INTERFACE_H_
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_disable_dcache.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_disable_dcache.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_disable_dcache.s
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_disable_dcache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable dcache on the microblaze.
#
# $Id: microblaze_disable_dcache.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_disable_dcache
.ent microblaze_disable_dcache
.align 2
microblaze_disable_dcache:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Clear the dcache enable bit
andi r12, r12, ~128
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_disable_dcache
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_disable_exceptions.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_disable_exceptions.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_disable_exceptions.s
===================================================================
##############################################################-*-asm-*-
#
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# Disable exceptions on microblaze.
#
# $Id: microblaze_disable_exceptions.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.section .text
.globl microblaze_disable_exceptions
.ent microblaze_disable_exceptions
.align 2
microblaze_disable_exceptions:
mfs r4, rmsr;
andi r4, r4, ~(0x100); /* Turn OFF the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
.end microblaze_disable_exceptions
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_disable_icache.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_disable_icache.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_disable_icache.s
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_disable_icache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable icache on the microblaze.
#
# $Id: microblaze_disable_icache.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_disable_icache
.ent microblaze_disable_icache
.align 2
microblaze_disable_icache:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Clear the icache enable bit
andi r12, r12, ~32
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_disable_icache
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_disable_interrupts.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_disable_interrupts.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_disable_interrupts.s
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_disable_interrupts.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Disable interrupts on the microblaze.
#
# $Id: microblaze_disable_interrupts.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_disable_interrupts
.ent microblaze_disable_interrupts
.align 2
microblaze_disable_interrupts:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Clear the interrupt enable bit
andi r12, r12, ~2
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_disable_interrupts
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_enable_dcache.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_enable_dcache.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_enable_dcache.s
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_enable_dcache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable dcache on the microblaze.
#
# $Id: microblaze_enable_dcache.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_enable_dcache
.ent microblaze_enable_dcache
.align 2
microblaze_enable_dcache:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Set the interrupt enable bit
ori r12, r12, 128
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_enable_dcache
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_enable_exceptions.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_enable_exceptions.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_enable_exceptions.s
===================================================================
##############################################################-*-asm-*-
#
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# Enable exceptions on microblaze.
#
# $Id: microblaze_enable_exceptions.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.section .text
.globl microblaze_enable_exceptions
.ent microblaze_enable_exceptions
.align 2
microblaze_enable_exceptions:
mfs r4, rmsr;
ori r4, r4, 0x100; /* Turn ON the EE bit */
mts rmsr, r4;
rtsd r15, 8;
nop;
.end microblaze_enable_exceptions
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_enable_icache.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_enable_icache.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_enable_icache.s
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_enable_icache.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable icache on the microblaze.
#
# $Id: microblaze_enable_icache.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_enable_icache
.ent microblaze_enable_icache
.align 2
microblaze_enable_icache:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Set the interrupt enable bit
ori r12, r12, 32
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_enable_icache
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_enable_interrupts.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_enable_interrupts.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_enable_interrupts.s
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_enable_interrupts.s
# Date : 2002, March 20.
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Enable interrupts on the microblaze.
#
# $Id: microblaze_enable_interrupts.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_enable_interrupts
.ent microblaze_enable_interrupts
.align 2
microblaze_enable_interrupts:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Set the interrupt enable bit
ori r12, r12, 2
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_enable_interrupts
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_exception_handler.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_exception_handler.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_exception_handler.c
===================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_exception_handler.c,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file microblaze_exception_handler.c
*
* This file contains exception handler registration routines for
* the MicroBlaze processor.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 06/24/04 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "microblaze_exceptions_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[];
/****************************************************************************/
/*****************************************************************************/
/**
*
* Registers an exception handler for the MicroBlaze. The
* argument provided in this call as the DataPtr is used as the argument
* for the handler when it is called.
*
* @param ExceptionId is the id of the exception to register this handler
* for.
* @param Top level handler.
* @param DataPtr is a reference to data that will be passed to the handler
* when it gets called.
* @return None.
*
* @note
*
* None.
*
****************************************************************************/
void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr)
{
MB_ExceptionVectorTable[ExceptionId - 1].Handler = Handler;
MB_ExceptionVectorTable[ExceptionId - 1].CallBackRef = DataPtr;
}
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_exceptions_g.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_exceptions_g.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_exceptions_g.c
===================================================================
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Exception Handler Table for MicroBlaze Processor
*
*******************************************************************/
#include "microblaze_exceptions_i.h"
#include "xparameters.h"
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_exceptions_g.h
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_exceptions_g.h?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_exceptions_g.h
===================================================================
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Exception Handling Header for MicroBlaze Processor
*
*******************************************************************/
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_exceptions_i.h
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_exceptions_i.h?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_exceptions_i.h
===================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_exceptions_i.h,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file microblaze_exceptions_i.h
*
* This header file contains defines for structures used by the microblaze
* hardware exception handler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00a 06/24/04 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */
#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xbasic_types.h"
typedef struct
{
XExceptionHandler Handler;
void *CallBackRef;
} MB_ExceptionVectorTableEntry;
/* Exception IDs */
#define XEXC_ID_UNALIGNED_ACCESS 1
#define XEXC_ID_ILLEGAL_OPCODE 2
#define XEXC_ID_IOPB_EXCEPTION 3
#define XEXC_ID_DOPB_EXCEPTION 4
#define XEXC_ID_DIV_BY_ZERO 5
#define XEXC_ID_FPU 6
void microblaze_register_exception_handler(Xuint8 ExceptionId, XExceptionHandler Handler, void *DataPtr);
#endif /* end of protection macro */
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_init_dcache_range.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_init_dcache_range.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_init_dcache_range.s
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_init_dcache_range.s
# Date : 2003, September 24
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Update dcache on the microblaze.
# Takes in two parameters
# r5 : Cache Base Address
# (start address in the cache where invalidation begins)
# r6 : Size of Cache to be invalidated
#
# $Id: microblaze_init_dcache_range.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_init_dcache_range
.ent microblaze_init_dcache_range
.align 2
microblaze_init_dcache_range:
# Read the MSR register into a temp register
mfs r9, rmsr
# Clear the dcache enable bit to disable the cache
# Register r10,r18 are volatile registers and hence do not need to be saved before use
andi r10, r9, ~128
mts rmsr, r10
## Start the loop
add r6,r5,r6 # One address beyond last address
L_start:
cmp r18,r5,r6
bleid r18, L_done # Jump out of the loop if done
addi r6,r6,-4 # Decrement the addrees by 4 [ delay slot]
brid L_start # Branch to the beginning of the loop
wdc r6,r0 # Invalidate the Cache [ delay slot]
L_done:
# Return
rtsd r15, 8
# Restore the MSR back
mts rmsr,r9
.end microblaze_init_dcache_range
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_init_icache_range.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_init_icache_range.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_init_icache_range.s
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_init_icache_range.s
# Date : 2003, September 24
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Update icache on the microblaze.
# Takes in two parameters
# r5 : Cache Base Address
# (start address in the cache where invalidation begins)
# r6 : Size of Cache to be invalidated
#
# $Id: microblaze_init_icache_range.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_init_icache_range
.ent microblaze_init_icache_range
.align 2
microblaze_init_icache_range:
# Read the MSR register into a temp register
mfs r9, rmsr
# Clear the icache enable bit to disable the cache
# Register r10,r18 are volatile registers and hence do not need to be saved before use
andi r10, r9, ~32
mts rmsr, r10
## Start the loop
add r6,r5,r6 # One address beyond last address
L_start:
cmp r18,r5,r6
bleid r18, L_done # Jump out of the loop if done
addi r6,r6,-4 # Decrement the addrees by 4 [ delay slot]
brid L_start # Branch to the beginning of the loop
wic r6,r0 # Invalidate the Cache [ delay slot]
L_done:
# Return
rtsd r15, 8
# Restore the MSR back
mts rmsr,r9
.end microblaze_init_icache_range
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_interrupt_handler.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_interrupt_handler.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_interrupt_handler.c
===================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_interrupt_handler.c,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file microblaze_interrupt_handler.c
*
* This file contains the standard interrupt handler for the MicroBlaze processor.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "microblaze_interrupts_i.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void __interrupt_handler () __attribute__ ((interrupt_handler));
/************************** Variable Definitions *****************************/
extern MB_InterruptVectorTableEntry MB_InterruptVectorTable;
/*****************************************************************************/
/**
*
* This function is the standard interrupt handler used by the MicroBlaze processor.
* It saves all volatile registers, calls the users top level interrupt handler.
* When this returns, it restores all registers, and returns using a rtid instruction.
*
* @param
*
* None
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
void __interrupt_handler(void)
{
/* The compiler saves all volatiles and the MSR */
MB_InterruptVectorTable.Handler(MB_InterruptVectorTable.CallBackRef);
/* The compiler restores all volatiles and MSR, and returns from interrupt */
}
/****************************************************************************//*****************************************************************************/
/**
*
* Registers a top-level interrupt handler for the MicroBlaze. The
* argument provided in this call as the DataPtr is used as the argument
* for the handler when it is called.
*
* @param Top level handler.
* @param DataPtr is a reference to data that will be passed to the handler
* when it gets called.
* @return None.
*
* @note
*
* None.
*
****************************************************************************/
void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr)
{
MB_InterruptVectorTable.Handler = Handler;
MB_InterruptVectorTable.CallBackRef = DataPtr;
}
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_interrupts_g.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_interrupts_g.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_interrupts_g.c
===================================================================
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Interrupt Handler Table for MicroBlaze Processor
*
*******************************************************************/
#include "microblaze_interrupts_i.h"
#include "xparameters.h"
extern void XNullHandler (void *);
/*
* The interrupt handler table for microblaze processor
*/
MB_InterruptVectorTableEntry MB_InterruptVectorTable[] =
{
XNullHandler,
(void*) XNULL
};
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_interrupts_i.h
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_interrupts_i.h?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_interrupts_i.h
===================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
// $Id: microblaze_interrupts_i.h,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
////////////////////////////////////////////////////////////////////////////////
/*****************************************************************************/
/**
*
* @file microblaze_interrupts_i.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* High-level driver functions are defined in xintc.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Date Changes
* ----- -------- -----------------------------------------------
* 1.00b 10/03/03 First release
* </pre>
*
******************************************************************************/
#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xbasic_types.h"
typedef struct
{
XInterruptHandler Handler;
void *CallBackRef;
} MB_InterruptVectorTableEntry;
#endif /* end of protection macro */
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_update_dcache.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_update_dcache.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_update_dcache.s
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_update_dcache.s
# Date : 2003, September 24
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Update dcache on the microblaze.
# Takes in three parameters
# r5 : Cache Tag Line
# r6 : Cache Data
# r7 : Lock/Valid information
# Bit 30 is Lock [ 1 indicates locked ]
# Bit 31 is Valid [ 1 indicates valid ]
#
# --------------------------------------------------------------
# | Lock | Valid | Effect
# --------------------------------------------------------------
# | 0 | 0 | Invalidate Cache
# | 0 | 1 | Valid, but unlocked cacheline
# | 1 | 0 | Invalidate Cache, No effect of lock
# | 1 | 1 | Valid cache. Locked to a
# | | | particular addrees
# --------------------------------------------------------------
#
# $Id: microblaze_update_dcache.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_update_dcache
.ent microblaze_update_dcache
.align 2
microblaze_update_dcache:
#Read the MSR register into a temp register
mfs r18, rmsr
#Clear the dcache enable bit to disable the cache
# Register r10,r18 are volatile registers and hence do not need to be saved before use
andi r10, r18, ~128
mts rmsr, r10
# Update the lock and valid info
andi r5,r5,0xfffffffc
or r5,r5,r7
# Update dcache
wdc r5,r6
#Return
rtsd r15, 8
# Restore the MSR back
mts rmsr,r18
.end microblaze_update_dcache
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_update_icache.s
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/microblaze_update_icache.s?rev=1.1&content-type=text/x-cvsweb-markup
Index: microblaze_update_icache.s
===================================================================
######################################################################
# Copyright (c) 2004 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# File : microblaze_update_icache.s
# Date : 2003, September 24
# Company: Xilinx
# Group : Emerging Software Technologies
#
# Summary:
# Update icache on the microblaze.
# Takes in three parameters
# r5 : Cache Tag Line
# r6 : Cache Data
# r7 : Lock/Valid information
# Bit 30 is Lock [ 1 indicates locked ]
# Bit 31 is Valid [ 1 indicates valid ]
#
# --------------------------------------------------------------
# | Lock | Valid | Effect
# --------------------------------------------------------------
# | 0 | 0 | Invalidate Cache
# | 0 | 1 | Valid, but unlocked cacheline
# | 1 | 0 | Invalidate Cache, No effect of lock
# | 1 | 1 | Valid cache. Locked to a
# | | | particular addrees
# --------------------------------------------------------------
#
# $Id: microblaze_update_icache.s,v 1.1 2006/06/23 19:03:42 quickwayne Exp $
#
####################################################################
.text
.globl microblaze_update_icache
.ent microblaze_update_icache
.align 2
microblaze_update_icache:
# Read the MSR register into a temp register
mfs r18, rmsr
# Clear the icache enable bit to disable the cache
# Register r10,r18 are volatile registers and hence do not need to be saved before use
andi r10, r18, ~32
mts rmsr, r10
# Update the lock and valid info
andi r5,r5,0xfffffffc
or r5,r5,r7
# Update icache
wic r5,r6
# Return
rtsd r15, 8
# Restore the MSR back
mts rmsr,r18
.end microblaze_update_icache
1.1 mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/outbyte.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/standalone_v1_00_a/src/outbyte.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: outbyte.c
===================================================================
#include "xparameters.h"
#include "xuartlite_l.h"
void outbyte(char c) {
XUartLite_SendByte(STDOUT_BASEADDRESS, c);
}
|
 |
Browse
