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Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Jun 23 21:03:42 CEST 2006
Subject: [cvs-checkins] MODIFIED: mb-jpeg ...
Date: 00/06/06 23:21:03 Added: mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src Makefile
xgpio.c xgpio.h xgpio_extra.c xgpio_g.c xgpio_i.h
xgpio_intr.c xgpio_l.h xgpio_selftest.c
Log:
Updated to EDK8.1
Revision Changes Path
1.1 mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/Makefile
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/Makefile?rev=1.1&content-type=text/x-cvsweb-markup
Index: Makefile
===================================================================
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=xgpio_l.h xgpio.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling gpio"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
make clean
include:
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
clean:
rm -rf ${OUTS}
1.1 mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: xgpio.c
===================================================================
/* $Id: xgpio.c,v 1.1 2006/06/23 19:03:41 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/**
* @file xgpio.c
*
* The implementation of the XGpio component's basic functionality. See xgpio.h
* for more information about the component.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xparameters.h"
#include "xgpio.h"
#include "xgpio_i.h"
#include "xstatus.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Initialize the XGpio instance provided by the caller based on the
* given DeviceID.
*
* Nothing is done except to initialize the InstancePtr.
*
* @param InstancePtr is a pointer to an XGpio instance. The memory the pointer
* references must be pre-allocated by the caller. Further calls to
* manipulate the component through the XGpio API must be made with this
* pointer.
*
* @param DeviceId is the unique id of the device controlled by this XGpio
* component. Passing in a device id associates the generic XGpio
* instance to a specific device, as chosen by the caller or application
* developer.
*
* @return
*
* - XST_SUCCESS Initialization was successfull.
* - XST_DEVICE_NOT_FOUND Device configuration data was not found for a device
* with the supplied device ID.
*
* @note
*
* None.
*
*****************************************************************************/
XStatus XGpio_Initialize(XGpio *InstancePtr, Xuint16 DeviceId)
{
XGpio_Config *ConfigPtr;
/*
* Assert arguments
*/
XASSERT_NONVOID(InstancePtr != XNULL);
/*
* Lookup configuration data in the device configuration table.
* Use this configuration info down below when initializing this component.
*/
ConfigPtr = XGpio_LookupConfig(DeviceId);
if (ConfigPtr == (XGpio_Config *)XNULL)
{
InstancePtr->IsReady = 0;
return(XST_DEVICE_NOT_FOUND);
}
/*
* Set some default values.
*/
InstancePtr->BaseAddress = ConfigPtr->BaseAddress;
InstancePtr->ConfigPtr = ConfigPtr;
/*
* Indicate the instance is now ready to use, initialized without error
*/
InstancePtr->IsReady = XCOMPONENT_IS_READY;
return(XST_SUCCESS);
}
/******************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* ConfigTable contains the configuration info for each device in the system.
*
* @param DeviceId is the device identifier to lookup.
*
* @return
*
* - A pointer of data type XGpio_Config which points to the device
* configuration if DeviceID is found.
* - XNULL if DeviceID is not found.
*
* @note
*
* None.
*
******************************************************************************/
XGpio_Config *XGpio_LookupConfig(Xuint16 DeviceId)
{
XGpio_Config *CfgPtr = XNULL;
int i;
for (i=0; i < XPAR_XGPIO_NUM_INSTANCES; i++)
{
if (XGpio_ConfigTable[i].DeviceId == DeviceId)
{
CfgPtr = &XGpio_ConfigTable[i];
break;
}
}
return CfgPtr;
}
/****************************************************************************/
/**
* Set the input/output direction of all discrete signals for the specified
* GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param DirectionMask is a bitmask specifying which discretes are input and
* which are output. Bits set to 0 are output and bits set to 1 are input.
*
* @return
*
* None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
*****************************************************************************/
void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
Xuint32 DirectionMask)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->ConfigPtr->IsDual == XTRUE)));
XGpio_mWriteReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET,
DirectionMask);
}
/****************************************************************************/
/**
* Read state of discretes for the specified GPIO channnel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
*
* @return Current copy of the discretes register.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
*****************************************************************************/
Xuint32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_NONVOID((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->ConfigPtr->IsDual == XTRUE)));
return XGpio_mReadReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) +
XGPIO_DATA_OFFSET);
}
/****************************************************************************/
/**
* Write to discretes register for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Data is the value to be written to the discretes register.
*
* @return
*
* None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
* See also XGpio_DiscreteSet() and XGpio_DiscreteClear().
*
*****************************************************************************/
void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, Xuint32 Data)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->ConfigPtr->IsDual == XTRUE)));
XGpio_mWriteReg(InstancePtr->BaseAddress,
((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
Data);
}
1.1 mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio.h
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio.h?rev=1.1&content-type=text/x-cvsweb-markup
Index: xgpio.h
===================================================================
/* $Id: xgpio.h,v 1.1 2006/06/23 19:03:41 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio.h
*
* This file contains the software API definition of the Xilinx General Purpose
* I/O (XGpio) device driver component.
*
* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs on
* the OPB or PLB bus and contains the following general features:
* - Support for up to 32 I/O discretes for each channel (64 bits total).
* - Each of the discretes can be configured for input or output.
* - Configurable support for dual channels and interrupt generation.
*
* The driver provides interrupt management functions. Implementation of
* interrupt handlers is left to the user. Refer to the provided interrupt
* example in the examples directory for details.
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* @note
*
* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
* the unused bits from registers are read as zero and written as don't cares.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/13/02 First release
* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
* </pre>
*****************************************************************************/
#ifndef XGPIO_H /* prevent circular inclusions */
#define XGPIO_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xbasic_types.h"
#include "xstatus.h"
#include "xgpio_l.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct
{
Xuint16 DeviceId; /* Unique ID of device */
Xuint32 BaseAddress; /* Device base address */
Xboolean InterruptPresent; /* Are interrupts supported in h/w */
Xboolean IsDual; /* Are 2 channels supported in h/w */
} XGpio_Config;
/**
* The XGpio driver instance data. The user is required to allocate a
* variable of this type for every GPIO device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct
{
Xuint32 BaseAddress; /* Device base address */
Xuint32 IsReady; /* Device is initialized and ready */
XGpio_Config *ConfigPtr;/* Pointer to the configuration */
} XGpio;
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Function Prototypes *****************************/
/*
* API Basic functions implemented in xgpio.c
*/
XStatus XGpio_Initialize(XGpio *InstancePtr, Xuint16 DeviceId);
void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
Xuint32 DirectionMask);
Xuint32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask);
XGpio_Config *XGpio_LookupConfig(Xuint16 DeviceId);
/*
* API Functions implemented in xgpio_extra.c
*/
void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask);
void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask);
/*
* API Functions implemented in xgpio_selftest.c
*/
XStatus XGpio_SelfTest(XGpio *InstancePtr);
/*
* API Functions implemented in xgpio_intr.c
*/
void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
void XGpio_InterruptEnable(XGpio *InstancePtr, Xuint32 Mask);
void XGpio_InterruptDisable(XGpio *InstancePtr, Xuint32 Mask);
void XGpio_InterruptClear(XGpio *InstancePtr, Xuint32 Mask);
Xuint32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
Xuint32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
#endif /* end of protection macro */
1.1 mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_extra.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_extra.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: xgpio_extra.c
===================================================================
/* $Id: xgpio_extra.c,v 1.1 2006/06/23 19:03:41 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 -2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/**
* @file xgpio_extra.c
*
* The implementation of the XGpio component's advanced discrete functions.
* See xgpio.h for more information about the component.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
#include "xgpio_i.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Set output discrete(s) to logic 1 for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Mask is the set of bits that will be set to 1 in the discrete data
* register. All other bits in the data register are unaffected.
*
* @return
*
* None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
*****************************************************************************/
void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask)
{
Xuint32 Current;
unsigned DataOffset;
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->ConfigPtr->IsDual == XTRUE)));
/* Calculate the offset to the data register of the GPIO once */
DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
/*
* Read the contents of the data register, merge in Mask and write
* back results
*/
Current = XGpio_mReadReg(InstancePtr->BaseAddress, DataOffset);
Current |= Mask;
XGpio_mWriteReg(InstancePtr->BaseAddress, DataOffset, Current);
}
/****************************************************************************/
/**
* Set output discrete(s) to logic 0 for the specified GPIO channel.
*
* @param InstancePtr is a pointer to an XGpio instance to be worked on.
* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
* @param Mask is the set of bits that will be set to 0 in the discrete data
* register. All other bits in the data register are unaffected.
*
* @return
*
* None.
*
* @note
*
* The hardware must be built for dual channels if this function is used
* with any channel other than 1. If it is not, this function will assert.
*
*****************************************************************************/
void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask)
{
Xuint32 Current;
unsigned DataOffset;
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID((Channel == 1) ||
((Channel == 2) &&
(InstancePtr->ConfigPtr->IsDual == XTRUE)));
/* Calculate the offset to the data register of the GPIO once */
DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
/*
* Read the contents of the data register, merge in Mask and write
* back results
*/
Current = XGpio_mReadReg(InstancePtr->BaseAddress, DataOffset);
Current &= ~Mask;
XGpio_mWriteReg(InstancePtr->BaseAddress, DataOffset, Current);
}
1.1 mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_g.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_g.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: xgpio_g.c
===================================================================
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xgpio.h"
/*
* The configuration table for devices
*/
XGpio_Config XGpio_ConfigTable[] =
{
{
XPAR_LEDS_4BIT_DEVICE_ID,
XPAR_LEDS_4BIT_BASEADDR,
XPAR_LEDS_4BIT_INTERRUPT_PRESENT,
XPAR_LEDS_4BIT_IS_DUAL
},
{
XPAR_DIPSWS_4BIT_DEVICE_ID,
XPAR_DIPSWS_4BIT_BASEADDR,
XPAR_DIPSWS_4BIT_INTERRUPT_PRESENT,
XPAR_DIPSWS_4BIT_IS_DUAL
},
{
XPAR_PUSHBUTTONS_5BIT_DEVICE_ID,
XPAR_PUSHBUTTONS_5BIT_BASEADDR,
XPAR_PUSHBUTTONS_5BIT_INTERRUPT_PRESENT,
XPAR_PUSHBUTTONS_5BIT_IS_DUAL
}
};
1.1 mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_i.h
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_i.h?rev=1.1&content-type=text/x-cvsweb-markup
Index: xgpio_i.h
===================================================================
/* $Id: xgpio_i.h,v 1.1 2006/06/23 19:03:41 quickwayne Exp $: */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/******************************************************************************/
/**
* @file xgpio_i.h
*
* This header file contains internal identifiers, which are those shared
* between the files of the driver. It is intended for internal use only.
*
* NOTES:
*
* None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 03/13/02 First release
* </pre>
******************************************************************************/
#ifndef XGPIO_I_H /* prevent circular inclusions */
#define XGPIO_I_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xgpio.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions ****************************/
extern XGpio_Config XGpio_ConfigTable[];
#endif /* end of protection macro */
1.1 mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_intr.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_intr.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: xgpio_intr.c
===================================================================
/* $Id */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xgpio_intr.c
*
* Implements GPIO interrupt processing functions for the XGpio
* component. See xgpio.h for more information about the component.
*
* The functions in this file require the hardware device to be built with
* interrupt capabilities. The functions will assert if called using hardware
* that does not have interrupt capabilities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 2.00a jhl 11/26/03 Initial release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
#include "xipif_v1_23_b.h"
/************************** Constant Definitions ****************************/
/* The following constant describes the offset of the interrupt registers
* that are contained in the IPIF. This offset should be added to the base
* address of the device when using the IPIF access functions.
*/
#define XGPIO_IPIF_OFFSET 0x100
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
* Enable the interrupt output signal. Interrupts enabled through
* XGpio_InterruptEnable() will not be passed through until the global enable
* bit is set by this function. This function is designed to allow all
* interrupts (both channels) to be enabled easily for exiting a critical
* section. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XGpio_InterruptGlobalEnable(XGpio *InstancePtr)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET);
}
/****************************************************************************/
/**
* Disable the interrupt output signal. Interrupts enabled through
* XGpio_InterruptEnable() will no longer be passed through until the global
* enable bit is set by XGpio_InterruptGlobalEnable(). This function is
* designed to allow all interrupts (both channels) to be disabled easily for
* entering a critical section. This function will assert if the hardware
* device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XGpio_InterruptGlobalDisable(XGpio *InstancePtr)
{
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET);
}
/****************************************************************************/
/**
* Enable interrupts. The global interrupt must also be enabled by calling
* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
* assert if the hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
* @param Mask is the mask to enable. Bit positions of 1 are enabled. This mask
* is formed by OR'ing bits from XGPIO_IR* bits which are contained in
* xgpio_l.h.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XGpio_InterruptEnable(XGpio *InstancePtr, Xuint32 Mask)
{
Xuint32 Register;
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
/* Read the interrupt enable register and only enable the specified
* interrupts without disabling or enabling any others.
*/
Register = XIIF_V123B_READ_IIER(InstancePtr->BaseAddress +
XGPIO_IPIF_OFFSET);
XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET,
Mask | Register);
}
/****************************************************************************/
/**
* Disable interrupts. This function allows specific interrupts for each
* channel to be disabled. This function will assert if the hardware device
* has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
* @param Mask is the mask to disable. Bits set to 1 are disabled. This mask
* is formed by OR'ing bits from XGPIO_IR* bits which are contained in
* xgpio_l.h.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XGpio_InterruptDisable(XGpio *InstancePtr, Xuint32 Mask)
{
Xuint32 Register;
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
/* Read the interrupt enable register and only disable the specified
* interrupts without enabling or disabling any others.
*/
Register = XIIF_V123B_READ_IIER(InstancePtr->BaseAddress +
XGPIO_IPIF_OFFSET);
XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET,
Mask & ~Register);
}
/****************************************************************************/
/**
* Clear pending interrupts with the provided mask. This function should be
* called after the software has serviced the interrupts that are pending.
* This function will assert if the hardware device has not been built with
* interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
* @param Mask is the mask to clear pending interrupts for. Bit positions of 1
* are cleared. This mask is formed by OR'ing bits from
* XGPIO_IR* bits which are contained in xgpio_l.h.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
void XGpio_InterruptClear(XGpio *InstancePtr, Xuint32 Mask)
{
Xuint32 Register;
XASSERT_VOID(InstancePtr != XNULL);
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_VOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
/* Read the interrupt status register and only clear the interrupts
* that are specified without affecting any others. Since the register
* is a toggle on write, make sure any bits to be written are already
* set.
*/
Register = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress +
XGPIO_IPIF_OFFSET);
XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET,
Register & Mask);
}
/****************************************************************************/
/**
* Returns the interrupt enable mask. This function will assert if the
* hardware device has not been built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
*
* @return A mask of bits made from XGPIO_IR* bits which are contained in
* xgpio_l.h.
*
* @return
*
* None.
*
* @note
*
* None.
*
*****************************************************************************/
Xuint32 XGpio_InterruptGetEnabled(XGpio *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_NONVOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
return XIIF_V123B_READ_IIER(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET);
}
/****************************************************************************/
/**
* Returns the status of interrupt signals. Any bit in the mask set to 1
* indicates that the channel associated with the bit has asserted an interrupt
* condition. This function will assert if the hardware device has not been
* built with interrupt capabilities.
*
* @param InstancePtr is the GPIO component to operate on.
*
* @return A pointer to a mask of bits made from XGPIO_IR* bits which are
* contained in xgpio_l.h.
*
* @note
*
* The interrupt status indicates the status of the device irregardless if
* the interrupts from the devices have been enabled or not through
* XGpio_InterruptEnable().
*
*****************************************************************************/
Xuint32 XGpio_InterruptGetStatus(XGpio *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
XASSERT_NONVOID(InstancePtr->ConfigPtr->InterruptPresent == XTRUE);
return XIIF_V123B_READ_IISR(InstancePtr->BaseAddress + XGPIO_IPIF_OFFSET);
}
1.1 mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_l.h
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_l.h?rev=1.1&content-type=text/x-cvsweb-markup
Index: xgpio_l.h
===================================================================
/* $Id: xgpio_l.h,v 1.1 2006/06/23 19:03:41 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpio_l.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* High-level driver functions are defined in xgpio.h.
*
* The macros that are available in this file use a multiply to calculate the
* addresses of registers. The user can control whether that multiply is done
* at run time or at compile time. A constant passed as the channel parameter
* will cause the multiply to be done at compile time. A variable passed as the
* channel parameter will cause it to occur at run time.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a jhl 04/24/02 First release of low level driver
* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
* change required the functions to be changed such that
* the interface is not compatible with previous versions.
* See the examples in the example directory for macros
* to help compile an application that was designed for
* previous versions of the driver. The interrupt registers
* are accessible using the ReadReg and WriteReg macros and
* a channel parameter was added to the other macros.
* </pre>
*
******************************************************************************/
#ifndef XGPIO_L_H /* prevent circular inclusions */
#define XGPIO_L_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xbasic_types.h"
#include "xio.h"
/************************** Constant Definitions *****************************/
/** @name Registers
*
* Register offsets for this device. This device utilizes IPIF interrupt
* registers.
* @{
*/
#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction register for 1st channel */
#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction register for 2nd channel */
#define XGPIO_GIER_OFFSET 0x11C /**< Glogal interrupt enable register */
#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
/* @} */
/* The following constant describes the offset of each channels data and
* tristate register from the base address.
*/
#define XGPIO_CHAN_OFFSET 8
/** @name Interrupt Status and Enable Register bitmaps and masks
*
* Bit definitions for the interrupt status register and interrupt enable
* registers.
* @{
*/
#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Write a value to a GPIO register. A 32 bit write is performed. If the
* GPIO component is implemented in a smaller width, only the least
* significant data is written.
*
* @param BaseAddress is the base address of the GPIO device.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note None.
*
* C-style signature:
* void XGpio_mWriteReg(Xuint32 BaseAddress, unsigned RegOffset,
* Xuint32 Data)
*
****************************************************************************/
#define XGpio_mWriteReg(BaseAddress, RegOffset, Data) \
XIo_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))
/****************************************************************************/
/**
*
* Read a value from a GPIO register. A 32 bit read is performed. If the
* GPIO component is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the GPIO device.
* @param Register is the register offset from the base to read from.
* @param Data is the data from the register.
*
* @return None.
*
* @note None.
*
* C-style signature:
* Xuint32 XGpio_mReadReg(Xuint32 BaseAddress, unsigned RegOffset)
*
****************************************************************************/
#define XGpio_mReadReg(BaseAddress, RegOffset) \
XIo_In32((BaseAddress) + (RegOffset))
/*****************************************************************************
*
* Set the input/output direction of the signals of the specified GPIO channel.
*
* @param BaseAddress contains the base address of the GPIO device.
* @param Channel contains the channel (1 or 2) to operate on.
* @param DirectionMask is a bitmask specifying which discretes are input and
* which are output. Bits set to 0 are output and bits set to 1 are
* input.
*
* @return None.
*
* @note None.
*
* C-style signature:
* void XGpio_mSetDataDirection(Xuint32 BaseAddress, unsigned Channel,
* Xuint32 DirectionMask)
*
******************************************************************************/
#define XGpio_mSetDataDirection(BaseAddress, Channel, DirectionMask) \
XGpio_mWriteReg((BaseAddress), \
(((Channel) - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET, \
(DirectionMask))
/****************************************************************************/
/**
* Get the data register of the specified GPIO channel.
*
* @param BaseAddress contains the base address of the GPIO device.
* @param Channel contains the channel (1 or 2) to operate on.
*
* @return The contents of the data register.
*
* @note None.
*
* C-style signature:
* Xuint32 XGpio_mGetDataReg(Xuint32 BaseAddress, unsigned Channel)
*
*****************************************************************************/
#define XGpio_mGetDataReg(BaseAddress, Channel) \
XGpio_mReadReg((BaseAddress), \
(((Channel) - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET)
/****************************************************************************/
/**
* Set the data register of the specified GPIO channel.
*
* @param BaseAddress contains the base address of the GPIO device.
* @param Channel contains the channel (1 or 2) to operate on.
* @param Data is the value to be written to the data register.
*
* @return None.
*
* @note None.
*
* C-style signature:
* void XGpio_mSetDataReg(Xuint32 BaseAddress, unsigned Channel,
* Xuint32 Data)
*
*****************************************************************************/
#define XGpio_mSetDataReg(BaseAddress, Channel, Data) \
XGpio_mWriteReg((BaseAddress), \
(((Channel) - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,\
(Data))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#endif /* end of protection macro */
1.1 mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_selftest.c
http://www.opencores.org/cvsweb.shtml/mb-jpeg/microblaze_0/libsrc/gpio_v2_00_a/src/xgpio_selftest.c?rev=1.1&content-type=text/x-cvsweb-markup
Index: xgpio_selftest.c
===================================================================
/* $Id: xgpio_selftest.c,v 1.1 2006/06/23 19:03:41 quickwayne Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 - 2004 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/**
* @file xgpio_selftest.c
*
* The implementation of the XGpio component's self test function.
* See xgpio.h for more information about the component.
*
* @note
*
* None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a rmm 02/04/02 First release
* 2.00a jhl 01/13/04 Addition of dual channels and interrupts.
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xgpio.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
/******************************************************************************/
/**
* Run a self-test on the driver/device. This function does a minimal test
* in which the data register is read. It only does a read without any kind
* of test because the hardware has been parameterized such that it may be only
* an input such that the state of the inputs won't be known.
*
* All other hardware features of the device are not guaranteed to be in the
* hardware since they are parameterizable.
*
* ARGUMENTS:
*
* @param InstancePtr is a pointer to the XGpio instance to be worked on.
* This parameter must have been previously initialized with
* XGpio_Initialize().
*
* @return
*
* XST_SUCCESS always. If the GPIO device was not present in the hardware a bus
* error could be generated. Other indicators of a bus error, such as registers
* in bridges or buses, may be necessary to determine if this function caused
* a bus error.
*
* @note
*
* None.
*
******************************************************************************/
XStatus XGpio_SelfTest(XGpio *InstancePtr)
{
XASSERT_NONVOID(InstancePtr != XNULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
/* Read from the data register of channel 1 which is always guaranteed
* to be in the hardware device. Since the data may be configured as
* all inputs, there is not way to guarantee the value read so don't
* test it.
*/
(void)XGpio_DiscreteRead(InstancePtr, 1);
return(XST_SUCCESS);
}
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