OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Sun May 28 17:32:14 CEST 2006
Subject: [cvs-checkins] MODIFIED: t400 ...

Date: 00/06/05 28:17:32

Modified: t400/rtl/vhdl t400_decoder.vhd Log: execute virtual NOP at location 0x0ff when vectoring to interrupt routine Revision Changes Path 1.5 t400/rtl/vhdl/t400_decoder.vhd http://www.opencores.org/cvsweb.shtml/t400/rtl/vhdl/t400_decoder.vhd.diff?r1=1.4&r2=1.5 (In the diff below, changes in quantity of whitespace are not shown.) Index: t400_decoder.vhd =================================================================== RCS file: /cvsroot/arniml/t400/rtl/vhdl/t400_decoder.vhd,v retrieving revision 1.4 retrieving revision 1.5 diff -u -b -r1.4 -r1.5 --- t400_decoder.vhd 27 May 2006 19:14:18 -0000 1.4 +++ t400_decoder.vhd 28 May 2006 15:32:14 -0000 1.5 @@ -3,7 +3,7 @@ -- The decoder unit. -- Implements the instruction opcodes and controls all units of the T400 core. -- --- $Id: t400_decoder.vhd,v 1.4 2006/05/27 19:14:18 arniml Exp $ +-- $Id: t400_decoder.vhd,v 1.5 2006/05/28 15:32:14 arniml Exp $ -- -- Copyright (c) 2006 Arnim Laeuger (arniml@o...) -- @@ -210,9 +210,17 @@ -- instruction byte 1 and mnemonic info ------------------------------- if icyc_en_i and last_cycle_s then + if not ack_int_s then + -- update instruction descriptors in normal mode ibyte1_q <= pm_data_i; mnemonic_q <= mnemonic_s; multi_byte_q <= multi_byte_s; + else + -- force NOP instruction when vectoring to interrupt routine + ibyte1_q <= "01000100"; + mnemonic_q <= MN_NOP; + multi_byte_q <= false; + end if; end if; -- instruction byte 2 ------------------------------------------------- @@ -273,7 +281,7 @@ variable cyc_v : natural range 0 to 4; variable t41x_type_v, t420_type_v : boolean; - variable no_int_v : boolean; + variable en_int_v : boolean; begin -- default assignments pc_op_o <= PC_NONE; @@ -291,7 +299,7 @@ is_lbi_o <= false; set_en_s <= false; force_mc_s <= false; - no_int_v := false; + en_int_v := true; ack_int_s <= false; cyc_v := to_integer(cyc_cnt_q); -- determine type @@ -390,7 +398,7 @@ -- Mnemonic JID ------------------------------------------------------- when MN_JID => force_mc_s <= true; - no_int_v := true; + en_int_v := false; dec_data_o(byte_t'range) <= pm_data_i; if cyc_v = 1 then if not second_cyc_q then @@ -409,7 +417,7 @@ -- Mnemonic JMP ------------------------------------------------------- when MN_JMP => - no_int_v := true; + en_int_v := false; dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q; if second_cyc_q and cyc_v = 1 then pc_op_o <= PC_LOAD; @@ -417,7 +425,7 @@ -- Mnemonic JP_JSRP --------------------------------------------------- when MN_JP_JSRP => - no_int_v := true; + en_int_v := false; -- universal decoder data dec_data_o <= '0' & "01" & ibyte1_q(6 downto 0); if cyc_v = 1 then @@ -436,7 +444,7 @@ -- Mnemonic JSR ------------------------------------------------------- when MN_JSR => - no_int_v := true; + en_int_v := false; dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q; if second_cyc_q and cyc_v = 1 then pc_op_o <= PC_LOAD; @@ -445,7 +453,7 @@ -- Mnemonic RET ------------------------------------------------------- when MN_RET => - no_int_v := true; + en_int_v := false; if cyc_v = 1 then pc_op_o <= PC_POP; stack_op_o <= STACK_POP; @@ -458,7 +466,7 @@ -- Mnemonic RETSK ----------------------------------------------------- when MN_RETSK => - no_int_v := true; + en_int_v := false; if cyc_v = 1 then pc_op_o <= PC_POP; stack_op_o <= STACK_POP; @@ -515,7 +523,7 @@ -- Mnemonic LQID ------------------------------------------------------ when MN_LQID => force_mc_s <= true; - no_int_v := true; + en_int_v := false; if not second_cyc_q then -- first cycle: push PC and set PC from A/M, -- read IOL from program memory @@ -640,7 +648,7 @@ -- Mnemonic LBI ------------------------------------------------------- when MN_LBI => is_lbi_o <= true; - no_int_v := true; + en_int_v := false; dec_data_o(br_range_t) <= ibyte1_q(br_range_t); dec_data_o(bd_range_t) <= ibyte1_q(bd_range_t); if cyc_v = 1 and not skip_lbi_i then @@ -782,7 +790,7 @@ -- LBI if ibyte2_q(7 downto 6) = "10" and not t41x_type_v then is_lbi_o <= true; - no_int_v := true; + en_int_v := false; if cyc_v > 0 and not skip_lbi_i then b_op_o <= B_SET_B; skip_op_o <= SKIP_LBI; @@ -817,15 +825,15 @@ -- Interrupt handling ----------------------------------------------------- if t420_type_v and - en_q(1) = '1' and int_i and not no_int_v then + en_q(1) = '1' and int_i and en_int_v then if last_cycle_s then if cyc_v = 1 then - pc_op_o <= PC_INT; stack_op_o <= STACK_PUSH; end if; if icyc_en_i then ack_int_s <= true; io_in_op_o <= IOIN_INTACK; + pc_op_o <= PC_INT; -- push skip state that was determined by current instruction -- and will be valid for the next instruction which is delayed -- by the interrupt @@ -851,6 +859,9 @@ -- File History: -- -- $Log: t400_decoder.vhd,v $ +-- Revision 1.5 2006/05/28 15:32:14 arniml +-- execute virtual NOP at location 0x0ff when vectoring to interrupt routine +-- -- Revision 1.4 2006/05/27 19:14:18 arniml -- interrupt functionality added --