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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Wed Apr 26 02:42:05 CEST 2006
    Subject: [cvs-checkins] MODIFIED: mdct ...
    Top
    Date: 00/06/04 26:02:42

    Modified: mdct/source DBUFCTL.VHD DCT1D.vhd DCT2D.VHD MDCT.VHD
    Log:
    Redesigned. Fully pipelined, always ready for data design


    Revision Changes Path
    1.2 mdct/source/DBUFCTL.VHD

    http://www.opencores.org/cvsweb.shtml/mdct/source/DBUFCTL.VHD.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: DBUFCTL.VHD
    ===================================================================
    RCS file: /cvsroot/mikel262/mdct/source/DBUFCTL.VHD,v
    retrieving revision 1.1
    retrieving revision 1.2
    diff -u -b -r1.1 -r1.2
    --- DBUFCTL.VHD 15 Apr 2006 12:57:07 -0000 1.1
    +++ DBUFCTL.VHD 26 Apr 2006 00:42:04 -0000 1.2
    @@ -29,15 +29,12 @@
    port(
    clk : in STD_LOGIC;
    rst : in STD_LOGIC;
    - requestwr : in STD_LOGIC;
    - requestrd : in STD_LOGIC;
    - releasewr : in STD_LOGIC;
    - releaserd : in STD_LOGIC;
    + wmemsel : in STD_LOGIC;
    + rmemsel : in STD_LOGIC;
    + datareadyack : in STD_LOGIC;

    memswitchwr : out STD_LOGIC;
    memswitchrd : out STD_LOGIC;
    - reqwrfail : out STD_LOGIC;
    - reqrdfail : out STD_LOGIC;
    dataready : out STD_LOGIC
    );
    end DBUFCTL;
    @@ -46,89 +43,29 @@

    signal memswitchwr_reg : STD_LOGIC;
    signal memswitchrd_reg : STD_LOGIC;
    - signal mem1_full_reg : STD_LOGIC;
    - signal mem2_full_reg : STD_LOGIC;
    - signal mem1_lock_reg : STD_LOGIC;
    - signal mem2_lock_reg : STD_LOGIC;

    begin

    - dataready <= '1' when
    - ((mem1_lock_reg = '0' and mem1_full_reg = '1') or
    - (mem2_lock_reg = '0' and mem2_full_reg = '1')) else '0';
    -
    memswitchwr <= memswitchwr_reg;
    memswitchrd <= memswitchrd_reg;

    + memswitchrd_reg <= rmemsel;
    +
    MEM_SWITCH : process(rst,clk)
    begin
    if rst = '1' then
    memswitchwr_reg <= '0'; -- initially mem 1 is selected
    - memswitchrd_reg <= '0'; -- initially mem 1 is selected
    - mem1_full_reg <= '0';
    - mem2_full_reg <= '0';
    - mem1_lock_reg <= '0';
    - mem2_lock_reg <= '0';
    - reqrdfail <= '0';
    - reqwrfail <= '0';
    + dataready <= '0';
    elsif clk = '1' and clk'event then

    - -- write request by DCT1D
    - if requestwr = '1' then
    - -- if mem1 is free
    - if mem1_lock_reg = '0' and mem1_full_reg = '0' then
    - memswitchwr_reg <= '0';
    - mem1_lock_reg <= '1';
    - reqwrfail <= '0';
    - -- if mem2 is free
    - elsif mem2_lock_reg = '0' and mem2_full_reg = '0' then
    - memswitchwr_reg <= '1';
    - mem2_lock_reg <= '1';
    - reqwrfail <= '0';
    - else
    - reqwrfail <= '1';
    - end if;
    - end if;
    + memswitchwr_reg <= wmemsel;

    - -- write request released by DCT1D
    - if releasewr = '1' then
    - -- if mem1 locked by DCT1D release it
    - if mem1_lock_reg = '1' and memswitchwr_reg = '0' then
    - mem1_lock_reg <= '0';
    - mem1_full_reg <= '1';
    - -- if mem2 locked by DCT1D release it
    - elsif mem2_lock_reg = '1' and memswitchwr_reg = '1' then
    - mem2_lock_reg <= '0';
    - mem2_full_reg <= '1'; - end if; + if wmemsel /= memswitchwr_reg then + dataready <= '1'; end if; - -- read request by DCT2D - if requestrd = '1' then - if mem1_lock_reg = '0' and mem1_full_reg = '1' then - memswitchrd_reg <= '0'; - mem1_lock_reg <= '1'; - reqrdfail <= '0'; - elsif mem2_lock_reg = '0' and mem2_full_reg = '1' then - memswitchrd_reg <= '1'; - mem2_lock_reg <= '1'; - reqrdfail <= '0'; - else - reqrdfail <= '1'; - end if; - end if; - - -- read request released by DCT2D - if releaserd = '1' then - -- if mem1 locked by DCT2D release it - if mem1_lock_reg = '1' and memswitchrd_reg = '0' then - mem1_lock_reg <= '0'; - mem1_full_reg <= '0'; - -- if mem2 locked by DCT2D release it - elsif mem2_lock_reg = '1' and memswitchrd_reg = '1' then - mem2_lock_reg <= '0'; - mem2_full_reg <= '0'; - end if; + if datareadyack = '1' then + dataready <= '0'; end if; end if; 1.6 mdct/source/DCT1D.vhd http://www.opencores.org/cvsweb.shtml/mdct/source/DCT1D.vhd.diff?r1=1.5&r2=1.6 (In the diff below, changes in quantity of whitespace are not shown.) Index: DCT1D.vhd =================================================================== RCS file: /cvsroot/mikel262/mdct/source/DCT1D.vhd,v retrieving revision 1.5 retrieving revision 1.6 diff -u -b -r1.5 -r1.6 --- DCT1D.vhd 22 Apr 2006 01:41:24 -0000 1.5 +++ DCT1D.vhd 26 Apr 2006 00:42:04 -0000 1.6 @@ -55,9 +55,7 @@ romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); - reqwrfail : in STD_LOGIC; - ready : out STD_LOGIC; -- read from FIFO odv : out STD_LOGIC; dcto : out std_logic_vector(OP_W-1 downto 0); romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); @@ -81,8 +79,7 @@ ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); ramwe : out STD_LOGIC; - requestwr : out STD_LOGIC; - releasewr : out STD_LOGIC + wmemsel : out STD_LOGIC ); end DCT1D; @@ -91,43 +88,22 @@ -------------------------------------------------------------------------------- architecture RTL of DCT1D is - type STATE_T is - ( - MEMREQ, - IDLE, - GET_ROM, - SUM, - WRITE_ODD - ); - - type ISTATE_T is - ( - ACQUIRE_1ROW - ); - type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0); - signal ready_reg : STD_LOGIC; signal databuf_reg : INPUT_DATA; signal latchbuf_reg : INPUT_DATA; signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); - signal inpcnt_reg : UNSIGNED(2 downto 0); - signal state_reg : STATE_T; - signal istate_reg : ISTATE_T; - signal cnt_reg : UNSIGNED(3 downto 0); + signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); signal ramwe_s : STD_LOGIC; - signal latch_done_reg : STD_LOGIC; - signal latch_done_prev_reg : STD_LOGIC; - signal requestwr_reg : STD_LOGIC; - signal releasewr_reg : STD_LOGIC; - signal col_tmp_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal wmemsel_reg : STD_LOGIC; + signal stage2_reg : STD_LOGIC; + signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0); + signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); begin - ready_sg: - ready <= ready_reg; - ramwe_sg: ramwe <= ramwe_s; @@ -140,50 +116,41 @@ dcto_sg: dcto <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s; - releasewr_sg: - releasewr <= releasewr_reg; - requestwr_sg: - requestwr <= requestwr_reg; - - -------------------------------------- - -- PROCESS - -------------------------------------- - GET_PROC : process(rst,clk) + wmemsel_sg: + wmemsel <= wmemsel_reg; + + process(clk,rst) begin if rst = '1' then inpcnt_reg <= (others => '0'); - ready_reg <= '0'; latchbuf_reg <= (others => (others => '0')); - latch_done_reg <= '0'; databuf_reg <= (others => (others => '0')); - --latch_done_prev_reg <= '0'; + stage2_reg <= '0'; + stage2_cnt_reg <= (others => '1'); + ramdatai_s <= (others => '0'); + ramwe_s <= '0'; + ramwaddro <= (others => '0'); + col_reg <= (others => '0'); + row_reg <= (others => '0'); + wmemsel_reg <= '0'; + col_2_reg <= (others => '0'); elsif clk = '1' and clk'event then - --latch_done_prev_reg <= latch_done_reg; - - if latch_done_reg = '0' or - (state_reg=IDLE and reqwrfail='0' and latch_done_reg = '1') then - - -- wait until DCT1D_PROC process 1D DCT computation - -- before latching new 8 input words - if (state_reg = IDLE and reqwrfail = '0' and latch_done_reg = '1') then - latch_done_reg <= '0'; - end if; + stage2_reg <= '0'; + ramwe_s <= '0'; + -------------------------------- + -- 1st stage + -------------------------------- if idv = '1' then - -- read next data from input FIFO - ready_reg <= '1'; - if ready_reg = '1' then + inpcnt_reg <= inpcnt_reg + 1; + -- right shift input data latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1); latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT; - inpcnt_reg <= inpcnt_reg + 1; - if inpcnt_reg = N-1 then - latch_done_reg <= '1'; - ready_reg <= '0'; -- after this sum databuf_reg is in range of -256 to 254 (min to max) databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT); databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7); @@ -193,84 +160,17 @@ databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7); databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6); databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5); + stage2_reg <= '1'; end if; end if; - else - ready_reg <= '0'; - end if; - end if; - end if; - end process; - - -------------------------------------- - -- PROCESS - -------------------------------------- - DCT1D_PROC: process(rst, clk) - begin - if rst = '1' then - col_reg <= (others => '0'); - row_reg <= (others => '0'); - state_reg <= MEMREQ; - cnt_reg <= (others => '0'); - - ramwaddro <= (others => '0'); - ramdatai_s <= (others => '0'); - ramwe_s <= '0'; - releasewr_reg <= '0'; - col_tmp_reg <= (others => '0'); - requestwr_reg <= '0'; - elsif rising_edge(clk) then - - case state_reg is - - when MEMREQ => - - ramwe_s <= '0'; - - -- release memory fully written - releasewr_reg <= '0'; - - -- request free memory for writing - requestwr_reg <= '1'; - - -- DBUFCTL 1T delay - if requestwr_reg = '1' then - requestwr_reg <= '0'; - state_reg <= IDLE; - end if; - - ---------------------- - -- wait for input data - ---------------------- - when IDLE => - - ramwe_s <= '0'; - - -- failure to allocate any memory buffer - if reqwrfail = '1' then - -- restart allocation procedure - state_reg <= MEMREQ; - -- wait until 8 input words are latched in latchbuf_reg - -- by GET_PROC - elsif latch_done_reg = '1' then - state_reg <= SUM; - end if; + -------------------------------- - ---------------------- - -- get MAC results from ROM even and ROM odd memories - ---------------------- - when GET_ROM => - - ramwe_s <='0'; - - state_reg <= SUM; - - --------------------- - -- do distributed arithmetic sum on even part, - -- write even part to RAM - --------------------- - when SUM => + -------------------------------- + -- 2nd stage + -------------------------------- + if stage2_cnt_reg < N then + if stage2_cnt_reg(0) = '0' then ramdatai_s <= STD_LOGIC_VECTOR(RESIZE (RESIZE(SIGNED(romedatao0),DA_W) + (RESIZE(SIGNED(romedatao1),DA_W-1) & '0') + @@ -282,27 +182,7 @@ (RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") - (RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"), DA_W)(DA_W-1 downto 12)); - - -- write even part - ramwe_s <= '1'; - -- reverse col/row order for transposition purpose - ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg); - - col_reg <= col_reg + 1; - col_tmp_reg <= col_reg + 2; - - - state_reg <= WRITE_ODD; - - --------------------- - -- do distributed arithmetic sum on odd part, - -- write odd part to RAM - --------------------- - when WRITE_ODD => - - -- write odd part - --ramwe_s <= '1'; - + else ramdatai_s <= STD_LOGIC_VECTOR(RESIZE (RESIZE(SIGNED(romodatao0),DA_W) + (RESIZE(SIGNED(romodatao1),DA_W-1) & '0') + @@ -314,86 +194,86 @@ (RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") - (RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"), DA_W)(DA_W-1 downto 12)); + end if; - -- write odd part - -- reverse col/row order for transposition purpose - ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg); + stage2_cnt_reg <= stage2_cnt_reg + 1; - -- move to next column + -- write RAM + ramwe_s <= '1'; + -- reverse col/row order for transposition purpose + ramwaddro <= STD_LOGIC_VECTOR(col_2_reg & row_reg); + -- increment column counter col_reg <= col_reg + 1; - col_tmp_reg <= col_reg + 1; + col_2_reg <= col_2_reg + 1; -- finished processing one input row - if col_reg = N - 1 then + if col_reg = 0 then row_reg <= row_reg + 1; - col_reg <= (others => '0'); - col_tmp_reg <= (others => '0'); + -- switch to 2nd memory if row_reg = N - 1 then - releasewr_reg <= '1'; - state_reg <= MEMREQ; - else - state_reg <= IDLE; + wmemsel_reg <= not wmemsel_reg; + col_reg <= (others => '0'); end if; - else - state_reg <= SUM; end if; - -------------------------------- - -- OTHERS - -------------------------------- - when others => - state_reg <= IDLE; - end case; + + end if; + + if stage2_reg = '1' then + stage2_cnt_reg <= (others => '0'); + col_reg <= (0=>'1',others => '0'); + col_2_reg <= (others => '0'); + end if; + ---------------------------------- end if; end process; -- read precomputed MAC results from LUT - romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(0) & databuf_reg(1)(0) & databuf_reg(2)(0) & databuf_reg(3)(0); - romeaddro1 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(1) & databuf_reg(1)(1) & databuf_reg(2)(1) & databuf_reg(3)(1); - romeaddro2 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(2) & databuf_reg(1)(2) & databuf_reg(2)(2) & databuf_reg(3)(2); - romeaddro3 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(3) & databuf_reg(1)(3) & databuf_reg(2)(3) & databuf_reg(3)(3); - romeaddro4 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro4 <= STD_LOGIC_VECTOR( col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(4) & databuf_reg(1)(4) & databuf_reg(2)(4) & databuf_reg(3)(4); - romeaddro5 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(5) & databuf_reg(1)(5) & databuf_reg(2)(5) & databuf_reg(3)(5); - romeaddro6 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(6) & databuf_reg(1)(6) & databuf_reg(2)(6) & databuf_reg(3)(6); - romeaddro7 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(7) & databuf_reg(1)(7) & databuf_reg(2)(7) & databuf_reg(3)(7); - romeaddro8 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(8) & databuf_reg(1)(8) & databuf_reg(2)(8) & databuf_reg(3)(8); - -- odd romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(4)(0) & @@ -441,5 +321,6 @@ databuf_reg(6)(8) & databuf_reg(7)(8); + end RTL; -------------------------------------------------------------------------------- 1.5 mdct/source/DCT2D.VHD http://www.opencores.org/cvsweb.shtml/mdct/source/DCT2D.VHD.diff?r1=1.4&r2=1.5 (In the diff below, changes in quantity of whitespace are not shown.) Index: DCT2D.VHD =================================================================== RCS file: /cvsroot/mikel262/mdct/source/DCT2D.VHD,v retrieving revision 1.4 retrieving revision 1.5 diff -u -b -r1.4 -r1.5 --- DCT2D.VHD 22 Apr 2006 01:41:24 -0000 1.4 +++ DCT2D.VHD 26 Apr 2006 00:42:04 -0000 1.5 @@ -55,7 +55,6 @@ romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); - reqrdfail : in STD_LOGIC; dataready : in STD_LOGIC; odv : out STD_LOGIC; @@ -83,114 +82,89 @@ romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); - requestrd : out STD_LOGIC; - releaserd : out STD_LOGIC + rmemsel : out STD_LOGIC; + datareadyack : out STD_LOGIC ); end DCT2D; architecture RTL of DCT2D is - type STATE2_T is - ( - IDLE, - GET_ROM, - SUM, - WRITE_ODD - ); - - type ISTATE2_T is - ( - IDLE_I, - ACQUIRE_1ROW - ); - type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0); signal databuf_reg : input_data2; signal latchbuf_reg : input_data2; signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); - signal state_reg : STATE2_T; - signal istate_reg : ISTATE2_T; - signal cnt_reg : UNSIGNED(3 downto 0); - signal latch_done_reg : STD_LOGIC; + signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); - signal colram_reg : UNSIGNED(RAMADRR_W/2 downto 0); - signal requestrd_reg : STD_LOGIC; - signal releaserd_reg : STD_LOGIC; - signal completed_reg : STD_LOGIC; - signal col_tmp_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0); + signal rmemsel_reg : STD_LOGIC; + signal stage1_reg : STD_LOGIC; + signal stage2_reg : STD_LOGIC; + signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0); + signal dataready_2_reg : STD_LOGIC; begin ramraddro_sg: - ramraddro <= STD_LOGIC_VECTOR(rowram_reg & colram_reg(2 downto 0)); - - requestrd_sg: - requestrd <= requestrd_reg; + ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg); - releaserd_sg: - releaserd <= releaserd_reg; + rmemsel_sg: + rmemsel <= rmemsel_reg; - GET_PROC : process(rst,clk) + process(rst,clk) begin if rst = '1' then - rowram_reg <= (others => '0'); + stage2_cnt_reg <= (others => '1'); + rmemsel_reg <= '0'; + stage1_reg <= '0'; + stage2_reg <= '0'; colram_reg <= (others => '0'); + rowram_reg <= (others => '0'); + col_reg <= (others => '0'); + row_reg <= (others => '0'); latchbuf_reg <= (others => (others => '0')); - istate_reg <= IDLE_I; - latch_done_reg <= '0'; - completed_reg <= '0'; - requestrd_reg <= '0'; - releaserd_reg <= '0'; databuf_reg <= (others => (others => '0')); - elsif clk = '1' and clk'event then - case istate_reg is + dcto <= (others => '0'); + odv <= '0'; + colr_reg <= (others => '0'); + rowr_reg <= (others => '0'); + dataready_2_reg <= '0'; + elsif clk='1' and clk'event then - ---------------------- - -- IDLE - ---------------------- - when IDLE_I => - -- one of ram buffers has new data, process it - if dataready = '1' then - requestrd_reg <= '1'; - end if; - -- give 1T delay needed by DBUFCTL - if requestrd_reg = '1' then - requestrd_reg <= '0'; - istate_reg <= ACQUIRE_1ROW; - -- to account for 1T RAM delay, increment RAM address counter - colram_reg <= (0=>'1',others => '0'); - end if; + stage2_reg <= '0'; + odv <= '0'; + datareadyack <= '0'; + + dataready_2_reg <= dataready; + + ---------------------------------- + -- read DCT 1D to barrel shifer + ---------------------------------- + if stage1_reg = '1' then - ---------------------- - -- latch input data to barrel shifter - ---------------------- - when ACQUIRE_1ROW => - - if latch_done_reg = '0' then - -- not starting from zero b/c of RAM 1T delay - if colram_reg /= 0 then -- right shift input data latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1); latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1); - end if; colram_reg <= colram_reg + 1; + colr_reg <= colr_reg + 1; - -- not N-1 - if colram_reg = N then - -- finished reading 64 point 1D DCT from RAM + if colram_reg = N-2 then + rowr_reg <= rowr_reg + 1; + end if; + + if colram_reg = N-1 then + rowram_reg <= rowram_reg + 1; if rowram_reg = N-1 then + stage1_reg <= '0'; + colr_reg <= (others => '0'); -- release memory - releaserd_reg <= '1'; - completed_reg <= '1'; + rmemsel_reg <= not rmemsel_reg; end if; - colram_reg <= ( others => '0'); - rowram_reg <= rowram_reg + 1; - -- 8 point input latched - latch_done_reg <= '1'; + -- after this sum databuf_reg is in range of -256 to 254 (min to max) databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1); databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7); @@ -200,88 +174,18 @@ databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7); databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6); databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5); - end if; - -- failure to allocate memory buffer - -- should never happen? - if reqrdfail = '1' then - istate_reg <= IDLE_I; - end if; - else - releaserd_reg <= '0'; - -- wait until DCT1D_PROC process 1D DCT computation - -- before latching new 8 input words - if state_reg = IDLE then - latch_done_reg <= '0'; - if completed_reg = '1' then - completed_reg <= '0'; - colram_reg <= (others => '0'); - istate_reg <= IDLE_I; - else - istate_reg <= ACQUIRE_1ROW; - -- to account for 1T RAM delay, increment RAM address counter - colram_reg <= (0=>'1',others => '0'); - end if; - end if; + -- 8 point input latched + stage2_reg <= '1'; end if; - - when others => - istate_reg <= IDLE_I; - end case; end if; - end process; + -------------------------------- + -- 2nd stage + -------------------------------- + if stage2_cnt_reg < N then - DCT1D_PROC: process(rst, clk) - begin - if rst = '1' then - col_reg <= (others => '0'); - row_reg <= (others => '0'); - state_reg <= IDLE; - cnt_reg <= (others => '0'); - odv <= '0'; - dcto <= (others => '0'); - col_tmp_reg <= (others => '0'); - elsif rising_edge(clk) then - - case state_reg is - - ---------------------- - -- wait for input data - ---------------------- - when IDLE => - - odv <= '0'; - -- wait until 8 input words are latched in latchbuf_reg - -- by GET_PROC - if latch_done_reg = '1' then - - state_reg <= SUM; - end if; - - ---------------------- - -- get MAC results from ROM even and ROM odd memories - ---------------------- - when GET_ROM => - - odv <= '0'; - - state_reg <= SUM; - - --------------------- - -- do distributed arithmetic sum on even part, - -- write even part to RAM - --------------------- - when SUM => - - -- (a0 + - -- a1*2 + - -- (a2 + a3*2)*4 + - -- a4 * 2^4 + - -- a5*2 * 2^4 + - -- (a6 + - -- a7*2)*2^6 )/ - -- 2^11 + if stage2_cnt_reg(0) = '0' then dcto <= STD_LOGIC_VECTOR(RESIZE (RESIZE(SIGNED(romedatao0),DA2_W) + (RESIZE(SIGNED(romedatao1),DA2_W-1) & '0') + @@ -295,21 +199,7 @@ (RESIZE(SIGNED(romedatao9),DA2_W-9) & "000000000") - (RESIZE(SIGNED(romedatao10),DA2_W-10) & "0000000000"), DA2_W)(DA2_W-1 downto 12)); - - -- write even part - odv <= '1'; - - col_reg <= col_reg + 1; - col_tmp_reg <= col_reg + 2; - - state_reg <= WRITE_ODD; - - --------------------- - -- do distributed arithmetic sum on odd part, - -- write odd part to RAM - --------------------- - when WRITE_ODD => - + else dcto <= STD_LOGIC_VECTOR(RESIZE (RESIZE(SIGNED(romodatao0),DA2_W) + (RESIZE(SIGNED(romodatao1),DA2_W-1) & '0') + @@ -323,79 +213,96 @@ (RESIZE(SIGNED(romodatao9),DA2_W-9) & "000000000") - (RESIZE(SIGNED(romodatao10),DA2_W-10) & "0000000000"), DA2_W)(DA2_W-1 downto 12)); + end if; + + stage2_cnt_reg <= stage2_cnt_reg + 1; + + -- write RAM + odv <= '1'; + -- increment column counter col_reg <= col_reg + 1; - col_tmp_reg <= col_reg + 1; - -- finished processing one input row (1 x N) + -- finished processing one input row if col_reg = N - 1 then row_reg <= row_reg + 1; - col_reg <= (others => '0'); - col_tmp_reg <= (others => '0'); - state_reg <= IDLE; - else - state_reg <= SUM; end if; + end if; + + if stage2_reg = '1' then + stage2_cnt_reg <= (others => '0'); + col_reg <= (0=>'1',others => '0'); + end if; + -------------------------------- + + ---------------------------------- + -- wait for new data + ---------------------------------- + -- one of ram buffers has new data, process it + if dataready = '1' and dataready_2_reg = '0' then + stage1_reg <= '1'; + -- to account for 1T RAM delay, increment RAM address counter + colram_reg <= (others => '0'); + colr_reg <= (0=>'1',others => '0'); + datareadyack <= '1'; + end if; + ---------------------------------- - ----------------- - when others => - state_reg <= IDLE; - end case; end if; end process; -- read precomputed MAC results from LUT - romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(0) & databuf_reg(1)(0) & databuf_reg(2)(0) & databuf_reg(3)(0); - romeaddro1 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(1) & databuf_reg(1)(1) & databuf_reg(2)(1) & databuf_reg(3)(1); - romeaddro2 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(2) & databuf_reg(1)(2) & databuf_reg(2)(2) & databuf_reg(3)(2); - romeaddro3 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(3) & databuf_reg(1)(3) & databuf_reg(2)(3) & databuf_reg(3)(3); - romeaddro4 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(4) & databuf_reg(1)(4) & databuf_reg(2)(4) & databuf_reg(3)(4); - romeaddro5 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(5) & databuf_reg(1)(5) & databuf_reg(2)(5) & databuf_reg(3)(5); - romeaddro6 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(6) & databuf_reg(1)(6) & databuf_reg(2)(6) & databuf_reg(3)(6); - romeaddro7 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(7) & databuf_reg(1)(7) & databuf_reg(2)(7) & databuf_reg(3)(7); - romeaddro8 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(8) & databuf_reg(1)(8) & databuf_reg(2)(8) & databuf_reg(3)(8); - romeaddro9 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(9) & databuf_reg(1)(9) & databuf_reg(2)(9) & databuf_reg(3)(9); - romeaddro10 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) & + romeaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) & databuf_reg(0)(10) & databuf_reg(1)(10) & databuf_reg(2)(10) & 1.3 mdct/source/MDCT.VHD http://www.opencores.org/cvsweb.shtml/mdct/source/MDCT.VHD.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: MDCT.VHD =================================================================== RCS file: /cvsroot/mikel262/mdct/source/MDCT.VHD,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- MDCT.VHD 21 Apr 2006 02:02:17 -0000 1.2 +++ MDCT.VHD 26 Apr 2006 00:42:04 -0000 1.3 @@ -36,7 +36,7 @@ dcti : in std_logic_vector(IP_W-1 downto 0); idv : in STD_LOGIC; - ready : out STD_LOGIC; -- ready for input data + fiforead : out STD_LOGIC; -- ready for input data odv : out STD_LOGIC; dcto : out std_logic_vector(COE_W-1 downto 0); -- debug @@ -75,9 +75,7 @@ romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); - reqwrfail : in STD_LOGIC; - ready : out STD_LOGIC; -- read from FIFO odv : out STD_LOGIC; dcto : out std_logic_vector(OP_W-1 downto 0); romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); @@ -101,8 +99,7 @@ ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); ramwe : out STD_LOGIC; - requestwr : out STD_LOGIC; - releasewr : out STD_LOGIC + wmemsel : out STD_LOGIC ); end component; @@ -136,7 +133,6 @@ romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0); ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); - reqrdfail : in STD_LOGIC; dataready : in STD_LOGIC; odv : out STD_LOGIC; @@ -164,8 +160,8 @@ romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0); ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0); - requestrd : out STD_LOGIC; - releaserd : out STD_LOGIC + rmemsel : out STD_LOGIC; + datareadyack : out STD_LOGIC ); end component; @@ -215,15 +211,12 @@ port( clk : in STD_LOGIC; rst : in STD_LOGIC; - requestwr : in STD_LOGIC; - requestrd : in STD_LOGIC; - releasewr : in STD_LOGIC; - releaserd : in STD_LOGIC; + wmemsel : in STD_LOGIC; + rmemsel : in STD_LOGIC; + datareadyack : in STD_LOGIC; memswitchwr : out STD_LOGIC; memswitchrd : out STD_LOGIC; - reqwrfail : out STD_LOGIC; - reqrdfail : out STD_LOGIC; dataready : out STD_LOGIC ); end component; @@ -324,13 +317,10 @@ signal ramwe2_s : STD_LOGIC; signal memswitchrd_s : STD_LOGIC; signal memswitchwr_s : STD_LOGIC; -signal reqwrfail_s : STD_LOGIC; -signal reqrdfail_s : STD_LOGIC; +signal wmemsel_s : STD_LOGIC; +signal rmemsel_s : STD_LOGIC; signal dataready_s : STD_LOGIC; -signal requestwr_s : STD_LOGIC; -signal releasewr_s : STD_LOGIC; -signal requestrd_s : STD_LOGIC; -signal releaserd_s : STD_LOGIC; +signal datareadyack_s : STD_LOGIC; begin @@ -361,9 +351,7 @@ romodatao6 => romodatao6_s, romodatao7 => romodatao7_s, romodatao8 => romodatao8_s, - reqwrfail => reqwrfail_s, - ready => ready, odv => odv1, dcto => dcto1, romeaddro0 => romeaddro0_s, @@ -387,8 +375,7 @@ ramwaddro => ramwaddro_s, ramdatai => ramdatai_s, ramwe => ramwe_s, - requestwr => requestwr_s, - releasewr => releasewr_s + wmemsel => wmemsel_s ); ------------------------------ @@ -421,7 +408,6 @@ romodatao9 => romo2datao9_s, romodatao10 => romo2datao10_s, ramdatao => ramdatao_s, - reqrdfail => reqrdfail_s, dataready => dataready_s, odv => odv, @@ -449,8 +435,8 @@ romoaddro9 => romo2addro9_s, romoaddro10 => romo2addro10_s, ramraddro => ramraddro_s, - requestrd => requestrd_s, - releaserd => releaserd_s + rmemsel => rmemsel_s, + datareadyack => datareadyack_s ); ------------------------------ @@ -493,15 +479,12 @@ port map( clk => clk, rst => rst, - requestwr => requestwr_s, - requestrd => requestrd_s, - releasewr => releasewr_s, - releaserd => releaserd_s, + wmemsel => wmemsel_s, + rmemsel => rmemsel_s, + datareadyack => datareadyack_s, memswitchwr => memswitchwr_s, memswitchrd => memswitchrd_s, - reqwrfail => reqwrfail_s, - reqrdfail => reqrdfail_s, dataready => dataready_s );

     
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