OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Tue Apr 25 15:17:59 CEST 2006
Subject: [cvs-checkins] MODIFIED: can ...

Date: 00/06/04 25:15:17

Modified: can/bench/verilog can_testbench.v can_testbench_defines.v Log: New tests for testing the bus-off. Revision Changes Path 1.42 can/bench/verilog/can_testbench.v http://www.opencores.org/cvsweb.shtml/can/bench/verilog/can_testbench.v.diff?r1=1.41&r2=1.42 (In the diff below, changes in quantity of whitespace are not shown.) Index: can_testbench.v =================================================================== RCS file: /home/oc/cvs/can/bench/verilog/can_testbench.v,v retrieving revision 1.41 retrieving revision 1.42 diff -u -b -r1.41 -r1.42 --- can_testbench.v 11 Jul 2005 10:25:13 -0000 1.41 +++ can_testbench.v 25 Apr 2006 13:17:59 -0000 1.42 @@ -50,6 +50,9 @@ // CVS Revision History // // $Log: can_testbench.v,v $ +// Revision 1.42 2006/04/25 13:17:59 igorm +// New tests for testing the bus-off. +// // Revision 1.41 2005/07/11 10:25:13 igorm // Fixing overrun problems. // @@ -247,6 +250,7 @@ reg tx_bypassed; reg extended_mode; +event igor; // Instantiate can_top module can_top i_can_top @@ -330,12 +334,13 @@ wire tx_tmp1; wire tx_tmp2; -assign tx_tmp1 = bus_off_on? tx_i : 1'bz; -assign tx_tmp2 = bus_off2_on? tx2_i : 1'bz; +assign tx_tmp1 = bus_off_on? tx_i : 1'b1; +assign tx_tmp2 = bus_off2_on? tx2_i : 1'b1; assign tx = tx_tmp1 & tx_tmp2; + `ifdef CAN_WISHBONE_IF // Generate wishbone clock signal 10 MHz initial @@ -354,10 +359,12 @@ // Generate clock signal 25 MHz +// Generate clock signal 16 MHz initial begin clk=0; - forever #20 clk = ~clk; + //forever #20 clk = ~clk; + forever #31.25 clk = ~clk; end @@ -479,7 +486,7 @@ // test_full_fifo_ext; // test currently switched off // send_frame_ext; // test currently switched off // test_empty_fifo; // test currently switched off - test_full_fifo; // test currently switched off +// test_full_fifo; // test currently switched off // test_reset_mode; // test currently switched off // bus_off_test; // test currently switched off // forced_bus_off; // test currently switched off @@ -488,12 +495,236 @@ // self_reception_request; // test currently switched off // manual_frame_basic; // test currently switched off // manual_frame_ext; // test currently switched off +// error_test; +// register_test; + bus_off_recovery_test; + + +/* + #5000; + $display("\n\nStart rx/tx err cnt\n"); + -> igor; + + // Switch-off reset mode + $display("Rest mode ON"); + write_register(8'd0, {7'h0, (`CAN_MODE_RESET)}); + + $display("Set extended mode"); + extended_mode = 1'b1; + write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the extended mode + + $display("Rest mode OFF"); + write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + + write_register(8'd14, 8'hde); // rx err cnt + write_register(8'd15, 8'had); // tx err cnt + + read_register(8'd14, tmp_data); // rx err cnt + read_register(8'd15, tmp_data); // tx err cnt + + // Switch-on reset mode + $display("Switch-on reset mode"); + write_register(8'd0, {7'h0, `CAN_MODE_RESET}); + write_register(8'd14, 8'h12); // rx err cnt + write_register(8'd15, 8'h34); // tx err cnt + + read_register(8'd14, tmp_data); // rx err cnt + read_register(8'd15, tmp_data); // tx err cnt + + // Switch-off reset mode + $display("Switch-off reset mode"); + write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + + read_register(8'd14, tmp_data); // rx err cnt + read_register(8'd15, tmp_data); // tx err cnt + + // Switch-on reset mode + $display("Switch-on reset mode"); + write_register(8'd0, {7'h0, `CAN_MODE_RESET}); + + write_register(8'd14, 8'h56); // rx err cnt + write_register(8'd15, 8'h78); // tx err cnt + + // Switch-off reset mode + $display("Switch-off reset mode"); + write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + + read_register(8'd14, tmp_data); // rx err cnt + read_register(8'd15, tmp_data); // tx err cnt +*/ + #1000; $display("CAN Testbench finished !"); $stop; end +task bus_off_recovery_test; + begin + -> igor; + + // Switch-on reset mode + write_register(8'd0, {7'h0, (`CAN_MODE_RESET)}); + write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)}); + + // Set Clock Divider register + extended_mode = 1'b1; + write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended) + write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended) + + write_register(8'd16, 8'h00); // acceptance code 0 + write_register(8'd17, 8'h00); // acceptance code 1 + write_register(8'd18, 8'h00); // acceptance code 2 + write_register(8'd19, 8'h00); // acceptance code 3 + write_register(8'd20, 8'hff); // acceptance mask 0 + write_register(8'd21, 8'hff); // acceptance mask 1 + write_register(8'd22, 8'hff); // acceptance mask 2 + write_register(8'd23, 8'hff); // acceptance mask 3 + + write_register2(8'd16, 8'h00); // acceptance code 0 + write_register2(8'd17, 8'h00); // acceptance code 1 + write_register2(8'd18, 8'h00); // acceptance code 2 + write_register2(8'd19, 8'h00); // acceptance code 3 + write_register2(8'd20, 8'hff); // acceptance mask 0 + write_register2(8'd21, 8'hff); // acceptance mask 1 + write_register2(8'd22, 8'hff); // acceptance mask 2 + write_register2(8'd23, 8'hff); // acceptance mask 3 + + // Switch-off reset mode + write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + + // Enable all interrupts + write_register(8'd4, 8'hff); // irq enable register + + repeat (30) send_bit(1); + -> igor; + $display("(%0t) CAN should be idle now", $time); + + // Node 2 sends a message + write_register2(8'd16, 8'h83); // tx registers + write_register2(8'd17, 8'h12); // tx registers + write_register2(8'd18, 8'h34); // tx registers + write_register2(8'd19, 8'h45); // tx registers + write_register2(8'd20, 8'h56); // tx registers + write_register2(8'd21, 8'hde); // tx registers + write_register2(8'd22, 8'had); // tx registers + write_register2(8'd23, 8'hbe); // tx registers + + write_register2(8'd1, 8'h1); // tx request + + // Wait until node 1 receives rx irq + read_register(8'd3, tmp_data); + while (!(tmp_data & 8'h01)) begin + read_register(8'd3, tmp_data); + end + + $display("Frame received by node 1."); + + // Node 1 will send a message and will receive many errors + write_register(8'd16, 8'haa); // tx registers + write_register(8'd17, 8'haa); // tx registers + write_register(8'd18, 8'haa); // tx registers + write_register(8'd19, 8'haa); // tx registers + write_register(8'd20, 8'haa); // tx registers + write_register(8'd21, 8'haa); // tx registers + write_register(8'd22, 8'haa); // tx registers + write_register(8'd23, 8'haa); // tx registers + + fork + begin + write_register(8'd1, 8'h1); // tx request + end + + begin + // Waiting until node 1 starts transmitting + wait (!tx_i); + repeat (33) send_bit(1); + repeat (330) send_bit(0); + repeat (1) send_bit(1); + end + + join + + // Switch-off reset mode + write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + + repeat (1999) send_bit(1); + + // Switch-on reset mode + write_register(8'd0, {7'h0, (`CAN_MODE_RESET)}); + write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)}); + + write_register(8'd14, 8'h0); // rx err cnt + + // Switch-off reset mode + write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + + + // Wait some time before simulation ends + repeat (10000) @ (posedge clk); + end +endtask // bus_off_recovery_test + + +task error_test; + begin + // Switch-off reset mode + write_register(8'd0, {7'h0, (`CAN_MODE_RESET)}); + write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)}); + + // Set Clock Divider register + extended_mode = 1'b1; + write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended) + write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended) + + // Set error warning limit register + write_register(8'd13, 8'h56); // error warning limit + + // Switch-off reset mode + write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + + // Enable all interrupts + write_register(8'd4, 8'hff); // irq enable register + + repeat (300) send_bit(0); + + $display("Kr neki"); + + end +endtask + + +task register_test; + integer i, j, tmp; + begin + $display("Change mode to extended mode and test registers"); + // Switch-off reset mode + write_register(8'd0, {7'h0, (`CAN_MODE_RESET)}); + write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)}); + + // Set Clock Divider register + extended_mode = 1'b1; + write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended) + write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended) + + // Switch-off reset mode + write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); + + for (i=1; i<128; i=i+1) begin + for (j=0; j<8; j=j+1) begin + read_register(i, tmp_data); + write_register(i, tmp_data | (1 << j)); + end + end + + end +endtask + task forced_bus_off; // Forcing bus-off by writinf to tx_err_cnt register begin @@ -687,7 +918,7 @@ read_receive_buffer; release_rx_buffer_command; - #1000 read_register(8'd3); + #1000 read_register(8'd3, tmp_data); read_receive_buffer; release_rx_buffer_command; read_receive_buffer; @@ -867,7 +1098,7 @@ read_receive_buffer; release_rx_buffer_command; - #1000 read_register(8'd3); + #1000 read_register(8'd3, tmp_data); read_receive_buffer; release_rx_buffer_command; read_receive_buffer; @@ -900,6 +1131,12 @@ write_register(8'd22, 8'h00); // acceptance mask 2 write_register(8'd23, 8'h00); // acceptance mask 3 +//write_register(8'd14, 8'h7a); // rx err cnt +//write_register(8'd15, 8'h7a); // tx err cnt + +//read_register(8'd14, tmp_data); // rx err cnt +//read_register(8'd15, tmp_data); // tx err cnt + repeat (100) @ (posedge clk); // Switch-off reset mode @@ -1167,13 +1404,16 @@ read_receive_buffer; // Read irq register - #1 read_register(8'd3); + #1 read_register(8'd3, tmp_data); // Read error code capture register - read_register(8'd12); + read_register(8'd12, tmp_data); // Read error capture code register -// read_register(8'd12); +// read_register(8'd12, tmp_data); + +read_register(8'd14, tmp_data); // rx err cnt +read_register(8'd15, tmp_data); // tx err cnt #4000000; @@ -1264,9 +1504,11 @@ // Node is error passive now. // Read irq register (error interrupt should be cleared now. - read_register(8'd3); + read_register(8'd3, tmp_data); - repeat (20) +->igor; + + repeat (34) begin send_bit(0); // SOF @@ -1332,11 +1574,13 @@ send_bit(1); // SUSPEND end // repeat +->igor; + // Node is bus-off now // Read irq register (error interrupt should be cleared now. - read_register(8'd3); + read_register(8'd3, tmp_data); @@ -1351,7 +1595,7 @@ end // repeat // Read irq register (error interrupt should be cleared now. - read_register(8'd3); + read_register(8'd3, tmp_data); repeat (64 * 11) begin @@ -1361,7 +1605,7 @@ // Read irq register (error interrupt should be cleared now. - read_register(8'd3); + read_register(8'd3, tmp_data); end @@ -1524,7 +1768,7 @@ read_receive_buffer; // Read irq register - read_register(8'd3); + read_register(8'd3, tmp_data); #1000; end @@ -1658,10 +1902,10 @@ end // Read irq register - #1 read_register(8'd3); + #1 read_register(8'd3, tmp_data); // Read arbitration lost capture register - read_register(8'd11); + read_register(8'd11, tmp_data); end @@ -1673,7 +1917,7 @@ end // Read irq register - #1 read_register(8'd3); + #1 read_register(8'd3, tmp_data); end repeat(1) @@ -1684,7 +1928,7 @@ end // Read arbitration lost capture register - read_register(8'd11); + read_register(8'd11, tmp_data); end end @@ -1720,7 +1964,7 @@ read_receive_buffer; // Read irq register - read_register(8'd3); + read_register(8'd3, tmp_data); #1000; end @@ -1796,7 +2040,7 @@ read_receive_buffer; // Read irq register - read_register(8'd3); + read_register(8'd3, tmp_data); #1000; end @@ -2023,10 +2267,10 @@ fifo_info; // Read irq register - read_register(8'd3); + read_register(8'd3, tmp_data); // Read irq register - read_register(8'd3); + read_register(8'd3, tmp_data); #1000; end @@ -2271,6 +2515,7 @@ task read_register; input [7:0] reg_addr; + output [7:0] data; `ifdef CAN_WISHBONE_IF begin @@ -2285,6 +2530,7 @@ wb_we_i = 0; wait (wb_ack_o); $display("(%0t) Reading register [%0d] = 0x%0x", $time, wb_adr_i, wb_dat_o); + data = wb_dat_o; @ (posedge wb_clk_i); #1; wb_adr_i = 'hz; @@ -2314,6 +2560,7 @@ rd_i = 1; #158; $display("(%0t) Reading register [%0d] = 0x%0x", $time, can_testbench.i_can_top.addr_latched, port_0_i); + data = port_0_i; #1; rd_i = 0; cs_can = 0; @@ -2352,6 +2599,7 @@ end `else begin + $display("(%0t) Writing register [%0d] with 0x%0x", $time, reg_addr, reg_data); wait (port_free); port_free = 0; @ (posedge clk); @@ -2380,6 +2628,7 @@ task read_register2; input [7:0] reg_addr; + output [7:0] data; `ifdef CAN_WISHBONE_IF begin @@ -2394,6 +2643,7 @@ wb_we_i = 0; wait (wb_ack_o); $display("(%0t) Reading register [%0d] = 0x%0x", $time, wb_adr_i, wb_dat_o); + data = wb_dat_o; @ (posedge wb_clk_i); #1; wb_adr_i = 'hz; @@ -2423,6 +2673,7 @@ rd2_i = 1; #158; $display("(%0t) Reading register [%0d] = 0x%0x", $time, can_testbench.i_can_top.addr_latched, port_0_i); + data = port_0_i; #1; rd2_i = 0; cs_can2 = 0; @@ -2494,14 +2745,14 @@ if(extended_mode) // Extended mode begin for (i=8'd16; i<=8'd28; i=i+1) - read_register(i); + read_register(i, tmp_data); //if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun) // $display("\nWARNING: Above packet was received with overrun."); end else begin for (i=8'd20; i<=8'd29; i=i+1) - read_register(i); + read_register(i, tmp_data); //if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun) // $display("\nWARNING: Above packet was received with overrun."); end 1.10 can/bench/verilog/can_testbench_defines.v http://www.opencores.org/cvsweb.shtml/can/bench/verilog/can_testbench_defines.v.diff?r1=1.9&r2=1.10 (In the diff below, changes in quantity of whitespace are not shown.) Index: can_testbench_defines.v =================================================================== RCS file: /home/oc/cvs/can/bench/verilog/can_testbench_defines.v,v retrieving revision 1.9 retrieving revision 1.10 diff -u -b -r1.9 -r1.10 --- can_testbench_defines.v 30 Sep 2003 20:53:58 -0000 1.9 +++ can_testbench_defines.v 25 Apr 2006 13:17:59 -0000 1.10 @@ -50,6 +50,9 @@ // CVS Revision History // // $Log: can_testbench_defines.v,v $ +// Revision 1.10 2006/04/25 13:17:59 igorm +// New tests for testing the bus-off. +// // Revision 1.9 2003/09/30 20:53:58 mohor // Fixing the core to be Bosch VHDL Reference compatible. // @@ -86,12 +89,19 @@ `define CAN_MODE_RESET 1'h1 /* Reset mode */ /* Bit Timing 0 register value */ -`define CAN_TIMING0_BRP 6'h0 /* Baud rate prescaler (2*(value+1)) */ -`define CAN_TIMING0_SJW 2'h2 /* SJW (value+1) */ +//`define CAN_TIMING0_BRP 6'h0 /* Baud rate prescaler (2*(value+1)) */ +//`define CAN_TIMING0_SJW 2'h2 /* SJW (value+1) */ + +`define CAN_TIMING0_BRP 6'h3 /* Baud rate prescaler (2*(value+1)) */ +`define CAN_TIMING0_SJW 2'h1 /* SJW (value+1) */ /* Bit Timing 1 register value */ -`define CAN_TIMING1_TSEG1 4'h4 /* TSEG1 segment (value+1) */ -`define CAN_TIMING1_TSEG2 3'h3 /* TSEG2 segment (value+1) */ +//`define CAN_TIMING1_TSEG1 4'h4 /* TSEG1 segment (value+1) */ +//`define CAN_TIMING1_TSEG2 3'h3 /* TSEG2 segment (value+1) */ +//`define CAN_TIMING1_SAM 1'h0 /* Triple sampling */ + +`define CAN_TIMING1_TSEG1 4'hf /* TSEG1 segment (value+1) */ +`define CAN_TIMING1_TSEG2 3'h2 /* TSEG2 segment (value+1) */ `define CAN_TIMING1_SAM 1'h0 /* Triple sampling */